CN111863933B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111863933B
CN111863933B CN201910356554.8A CN201910356554A CN111863933B CN 111863933 B CN111863933 B CN 111863933B CN 201910356554 A CN201910356554 A CN 201910356554A CN 111863933 B CN111863933 B CN 111863933B
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layer
substrate
region
semiconductor
forming
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CN111863933A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Abstract

A semiconductor structure and method of forming the same, the method of forming comprising: forming a substrate, wherein the substrate comprises a diode region, the substrate comprises a substrate and a semiconductor column protruding out of the substrate, and first type ions are doped in the substrate and the semiconductor column; a doped layer is formed on the substrate of the diode region and the side wall of the semiconductor column, a second type ion is doped in the doped layer, and the second type ion is different from the first type ion in conductivity type. The embodiment of the invention is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous progress of semiconductor technology, semiconductor devices are being developed toward high integration and high quality, and feature sizes of semiconductor devices are correspondingly reduced. The reduction in feature size of semiconductor devices means that more semiconductor devices can be formed on the same chip.
Semiconductor diodes, also known as crystal diodes, are known as diodes (diodes), which are commonly used in the semiconductor field. A PN junction is arranged in the diode, and the electronic device has unidirectional conductivity according to the direction of an applied voltage. The PN junction in the diode is a p-n junction interface formed by a p-type semiconductor and an n-type semiconductor. Space charge layers are formed on two sides of the interface to form a self-built electric field. When the applied voltage is equal to zero, the diffusion current and the drift current caused by the self-built electric field are equal and are in an electric balance state due to the concentration difference of carriers at two sides of the p-n junction. Semiconductor diodes play an important role in many circuits and are also very widely used.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate, wherein the substrate comprises a diode region, the substrate comprises a substrate and a semiconductor column protruding out of the substrate, and first type ions are doped in the substrate and the semiconductor column; a doped layer is formed on the substrate of the diode region and the side wall of the semiconductor column, a second type ion is doped in the doped layer, and the second type ion is different from the first type ion in conductivity type.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: the substrate comprises a diode region, the substrate comprises a substrate and a semiconductor column protruding out of the substrate, and first type ions are doped in the substrate and the semiconductor column; and the doping layer is positioned on the substrate of the diode region and the side wall of the semiconductor column, and is doped with second type ions, wherein the second type ions are different from the first type ions in conductivity type.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the doped layer is positioned on the substrate of the diode region and the side wall of the semiconductor column, so that the contact area between the doped layer and the substrate is increased, and the area of a PN junction interface formed by the doped layer and the substrate is correspondingly increased, thereby improving the performance of a diode device and the capability of conducting electrostatic current (ESD current).
In an alternative scheme, the substrate further comprises a MOS region, the doped layer is further formed on the substrate of the MOS region, the doped layer on the substrate of the MOS region is used as a source region, and therefore the process steps of forming the MOS device and forming the diode device are integrated, the process flow is simplified, the manufacturing efficiency is improved, meanwhile, the source region is not formed at the bottom of a semiconductor column of the MOS region or in the substrate, the probability of diffusion of doped ions in the source region to a channel region is small, the short channel effect is improved, the doping concentration of the source region can be properly increased, the resistance of the source region and the contact resistance of the source region and a subsequent contact hole plug are reduced, and the performance of the MOS device is correspondingly improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic diagram of another semiconductor structure;
fig. 3 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reasons for poor performance of the device are analyzed by combining two semiconductor structures.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.
The semiconductor structure includes: a base (not labeled) including a diode region 1a, the base including a substrate 1 and a fin 2 protruding from the substrate 1, the fin 2 being doped with a first type of ion; and the doping layer 3 is positioned in the fin part 2, and ions of a second type are doped in the doping layer 3, and the second type ions are different from the first type ions in conductivity type.
The fin portion 2 of the diode region 1a and the doped layer 3 form a PN junction, and a contact surface of the fin portion 2 and the doped layer 3 is a PN junction interface. Along with further shrinking of the semiconductor structure, the width of the fin portion 2 is also continuously reduced, and the contact area between the fin portion 2 and the doped layer 3 is also smaller, that is, the area of the PN junction interface is smaller, which easily results in smaller on-current of the formed diode device, and the performance of the formed diode device is poorer.
Referring to fig. 2, a schematic structural diagram of another semiconductor structure is shown.
The semiconductor structure includes: a base (not shown) comprising a diode region a, the base comprising a substrate 6 and a semiconductor pillar 7 protruding from the substrate 6, the semiconductor pillar 7 of the diode region a being doped with ions of a first type; and a doped layer 8 is positioned on top of the semiconductor pillars 7.
Wherein the doped layer 8 of the diode region a and the semiconductor pillar 7 form a PN junction. The substrate further comprises a MOS region B, wherein the MOS region B is used for forming a Vertical Gate All Around (VGAA) MOS transistor, which is beneficial to further saving the area of a wafer and improving the performance of a MOS device. The doped layer 8 is also located at the top of the semiconductor column 7 of the MOS region B, and the doped layer 8 of the MOS region B is used as a drain region of the MOS device, so that the process steps of forming the MOS device and forming the diode device are integrated, which is beneficial to simplifying the process flow.
However, the contact area between the doped layer 8 and the semiconductor pillar 7 is still limited by the width dimension of the semiconductor pillar 7, and the area of the PN junction interface is small, which results in a small on-current of the formed diode device, which has poor performance.
In order to solve the technical problem, the embodiment of the invention increases the contact area of the doped layer and the substrate by locating the doped layer on the substrate of the diode region and the side wall of the semiconductor column, and correspondingly increases the area of the PN junction interface formed by the doped layer and the substrate, thereby improving the performance of the diode device and the capability of conducting electrostatic current.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3 to 6, a base (not shown) including a diode region I is formed, the base including a substrate 100 (shown in fig. 6) and a semiconductor pillar 110 (shown in fig. 6) protruding from the substrate 100, the substrate 100 and the semiconductor pillar 110 being doped with a first type of ions.
The substrate of the diode region I is used to form a diode device. In this embodiment, the substrate further includes a MOS region II, where the substrate of the MOS region II is used to form a MOS device.
In this embodiment, the diode region I and the MOS region II are adjacent regions. In other embodiments, the diode region and the MOS region may be non-adjacent regions.
The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures. The substrate 100 in the diode region I is used to form a P-type doped region or an N-type doped region of the diode device.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The semiconductor column 110 in the diode region I is used for forming a P-type doped region or an N-type doped region of the diode device, and the semiconductor column 110 in the diode region I is also used for providing a process platform for the subsequent formation of a doped layer; the semiconductor column 110 of the MOS region I is used to provide a process platform for forming a MOS device later, and the semiconductor column 110 of the MOS region I is also used to form a channel region when the MOS device is in operation.
In this embodiment, the semiconductor pillars 110 are made of the same material as the substrate 100, and the semiconductor pillars 110 are made of silicon. In other embodiments, the semiconductor pillars and the substrate material may also be different according to actual process requirements, and the material of the semiconductor pillars may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The substrate 100 and the semiconductor pillars 110 are doped with a first type of ion.
When the substrate 100 and the semiconductor pillar 110 of the diode region I are used As N-type doped regions of the diode device, the first type ions are N-type ions, wherein the N-type ions may be P ions, as ions, or Sb ions; accordingly, the substrate of the MOS region II is used to form a PMOS transistor. When the substrate 100 and the semiconductor pillar 110 of the diode region I are used as P-type doped regions of the diode device, the first type ions are P-type ions, wherein the P-type ions may be B ions, ga ions, or In ions; accordingly, the substrate of the MOS region II is used to form an NMOS transistor.
Specifically, the step of forming the substrate includes:
as shown in fig. 3, a semiconductor layer 10 is provided. The semiconductor layer 10 is used for subsequent formation of a substrate and semiconductor pillars. Accordingly, the semiconductor layer 10 is also doped with ions of the first type.
Therefore, in the present embodiment, the material of the semiconductor layer 10 is silicon. In other embodiments, the material of the semiconductor layer may be other suitable materials, depending on the actual desired substrate and semiconductor pillar materials. In other embodiments, the semiconductor layer may further include a first semiconductor layer for forming the substrate and a second semiconductor layer on the first semiconductor layer for forming the semiconductor pillars.
With continued reference to fig. 3, a layer of hard mask material 101 is formed on the semiconductor layer 10.
The hard mask material layer 101 is subjected to a subsequent patterning step to form a hard mask layer, thereby serving as an etching mask for forming a substrate and a semiconductor pillar. In this embodiment, the material of the hard mask material layer 101 is silicon nitride.
As shown in fig. 4, the semiconductor layer 10 is patterned (as shown in fig. 3) to form an initial base (not shown) including an initial substrate 11 and initial semiconductor pillars 12 protruding from the initial substrate 11.
The initial substrate 11 is used for the subsequent formation of the substrate; the initial semiconductor pillars 12 are used for subsequent formation of semiconductor pillars.
Specifically, before patterning the semiconductor layer 10, it further includes: the hard mask material layer 101 is patterned to form a hard mask layer 102. Accordingly, the semiconductor layer 10 is patterned using the hard mask layer 102 as a mask.
As shown in fig. 5, a protective layer 103 is formed on the sidewalls of the initial semiconductor pillars 12.
The subsequent process further comprises: after etching back a partial thickness of the initial substrate 11 to form a substrate and a semiconductor pillar, the protective layer 103 is used as an etching mask in this etching step; and the protective layer 103 covers part of the side wall of the semiconductor column, so that in the subsequent step of forming the doped layer, the protective layer 103 can also play a role in protecting part of the side wall of the semiconductor column, thereby providing a process foundation for the subsequent formation of the gate structure surrounding part of the side wall of the semiconductor column.
In the semiconductor field, an epitaxial process is typically used to form the doped layer. Therefore, the protective layer 103 is different from the material of the initial substrate 11 or the initial semiconductor pillar 12.
The material of the protective layer 103 may be silicon nitride, silicon oxide, silicon oxynitride, boron nitride, or silicon carbonitride. In this embodiment, the material of the protection layer 103 is silicon nitride. Silicon nitride is a material commonly used in semiconductor processing, and has high process compatibility, and the silicon nitride material has high etching selectivity with the material of the initial semiconductor column 12, so that the protective layer 103 can be removed conveniently.
The protective layer 103 should not be too thin nor too thick. If the protective layer 103 is too thin, in the subsequent step of forming the doped layer, the protective layer 103 is difficult to play a role in protecting the semiconductor pillars in the MOS region II, and the thickness of the protective layer 103 is too small to easily reduce the covering capability of the protective layer 103, thereby reducing the formation quality of the protective layer 103; if the protective layer 103 is too thick, process time and materials are easily wasted, the difficulty in removing the protective layer 103 later increases, and when the distance between adjacent initial semiconductor pillars 12 is too close, the sidewalls of the protective layer 103 on the sidewalls of adjacent initial semiconductor pillars 12 are easily contacted. For this reason, in the present embodiment, the thickness of the protective layer 103 is 3 nm to 10 nm.
In this embodiment, the step of forming the protective layer 103 includes: forming a protective material layer (not shown) conformally covering the initial substrate 11 and the initial semiconductor pillars 12; and removing the protective material layer on the initial substrate 11 and at the top of the initial semiconductor column 12, and taking the remaining protective material layer as the protective layer 103.
In this embodiment, the atomic layer deposition process is used to form the protective material layer, which is favorable for improving the conformal covering capability of the protective material layer and the thickness uniformity of the protective material layer, and accordingly improves the quality of the protective layer 103.
In this embodiment, a maskless etching (mask etching) process is used to remove the protective material layer on the initial substrate 11 and on the top of the initial semiconductor pillar 12, so that the operation steps are simple and the process cost is low. Specifically, a maskless dry etching process is adopted to perform a maskless etching process. The dry etching process is adopted to realize anisotropic etching easily by adjusting parameters such as bias voltage, process pressure and the like.
As shown in fig. 6, after the protective layer 103 is formed, the initial substrate 11 is etched back to a partial thickness to form the substrate 100 and the semiconductor pillars 110. Specifically, the initial substrate 11 is etched using the protective layer 109 as a mask.
The protection layer 103 is exposed from a portion of the sidewall of the MOS region II semiconductor pillar 110 near the side of the substrate 100 by etching back a portion of the thickness of the initial substrate 11, so as to define a formation region of a subsequent doped layer on the MOS region II semiconductor pillar 110. Thus, the amount of etching of the initial substrate 11 is dependent on the subsequently required thickness of the doped layer.
Specifically, an anisotropic dry etching process is used to etch back a portion of the thickness of the initial substrate 11. The dry etching process is favorable for accurately controlling the etching amount of the initial substrate 11, so that the height of the side wall of the MOS region II semiconductor column 110 exposed by the protective layer 103 meets the process requirement, and the forming thickness of the subsequent doped layer is correspondingly favorable for accurately controlling.
Referring to fig. 7 in combination, after etching back the initial substrate 11 with a partial thickness, before removing the protective layer 103 on the diode region I, the method further includes: the semiconductor pillars 110 at the bottom of the protective layer 103 are laterally etched.
After the protective layer 103 is used as a mask to etch back the initial substrate 11 with partial thickness, the formed semiconductor column 110 is in an inverted T shape, and the semiconductor column 110 at the bottom of the protective layer 103 is laterally etched, so that the semiconductor column 110 has a steep side wall, and the uniformity of the width dimension of the semiconductor column 110 is good; after the doped layer is formed subsequently, the doped layer of the MOS region II surrounds the side wall of the semiconductor column 110 exposed by the protective layer 103, and the distance between the doped layer of the MOS region II and the channel region is relatively short, so that the resistance of the source region of the MOS device and the contact resistance between the plug of the subsequent contact hole and the source region are reduced.
In this embodiment, the semiconductor pillars 110 at the bottom of the protective layer 103 are laterally etched using an isotropic dry etching process. Isotropic etching can be realized by adjusting the bias voltage, the process pressure and other process parameters of the dry etching process, and the dry etching process has higher process stability and controllability, thereby being beneficial to precisely controlling the transverse etching amount.
In other embodiments, according to actual requirements, a wet etching process or a process combining dry etching and wet etching may be used to laterally etch the semiconductor pillar at the bottom of the protective layer.
Referring to fig. 8 in combination, after forming the substrate 100 and the semiconductor pillars 110, the method further includes: the protective layer 103 on the diode region I is removed.
The sidewall of the diode region I semiconductor pillar 110 is exposed by removing the protective layer 103 of the diode region I, in preparation for the subsequent formation of a doped layer on the sidewall of the diode region I semiconductor pillar 110 and the substrate 100.
Specifically, a cover layer (not shown) is formed to cover the MOS region II; removing the protective layer 103 exposed by the cover layer; and removing the covering layer. In this embodiment, the material of the cover layer is photoresist. Accordingly, a photolithographic process is employed to form the cap layer.
In this embodiment, a wet etching process is used to remove the protection layer 103 on the diode region I. The wet etching process is easy to realize a large etching selectivity and isotropic etching, is easy to remove the protective layer 103 on the side wall of the diode region I semiconductor column 110, and has simple process and low process cost. In other embodiments, according to the actual process, an isotropic dry etching process may also be used to remove the protective layer on the diode region.
In this embodiment, an ashing process is used to remove the cover layer.
Referring to fig. 9, a doped layer 104 is formed on sidewalls of the substrate 100 and the semiconductor pillar 110 of the diode region I, the doped layer 104 is doped with a second type of ions, and the second type of ions is different from the first type of ions in conductivity type.
By locating the doped layer 104 on the sidewall of the substrate 100 and the semiconductor pillar 110 of the diode region I, the contact area between the doped layer 104 and the substrate is increased, and the area of the PN junction interface formed by the doped layer 104 and the substrate is correspondingly increased, thereby improving the performance of the diode device and the capability of conducting electrostatic current.
The doped layer 104 of diode region I is used as an N-type or P-type doped region of the diode device.
Specifically, when the substrate 100 and the semiconductor pillar 110 are used as N-type doped regions of the diode device, the doped layer 104 of the diode region I is used as a P-type doped region, and the second type of ions are P-type ions, wherein the P-type ions may be B ions, ga ions, or In ions. Accordingly, the material of doped layer 104 may be silicon germanium doped with P-type ions.
When the substrate 100 and the semiconductor pillars 110 are used As P-type doped regions of a diode device, the doped layer 104 of the diode region I is used As an N-type doped region, and the second type of ions are N-type ions, where the N-type ions may be P ions, as ions, or Sb ions. Accordingly, the material of doped layer 104 may be silicon carbide or silicon phosphide doped with N-type ions.
In this embodiment, an epitaxial process is used to form an epitaxial layer, and in-situ autodoping process ions form doped layer 104 during the formation of the epitaxial layer. The manner of forming the epitaxial layer and forming the doped layer 104 by adopting an in-situ self-doping process is beneficial to improving the formation quality of the doped layer 104 and preventing the damage of ion doping treatment to the epitaxial layer.
Therefore, the epitaxial layer is formed by performing epitaxial growth based on the substrate 100, the sidewall of the semiconductor pillar 110 in the diode region I, and the sidewall of the semiconductor pillar 110 in the MOS region II exposed by the protective layer 103. Accordingly, in the step of forming the doped layer 104, the doped layer 104 is further formed on the substrate 100 of the MOS region II, and the doped layer 104 on the substrate 100 of the MOS region II serves as a source region (not shown).
By forming the source region of the MOS device and the doped layer 104 of the diode device in the same step, the process steps of forming the MOS device and forming the diode device are integrated, which is beneficial to simplifying the process flow and improving the manufacturing efficiency, meanwhile, the source region is not formed at the bottom of the MOS region II semiconductor pillar 110 or in the substrate 100, the probability of diffusing doped ions in the source region to the channel region is smaller, which is beneficial to improving the short channel effect, and the embodiment can properly increase the doping concentration of the source region, is beneficial to reducing the resistance of the source region and the contact resistance of the source region and the subsequent contact hole plug, and correspondingly improves the performance of the MOS device.
The doped layer 104 is preferably not too thin or too thick. If the doped layer 104 is too thin, the volume of the doped layer 104 is correspondingly too small, which tends to increase the resistance of the semiconductor structure; if the doped layer 104 is too thick, process time and process materials are easily wasted, and the exposed height of the MOS region II semiconductor pillar 110 of the doped layer 104 is easily reduced, the portion of the MOS region II semiconductor pillar 110 for providing a conductive channel is correspondingly reduced, which easily affects the performance of the formed MOS device, for example: resulting in an aggravation of short channel effects, etc. For this reason, in the present embodiment, the thickness of the doped layer 104 is 4 nm to 12 nm.
In this embodiment, a protection layer 103 is formed on the sidewall of the MOS region II semiconductor pillar 110, and the protection layer 103 exposes a portion of the sidewall of the MOS region II semiconductor pillar 100 near the substrate 100. Accordingly, doped layer 104 surrounds the sidewalls of MOS region II semiconductor pillars 110 exposed by protective layer 103.
It should be noted that, referring to fig. 10, after forming the doped layer 104, the method further includes: and removing the doped layer 104 at the junction of the diode region I and the MOS region II. The doped layer 104 at the junction of the diode region I and the MOS region II is removed, so that the electrical isolation of the diode region I and the MOS region II is realized.
Specifically, a dry etching process is used to remove the doped layer 104 at the junction of the diode region I and the MOS region II.
With continued reference to fig. 10, after removing the doped layer 104 at the junction of the diode region I and the MOS region II, the method further includes: the exposed portion of the thickness of the substrate 100 of the remaining doped layer 104 is removed, forming a recess 200 in the substrate 100.
By forming the groove 200, the substrate 100 at the junction of the diode region I and the MOS region II is further isolated, and the step of forming a dielectric layer on the substrate 100 exposed by the semiconductor pillar 110 is further included, and the material of the dielectric layer can be filled into the groove 200 correspondingly, which is beneficial to improving the effect of electrical isolation between the diode device and the MOS device.
Accordingly, in the step of removing the doped layer 104 at the junction of the diode region I and the MOS region II, the process parameters and the etching gas type of the dry etching process are adjusted, so that the substrate 100 with a partial thickness exposed by the remaining doped layer 104 is removed in the same etching machine.
Referring to fig. 11 to 13 in combination, after forming the doped layer 104, the method further includes: at least a portion of the protective layer 103 is removed, exposing a portion of the sidewall of the MOS region II semiconductor pillar 110 near the top side, so as to prepare for the subsequent formation of a gate structure surrounding the sidewall of the MOS region II semiconductor pillar 110.
In this embodiment, after forming the doped layer 104, the method further includes: as shown in fig. 11, a first dielectric layer 105 is formed on the substrate 100 where the semiconductor pillars 110 are exposed, covering the top of the semiconductor pillars 110; as shown in fig. 12, the first dielectric layer 105 is etched back to a partial thickness on the MOS region II, exposing a partial sidewall of the MOS region II semiconductor pillar 110 near the top side.
The first dielectric layer 105 is used to isolate adjacent devices. After etching back the first dielectric layer 105 with a partial thickness on the MOS region II, the first dielectric layer 105 on the MOS region II is further used to isolate the source region from a subsequent gate structure; moreover, the first dielectric layer 105 can protect the diode region I, so as to reduce the influence of the subsequent gate structure forming process on the diode region I, thereby reducing the influence on the performance of the diode device.
In this embodiment, the material of the first dielectric layer 105 is silicon oxide. In other embodiments, the material of the first dielectric layer may be silicon nitride, silicon oxynitride, or other insulating materials.
In this embodiment, a groove 200 is formed in the substrate 100 at the junction of the diode region I and the MOS region II (as shown in fig. 10), so in the step of forming the first dielectric layer 105, the material of the first dielectric layer 105 is also filled in the groove 200, thereby improving the isolation effect between the diode device and the MOS device.
Specifically, a dry etching process is used to etch back a portion of the thickness of the first dielectric layer 105 over the MOS region II.
In this embodiment, before etching back the first dielectric layer 105 with a partial thickness on the MOS region II, the method further includes: forming a first mask layer (not shown) covering the first dielectric layer 105 of the diode region I; etching back the first dielectric layer 105 with partial thickness on the MOS region II by taking the first mask layer as a mask; and removing the first mask layer.
The first mask layer is used for protecting the first dielectric layer 105 of the diode region I. For a detailed description of the first mask layer, reference may be made to the foregoing description of the cover layer, which is not repeated herein.
In this embodiment, after etching back the first dielectric layer 105 with a partial thickness on the MOS region II, the protection layer 103 on the partial sidewall of the semiconductor pillar 110 of the MOS region II is exposed.
Accordingly, referring to fig. 13 in combination, the step of removing at least a portion of the protective layer 103 includes: and removing the protection layer 103 exposed by the first dielectric layer 105 of the MOS region II.
By removing the protective layer 103 exposed by the first dielectric layer 105 of the MOS region II after the first dielectric layer 105 is formed, the first dielectric layer 105 can protect the semiconductor pillar 110 and the doped layer 104 of the diode region I in the step of removing the protective layer 103 exposed by the first dielectric layer 105 of the MOS region II, thereby reducing an influence on the diode region I.
In this embodiment, an isotropic dry etching process is used to remove the protection layer 103 exposed by the first dielectric layer 105 in the MOS region II. Isotropic etching can be realized by adjusting the bias voltage, the process pressure and other process parameters of the dry etching process, and the dry etching process has higher process stability and controllability, so that the influence of the process for removing the protective layer 103 on other film structures (such as the semiconductor column 110) is reduced.
In this embodiment, the process of etching back the first dielectric layer 105 with the partial thickness of the MOS region II has a larger etching selectivity to the first dielectric layer 105 and the protective layer 103, so that the first dielectric layer 105 and the protective layer 103 are etched in different steps, respectively. In other embodiments, when the etching rates of the material of the protective layer and the material of the first dielectric layer are relatively close, the first dielectric layer and the protective layer may be etched in the same step, respectively.
Referring to fig. 14 to fig. 16, after removing the protective layer 103 exposed by the first dielectric layer 105 of the MOS region II, the method further includes: a gate structure 120 is formed to surround the exposed sidewall of the MOS region II semiconductor pillar 110 of the doped layer 104 (as shown in fig. 16), and the gate structure 120 exposes at least the top of the MOS region II semiconductor pillar 110.
The gate structure 120 is used for controlling the on/off of the conducting channel when the MOS device is operated.
In this embodiment, the gate structure 120 is a metal gate structure. As shown in fig. 16, the gate structure 120 includes a gate oxide layer 121 surrounding the sidewall of the MOS region II semiconductor pillar 110 where the doped layer 104 is exposed, a high-k gate dielectric layer 122 surrounding the gate oxide layer 121, a work function layer 123 surrounding the high-k gate dielectric layer 122, and a gate electrode layer 124 surrounding the work function layer 123.
In this embodiment, the gate oxide layer 121 is made of silicon oxide.
In this embodiment, the material of the high-k gate dielectric layer 122 is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 122 is HfO 2 . In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
When the MOS device is an NMOS transistor, the material of the work function layer 123 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when the MOS device formed is a PMOS transistor, the material of the work function layer 123 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the material of the gate electrode layer 124 is magnesium-tungsten alloy. In other embodiments, the material of the gate electrode layer may also be W, al, cu, ag, au, pt, ni or Ti.
In this embodiment, the step of forming the gate structure 120 includes:
as shown in fig. 14, a gate oxide material layer 106 surrounding the exposed side wall of the MOS region II semiconductor pillar 110 of the protective layer 103 is formed; forming a high-k dielectric material layer 107 covering the gate oxide material layer 106, the hard mask layer 102 and the MOS region II first dielectric layer 105 in a conformal manner; forming a work function material layer 108 conformally covering the high-k dielectric material layer 107; a gate electrode material layer 109 is formed conformally overlying the work function material layer 108.
As shown in fig. 15, the gate electrode material layer 109, the work function material layer 108 and the high-k dielectric material layer 107 on the top of the portion of the first dielectric layer 105 far from the junction of the diode region I and the MOS region II are removed, and a portion of the top of the first dielectric layer 105 is exposed, so as to prepare for the subsequent formation of a source contact plug electrically connected to the source region.
With continued reference to fig. 15, after removing the gate electrode material layer 109, the work function material layer 108, and the high-k dielectric material layer 107 on the top of the portion of the first dielectric layer 105 away from the junction of the diode region I and the MOS region II, a dielectric material layer 111 is formed that covers the remaining gate electrode material layer 109 and the first dielectric layer 105.
The dielectric material layer 111 is used to subsequently form a second dielectric layer to achieve electrical isolation between adjacent devices. In this embodiment, the material of the dielectric material layer 111 is silicon oxide. For the description of the dielectric material layer 111, reference may be made to the foregoing detailed description of the first dielectric layer 105, which is not repeated herein.
As shown in fig. 16, the top of the semiconductor pillar 110 is used as a stop position, the dielectric material layer 111, the gate electrode material layer 109, the work function material layer 108 and the high-k dielectric material layer 107 are planarized, the remaining dielectric material layer 111 is used as the second dielectric layer 112, the gate oxide material layer 106 is used as the gate oxide layer 121, and the remaining high-k dielectric material layer 107 is used as the high-k dielectric layer 122.
The second dielectric layer 112 also serves to achieve electrical isolation between adjacent devices. In the planarization process, the hard mask layer 102 and the first dielectric layer 105 with the thickness of the diode region I are also removed, and the remaining first dielectric layer 105 and the second dielectric layer 112 are used as bottom dielectric layers (not labeled). Specifically, the bottom dielectric layer exposes the top of semiconductor pillars 110.
With continued reference to fig. 16, after the second dielectric layer 112 is formed, a portion of the work function material layer 108 and the gate electrode material layer 109 are etched back, the remaining work function material layer 108 serves as a work function layer 123, the remaining gate electrode material layer 109 serves as the gate electrode layer 124, and the gate electrode layer 124, the work function layer 123, the high-k dielectric layer 122, and the gate oxide layer 121 form the gate structure 120.
After etching back the work function layer 108 and the gate electrode material layer 109, a portion of the sidewall of the MOS region II semiconductor pillar 110 near the top side is exposed, thereby electrically isolating the gate structure 120 from the drain region formed subsequently.
In this embodiment, the work function material layer 108 and the gate electrode material layer 109 are etched by a dry etching process. Specifically, the dry etching process has a larger etching selectivity to the work function material layer 108 and the gate electrode material layer 109, and the semiconductor pillar 110, the gate oxide layer 121, the high-k dielectric layer 122, the bottom dielectric layer, and the doped layer 104, so that the work function material layer 108 and the gate electrode material layer 109 with partial thicknesses can be etched by using a maskless dry etching process, and accordingly, the cost is saved.
Referring to fig. 17 in combination, after forming the gate structure 120, further includes: a drain region 114 is formed on top of the MOS region II semiconductor pillar 110. The drain region 114 is of the same material as the source region and is doped with the same type of ion.
Specifically, when forming a PMOS transistor, the material of the drain region 114 may be silicon germanium doped with P-type ions; wherein, the P-type ion can be B ion, ga ion or In ion. When forming an NMOS transistor, the material of the drain region 114 may be silicon carbide or silicon phosphide doped with N-type ions; wherein, the N-type ions can be P ions, as ions or Sb ions.
In this embodiment, an epitaxial process is used to form an epitaxial layer, and in-situ autodoping process ions are used to form the drain region 114 during the formation of the epitaxial layer.
In this embodiment, the bottom dielectric layer also exposes the top of the semiconductor pillar 110 in the diode region I. Thus, as shown in fig. 17, before forming the drain region 114, further includes: a second mask layer 113 is formed to cover the top of the diode region I semiconductor pillar 110.
The second mask layer 113 is used to prevent the semiconductor pillar 110 of the diode region I from being epitaxially grown in the epitaxial process. In this embodiment, the material of the second mask layer 113 is silicon nitride.
Referring to fig. 18, after forming drain region 114, further includes: removing the second mask layer 113; after removing the second mask layer 113, a top dielectric layer 115 is formed covering the bottom dielectric layer and the drain region 114, and the top dielectric layer 115 and the bottom dielectric layer form an interlayer dielectric layer (not labeled). In this embodiment, a wet etching process is used to remove the second mask layer 113.
The top dielectric layer 115 is used to provide a process platform for the subsequent formation of contact plugs, and the top dielectric layer 115 is also used to achieve isolation between adjacent interconnect structures. The top dielectric layer 115 is the same material as the first dielectric layer 105. For a detailed description of the top dielectric layer 115, reference may be made to the foregoing description of the first dielectric layer 105, which is not repeated herein.
Referring to fig. 19, after forming the top dielectric layer 115, a contact hole plug 116 is formed in the interlayer dielectric layer, wherein the contact hole plug 116 electrically connected to the diode region I doped layer 104 serves as a first contact hole plug, the contact hole plug 116 electrically connected to the diode region I semiconductor pillar 110 serves as a second contact hole plug, the contact hole plug 116 electrically connected to the source region serves as a source region contact hole plug, the contact hole plug 116 electrically connected to the gate structure 120 serves as a gate contact hole plug, and the contact hole plug 116 electrically connected to the drain region 114 serves as a drain region contact hole plug. In this embodiment, the contact plug 116 is made of tungsten.
The first contact plug is formed in the interlayer dielectric layer at one side of the semiconductor pillar 110, and is used for electrically connecting the doped layer 104 of the diode region I with an external circuit or other interconnection structures; the second contact plug is formed in the interlayer dielectric layer above the semiconductor pillar 110, and is used for electrically connecting the semiconductor pillar 110 in the diode region I with an external circuit or other interconnection structure; the source region contact hole plug is formed in the interlayer dielectric layer at one side of the gate structure 120, and is used for realizing the electrical connection between the source region and an external circuit or other interconnection structures; the gate contact plug is formed in the interlayer dielectric layer at the other side of the gate structure 120, and is used for realizing the electrical connection between the gate structure 120 and an external circuit or other interconnection structures; a drain contact plug is formed in the interlayer dielectric layer above drain region 114 for making electrical connection of drain region 114 to an external circuit or other interconnect structure.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 19, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base (not labeled) including a diode region I, the base including a substrate 100 and a semiconductor pillar 110 protruding from the substrate 100, the substrate 100 and the semiconductor pillar 110 being doped with a first type of ions; and a doped layer 104 located on the substrate 100 and the semiconductor pillar 110 side wall of the diode region I, wherein the doped layer 104 is doped with a second type of ions, and the second type of ions has a conductivity type different from that of the first type of ions.
By locating the doped layer 104 on the sidewall of the substrate 100 and the semiconductor pillar 110 of the diode region I, the contact area between the doped layer 104 and the substrate is increased, and the area of the PN junction interface formed by the doped layer 104 and the substrate is correspondingly increased, thereby improving the performance of the diode device and the capability of conducting electrostatic current.
The base of the diode region I is used to form a diode device. In this embodiment, the substrate further includes a MOS region II, where the MOS region II substrate is used to form a MOS device.
In this embodiment, the diode region I and the MOS region II are adjacent regions. In other embodiments, the diode region and the MOS region may not be adjacent.
The substrate 100 of the diode region I is used to form a P-type doped region or an N-type doped region of the diode device.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The semiconductor pillar 110 of the diode region I is used to form a P-type doped region or an N-type doped region of the diode device, and the semiconductor pillar 110 of the diode region I is also used to provide a process platform for the formation of the doped layer 104; the semiconductor pillars 110 of the MOS region I are used to provide a process platform for forming the MOS device, and the semiconductor pillars 110 of the MOS region I are also used to form a channel region when the MOS device is in operation.
In this embodiment, the semiconductor pillars 110 are made of the same material as the substrate 100, and the semiconductor pillars 110 are made of silicon. In other embodiments, the semiconductor pillars and the substrate may be made of different materials, and the semiconductor pillars may be made of germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The substrate 100 and the semiconductor pillars 110 are doped with a first type of ion. When the substrate 100 and the semiconductor pillar 110 of the diode region I are used As N-type doped regions of the diode device, the first type ions are N-type ions, wherein the N-type ions may be P ions, as ions, or Sb ions; accordingly, the substrate of the MOS region II is used to form a PMOS transistor. When the substrate 100 and the semiconductor pillar 110 of the diode region I are used as P-type doped regions of the diode device, the first type ions are P-type ions, wherein the P-type ions may be B ions, ga ions, or In ions; accordingly, the substrate of the MOS region II is used to form an NMOS transistor.
The doped layer 104 of the diode region I is used as an N-type doped region or a P-type doped region of the diode device.
Specifically, when the substrate 100 and the semiconductor pillar 110 are used as N-type doped regions of the diode device, the doped layer 104 of the diode region I is used as a P-type doped region, the second type of ions are P-type ions, and the material of the doped layer 104 may be silicon germanium doped with P-type ions; when the substrate 100 and the semiconductor pillar 110 are used as P-type doped regions of a diode device, the doped layer 104 of the diode region I is used as an N-type doped region, the second type of ions are corresponding to N-type ions, and the material of the doped layer 104 may be silicon carbide or silicon phosphide doped with the N-type ions, respectively.
The doped layer 104 is also located on the substrate 100 of the MOS region II, and the doped layer 104 located on the substrate 100 of the MOS region II serves as a source region (not shown).
The source region of the MOS device and the doped layer 104 of the diode device are formed in the same step, so that the process steps of forming the MOS device and the diode device are integrated, the process is simplified, the manufacturing efficiency is improved, meanwhile, the source region is not located at the bottom of a semiconductor column of the MOS region or in a substrate, the probability of diffusion of doped ions in the source region to a channel region is small, the short channel effect is improved, the doping concentration of the source region can be properly increased, the resistance of the source region and the contact resistance of the source region and a contact hole plug are reduced, and the performance of the MOS device is correspondingly improved.
Doped layer 104 is not too thin nor too thick. If the thickness of the doped layer 104 is too small, the volume of the doped layer 104 is correspondingly too small, which tends to increase the resistance of the semiconductor structure; if the doped layer 104 is too thick, process time and process materials are easily wasted, and the exposed height of the MOS region II semiconductor pillar 110 of the doped layer 104 is easily reduced, the portion of the MOS region II semiconductor pillar 110 for providing a conductive channel is correspondingly reduced, which easily affects the performance of the formed MOS device, for example: resulting in an aggravation of short channel effects, etc. For this reason, in the present embodiment, the thickness of the doped layer 104 is 4 nm to 12 nm.
It should be noted that, the doped layer 104 is isolated at the junction of the diode region I and the MOS region II, so as to electrically isolate the diode region I and the MOS region II.
In this embodiment, the semiconductor structure further includes: a recess 200 (shown in fig. 10) is located in the substrate 100 at the junction of the diode region I and the MOS region II. The substrate 100 at the junction of the diode region I and the MOS region II is isolated by the recess 200.
The semiconductor structure further includes: the first dielectric layer 105 is located on the substrate 100 exposed by the semiconductor column 110, the first dielectric layer 105 on the diode region I covers the side wall of the semiconductor column 110, and the first dielectric layer 105 on the MOS region II exposes a portion of the side wall of the semiconductor column 110 near the top.
The first dielectric layer 105 serves to isolate adjacent devices. The first dielectric layer 110 of the MOS region II is further used to realize isolation between the source region and the gate structure; the first dielectric layer 105 of the diode region I can protect the semiconductor pillar 110 and the doped layer 104 of the diode region I during the formation of the semiconductor structure, so as to reduce the influence of the formation of the MOS region II gate structure on the diode region I. In this embodiment, the material of the first dielectric layer 105 is silicon oxide. In other embodiments, the material of the first dielectric layer may be other insulating materials such as silicon nitride, silicon oxynitride, and the like.
In this embodiment, the first dielectric layer 105 is further located in the recess 200, so as to improve the isolation effect between the MOS device and the diode device.
In this embodiment, the semiconductor structure further includes: the protection layer 103 is located between the first dielectric layer 105 of the MOS region II and the sidewall of the semiconductor column 110. The doped layer 104 is typically formed by an epitaxial process, and the protective layer 103 is used to protect a portion of the sidewall of the semiconductor pillar 110 of the MOS region II during the step of forming the doped layer 104, so that the gate structure can surround the sidewall of the semiconductor pillar 110 of the MOS region II.
The formation of doped layer 104 typically includes a step of etching back a portion of the thickness of first dielectric layer 105 of MOS region II to expose a portion of the sidewalls of MOS region II semiconductor pillar 110. The reason that the protection layer 103 is located between the MOS region II first dielectric layer 105 and the sidewall of the semiconductor pillar 110 is that: after etching back the first dielectric layer 105 of the MOS region II with partial thickness, the protection layer 103 exposed by the first dielectric layer 105 is removed.
Thus, doped layer 104 surrounds the sidewall of MOS region II semiconductor pillar 110 exposed by protective layer 103 on the side closer to substrate 100. Therefore, the protective layer 103 is different from the material of the substrate 100 or the semiconductor pillars 110.
The material of the protective layer 103 may be silicon nitride, silicon oxide, silicon oxynitride, boron nitride, or silicon carbonitride oxide. In this embodiment, the material of the protection layer 103 is silicon nitride. The silicon nitride is a material commonly used in a semiconductor process, the process compatibility is high, and the silicon nitride material and the material of the semiconductor column 110 have a high etching selectivity, so that the protection layer 103 exposed by the first dielectric layer 105 can be conveniently removed.
The protective layer 103 should not be too thin nor too thick. If the protective layer 103 is too thin, the protective layer 103 is difficult to protect the MOS region II semiconductor pillar 110, and the thickness is too small, so that the covering capability of the protective layer 103 is easily reduced, and the formation quality of the protective layer 103 is further reduced; if the protective layer 103 is too thick, process time and materials are easily wasted, difficulty in removing the protective layer 103 is increased, and when the distance of the adjacent semiconductor pillars 110 is too short, sidewalls of the protective layer 103 on sidewalls of the adjacent semiconductor pillars 110 are easily contacted. For this reason, in the present embodiment, the thickness of the protective layer 103 is 3 nm to 10 nm.
The semiconductor structure further includes: the gate structure 120 surrounds the exposed sidewall of the MOS region II semiconductor pillar 110 of the doped layer 104, and the gate structure 120 at least exposes the top of the MOS region II semiconductor pillar 110.
In this embodiment, the gate structure 120 is a metal gate structure, and the gate structure 120 includes: a gate oxide layer 121 surrounding the sidewall of the MOS region II semiconductor pillar 110 exposed by the doped layer 104, a high-k gate dielectric layer 122 surrounding the gate oxide layer 121, a work function layer 123 surrounding the high-k gate dielectric layer 122, and a gate electrode layer 124 surrounding the work function layer 123.
In this embodiment, the gate oxide layer 121 is made of silicon oxide.
In this embodiment, the material of the high-k gate dielectric layer 122 is a high-k dielectric material. Specifically, the material of the high-k gate dielectric layer 122 is HfO 2 。
When forming an NMOS transistor, the material of the work function layer 123 includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the material of the work function layer 123 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
In this embodiment, the material of the gate electrode layer 124 is magnesium-tungsten alloy.
The semiconductor structure further includes: and a drain region 114 located on top of the semiconductor pillar 110 of the MOS region II. The drain region 114 is the same material as the source region and is doped with the same type of ion.
For a detailed description of the drain region 114, reference may be made to the foregoing description of the source region, and a detailed description thereof will not be repeated here.
The semiconductor structure further includes: the second dielectric layer 112 is located on the exposed substrate of the gate structure 120. The second dielectric layer 112 also serves to achieve electrical isolation between adjacent devices. The second dielectric layer 112 and the first dielectric layer 105 form a bottom dielectric layer (not shown). Specifically, the bottom dielectric layer exposes the top of semiconductor pillars 110. For the description of the second dielectric layer 112, reference may be made to the foregoing detailed description of the first dielectric layer 105, which is not repeated here.
In this embodiment, the semiconductor structure further includes: a top dielectric layer 115 covering the bottom dielectric layer and the drain region 114, the top dielectric layer 115 and the bottom dielectric layer forming an interlayer dielectric layer (not labeled); the contact hole plug 116 is located in the interlayer dielectric layer, wherein the contact hole plug 116 electrically connected to the doped layer 104 of the diode region I is used as a first contact hole plug, the contact hole plug 116 electrically connected to the semiconductor pillar 110 of the diode region I is used as a second contact hole plug, the contact hole plug 116 electrically connected to the source region is used as a source region contact hole plug, the contact hole plug 116 electrically connected to the gate structure 120 is used as a gate contact hole plug, and the contact hole plug 116 electrically connected to the drain region 114 is used as a drain region contact hole plug.
The top dielectric layer 115 is used to provide a process platform for forming contact hole plugs 116, and the top dielectric layer 115 is also used to achieve isolation between adjacent interconnect structures. The top dielectric layer 115 is the same material as the first dielectric layer 105. For a detailed description of the top dielectric layer 115, reference may be made to the foregoing description of the first dielectric layer 105, and a detailed description thereof will not be repeated here.
In this embodiment, the contact plug 116 is made of tungsten.
The first contact plug is located in the interlayer dielectric layer at one side of the semiconductor pillar 110, and is used for electrically connecting the doped layer 104 of the diode region I with an external circuit or other interconnection structures; the second contact plug is located in the interlayer dielectric layer above the semiconductor pillar 110, and is used for electrically connecting the semiconductor pillar 110 in the diode region I with an external circuit or other interconnection structure; the source region contact hole plug is located in the interlayer dielectric layer at one side of the gate structure 120, and is used for realizing the electric connection between the source region and an external circuit or other interconnection structures; the gate contact plug is located in the interlayer dielectric layer at the other side of the gate structure 120, and is used for realizing the electrical connection between the gate structure 120 and an external circuit or other interconnection structures; the drain contact plugs are located in the interlayer dielectric layer above the drain 114 for making electrical connection of the drain 114 to an external circuit or other interconnect structure.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate comprises a diode region, the substrate comprises a substrate and a semiconductor column protruding out of the substrate, and first type ions are doped in the substrate and the semiconductor column; the substrate further comprises a MOS region;
forming a doped layer on the substrate of the diode region and the side wall of the semiconductor column, wherein the doped layer is doped with second type ions, and the second type ions are different from the first type ions in conductivity type;
in the step of forming the doped layer, the doped layer is further formed on the substrate of the MOS region, and the doped layer on the substrate of the MOS region is used as a source region;
After forming the doped layer, the method further comprises: forming a gate structure surrounding the side wall of the MOS region semiconductor column exposed by the doped layer, wherein the gate structure at least exposes the top of the MOS region semiconductor column; and after the grid electrode structure is formed, forming a drain region at the top of the MOS region semiconductor column.
2. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the base, a protective layer is formed on a sidewall of the MOS region semiconductor pillar, the protective layer exposing a portion of the sidewall of the MOS region semiconductor pillar on a side close to the substrate;
in the step of forming the doped layer, the doped layer surrounds the side wall of the MOS region semiconductor column exposed by the protective layer;
after forming the doped layer, before forming the gate structure, the method further comprises: and removing at least part of the protective layer to expose part of the side wall of the side, close to the top, of the semiconductor column of the MOS region.
3. The method of forming a semiconductor structure of claim 2, wherein the step of forming the substrate comprises: forming an initial base, wherein the initial base comprises an initial substrate and an initial semiconductor column protruding out of the initial substrate; forming a protective layer on the side wall of the initial semiconductor column; after the protective layer is formed, etching back the initial substrate with partial thickness to form the substrate and the semiconductor column;
After forming the substrate and the semiconductor column, the method further comprises: and removing the protective layer on the diode region.
4. The method of forming a semiconductor structure of claim 3, further comprising, after etching back a portion of the initial substrate, before removing the protective layer over the diode region:
and transversely etching the semiconductor column at the bottom of the protective layer.
5. The method of forming a semiconductor structure of claim 2, further comprising, after forming the doped layer, prior to forming the gate structure: forming a dielectric layer on the substrate exposed by the semiconductor column, wherein the dielectric layer covers the top of the semiconductor column; etching back part of the thickness of the dielectric layer on the MOS region to expose part of the side wall of the side, close to the top, of the semiconductor column of the MOS region;
the step of removing at least a portion of the protective layer comprises: and removing the protective layer exposed out of the MOS region dielectric layer.
6. The method of forming a semiconductor structure of claim 3, wherein the step of forming the protective layer comprises: forming a protective material layer conformally covering the initial substrate and the initial semiconductor column; and removing the protective material layers at the tops of the initial substrate and the initial semiconductor column, and taking the residual protective material layers as the protective layers.
7. The method of forming a semiconductor structure of claim 1, wherein the diode region and the MOS region are adjacent regions;
after forming the doped layer, before forming the gate structure, the method further comprises: and removing the doped layer at the junction of the diode region and the MOS region.
8. The method of forming a semiconductor structure of claim 7, wherein after removing said doped layer at the junction of said diode region and MOS region, prior to forming said gate structure, further comprising:
and removing the substrate with the thickness of the exposed part of the doping layer, and forming a groove in the substrate.
9. The method of forming a semiconductor structure of claim 2, wherein the protective layer has a thickness of 3 nm to 10 nm.
10. The method of claim 1, wherein an epitaxial layer is formed using an epitaxial process, and wherein the doped layer is formed in situ from doping ions during the formation of the epitaxial layer.
11. The method of forming a semiconductor structure of claim 1, wherein the doped layer has a thickness of 4 nm to 12 nm.
12. A semiconductor structure, comprising:
The substrate comprises a diode region, the substrate comprises a substrate and a semiconductor column protruding out of the substrate, and first type ions are doped in the substrate and the semiconductor column; the substrate further comprises a MOS region;
the doped layer is positioned on the substrate of the diode region and the side wall of the semiconductor column, and doped with second type ions, wherein the second type ions are different from the first type ions in conductivity type;
the doped layer is also positioned on the substrate of the MOS region, and the doped layer positioned on the substrate of the MOS region is used as a source region;
a gate structure surrounding the semiconductor column of the MOS region exposed by the doped layer, wherein the gate structure at least exposes the top of the semiconductor column of the MOS region;
and the drain region is positioned at the top of the semiconductor column of the MOS region.
13. The semiconductor structure of claim 12, further comprising: the dielectric layer is positioned on the substrate exposed by the semiconductor column, the dielectric layer on the diode region covers the side wall of the semiconductor column, and the dielectric layer on the MOS region exposes part of the side wall of the semiconductor column close to the top;
the protective layer is positioned between the dielectric layer of the MOS region and the side wall of the semiconductor column;
The doped layer surrounds the side wall of the MOS region semiconductor column exposed by the protective layer, which is close to one side of the substrate.
14. The semiconductor structure of claim 13, wherein the protective layer has a thickness of 3 nm to 10 nm.
15. The semiconductor structure of claim 13, wherein the material of the protective layer is silicon nitride, silicon oxide, silicon oxynitride, boron nitride, or silicon oxycarbonitride.
16. The semiconductor structure of claim 12, wherein the doped layer has a thickness of 4 nm to 12 nm.
17. The semiconductor structure of claim 13, wherein the diode region and MOS region are adjacent regions;
the doped layer is isolated at the junction of the diode region and the MOS region.
18. The semiconductor structure of claim 17, further comprising: and the groove is positioned in the substrate at the junction of the diode region and the MOS region.
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