CN113035957A - Fin type field effect transistor and semiconductor device - Google Patents
Fin type field effect transistor and semiconductor device Download PDFInfo
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- CN113035957A CN113035957A CN202110224048.0A CN202110224048A CN113035957A CN 113035957 A CN113035957 A CN 113035957A CN 202110224048 A CN202110224048 A CN 202110224048A CN 113035957 A CN113035957 A CN 113035957A
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- 230000005669 field effect Effects 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 29
- 238000005457 optimization Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000035800 maturation Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001404 mediated effect Effects 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The invention provides a fin field effect transistor and a semiconductor device, wherein a diode structure consisting of a first conduction type well layer, a second conduction type deep well layer and a second conduction type well layer is formed in a diode in the fin field effect transistor manufacturing process, so that the leakage current condition of the diode in the fin field effect transistor manufacturing process can be reduced; and through the optimization design of the occupied areas of the first conduction type well layer, the second conduction type well layer and the second conduction type deep well layer, the performance of the diode in the fin field effect transistor manufacturing process is improved, meanwhile, the design of the diode in the fin field effect transistor is optimized, and the limitation of the layout design is reduced.
Description
Technical Field
The invention relates to the technical field of fin field effect transistor processing, in particular to a fin field effect transistor and a semiconductor device.
Background
A Field Effect Transistor (FET) is also referred to as a unipolar Transistor, in which conduction is mediated by majority carriers. It belongs to a voltage control type semiconductor device. Has high input resistance (10^ s)7～10^12Omega), low noise, low power consumption, large dynamic range,Easy integration, no secondary breakdown phenomenon, wide safe working area and the like, and is widely applied to the field of semiconductor preparation. With the continuous maturation of FET technology and the continuous pursuit of high performance devices, technicians have developed a new type of field effect transistor, FinFET (fin field effect transistor), in which the gate is formed into a fin-like 3D structure that can be turned on and off in a control circuit. This design can greatly improve circuit control and reduce leakage current (leakage current), and is applied to the process technology of short transistor; therefore, the Fin FET has the advantages of low power consumption and small area, and can effectively suppress the short channel effect and the lower drain induced barrier lowering effect, and is gradually put into mass production at present. However, there are still many limitations on the device design of each type of finfet.
Disclosure of Invention
In view of this, the invention provides a diode and a semiconductor device in a fin field effect transistor manufacturing process, which effectively solve the technical problems in the prior art, optimize the design of the diode in the fin field effect transistor, and reduce the limitation of the layout design.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a diode in a fin field effect transistor process, comprising:
a first conductivity type substrate including opposing first and second faces;
a second conductivity type deep well layer in the first conductivity type substrate;
a first conductivity type well layer and a second conductivity type well layer located in the first conductivity type substrate and located on a surface of the second conductivity type deep well layer on a side facing the first face, the first conductivity type well layer and the second conductivity type well layer being flush with the first face on a surface facing away from the second conductivity type deep well layer; wherein an orthographic projection of the second conductivity-type deep well layer on the second face covers an orthographic projection of the second conductivity-type well layer on the second face, and an orthographic projection of the second conductivity-type well layer on the second face completely covers an orthographic projection of the first conductivity-type well layer on the second face;
and the fin part is positioned on one side, away from the second conduction type deep well layer, of the first conduction type well layer, and the fin part is positioned on one side, away from the second conduction type deep well layer, of the second conduction type well layer.
Optionally, an orthographic projection of the second conductivity type deep well layer on the second surface coincides with an orthographic projection of the second conductivity type well layer on the second surface.
Optionally, an orthographic projection of the second conductivity-type deep well layer on the second surface completely covers an orthographic projection of the second conductivity-type well layer on the second surface.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type.
Optionally, the first conductivity type is an N-type, and the second conductivity type is a P-type.
Optionally, the diode in the fin field effect transistor process further includes:
the shallow trench isolation layer is located on the first face and comprises shallow trenches corresponding to the first conduction type fin portions and the second conduction type fin portions one to one.
Optionally, the shallow trench isolation layer is an oxide shallow trench isolation layer.
Optionally, the diode in the fin field effect transistor process further includes:
the fin part comprises a first conduction type epitaxial layer and a second conduction type epitaxial layer, wherein the first conduction type epitaxial layer is positioned on one side, away from the first conduction type substrate, of the first conduction type fin part, and the second conduction type epitaxial layer is positioned on one side, away from the first conduction type substrate, of the second conduction type fin part.
Optionally, the first conductive type substrate is a silicon substrate.
Correspondingly, the invention also provides a semiconductor device which comprises the diode in the fin field effect transistor manufacturing process.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a diode and a semiconductor device in fin field effect transistor manufacturing process, which comprises the following steps: a first conductivity type substrate including opposing first and second faces; a second conductivity type deep well layer in the first conductivity type substrate; a first conductivity type well layer and a second conductivity type well layer located in the first conductivity type substrate and located on a surface of the second conductivity type deep well layer on a side facing the first face, the first conductivity type well layer and the second conductivity type well layer being flush with the first face on a surface facing away from the second conductivity type deep well layer; wherein an orthographic projection of the second conductivity-type deep well layer on the second face covers an orthographic projection of the second conductivity-type well layer on the second face, and an orthographic projection of the second conductivity-type well layer on the second face completely covers an orthographic projection of the first conductivity-type well layer on the second face; and the fin part is positioned on one side, away from the second conduction type deep well layer, of the first conduction type well layer, and the fin part is positioned on one side, away from the second conduction type deep well layer, of the second conduction type well layer.
According to the technical scheme provided by the invention, the diode structure consisting of the first conduction type well layer, the second conduction type deep well layer and the second conduction type well layer is formed in the diode in the fin field effect transistor manufacturing process, so that the leakage current condition of the diode in the fin field effect transistor manufacturing process can be further reduced; and through the optimization design of the occupied areas of the first conduction type well layer, the second conduction type well layer and the second conduction type deep well layer, the performance of the diode in the fin field effect transistor manufacturing process is improved, meanwhile, the design of the diode in the fin field effect transistor is optimized, and the limitation of the layout design is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a diode structure in a FinFET process according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating an area relationship among a first conductivity type well layer, a second conductivity type well layer, and a second conductivity type deep well layer according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an area relationship among another first conductivity type well layer, a second conductivity type well layer, and a second conductivity type deep well layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a diode structure in another FinFET process according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a diode in a finfet process according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background, with the continuous maturation of FET technology and the continuous pursuit of high performance devices, the skilled person has developed a new type of field effect transistor, Fin FET (Fin field effect transistor), in which the gate is in a Fin-like 3D structure to control the on and off of the circuit. The design can greatly improve the circuit control and reduce the leakage current (leakage current), and can also greatly shorten the gate length of the transistor; therefore, the FinFET has the advantages of low power consumption and small area, and can effectively suppress the short channel effect and the lower drain induced barrier lowering effect, and is gradually put into mass production at present. There are still limitations on the device design of each type of finfet.
Based on the above, the embodiment of the invention provides a diode and a semiconductor device in a fin field effect transistor manufacturing process, which effectively solve the technical problems in the prior art, improve the performance of the diode in the fin field effect transistor manufacturing process, optimize the design of the diode in the fin field effect transistor, and reduce the limit of the layout design.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 5.
Referring to fig. 1, a schematic structural diagram of a diode in a fin field effect transistor manufacturing process according to an embodiment of the present invention is shown, wherein the diode in the fin field effect transistor manufacturing process includes:
a first conductivity type substrate 100, said first conductivity type substrate 100 comprising opposing first 101 and second 102 faces.
A second conductive type deep well layer 200 in the first conductive type substrate 100.
A first conductivity type well layer 300 and a second conductivity type well layer 400 in the first conductivity type substrate 100 and on a surface of the second conductivity type deep well layer 200 on a side facing the first face 101, the first conductivity type well layer 300 and the second conductivity type well layer 400 being flush with the first face 101 on a surface facing away from the second conductivity type deep well layer 200; wherein an orthographic projection of the second conductivity-type deep well layer 200 on the second face 102 covers an orthographic projection of the second conductivity-type well layer 400 on the second face 102, and an orthographic projection of the second conductivity-type well layer 400 on the second face 102 completely covers an orthographic projection of the first conductivity-type well layer 300 on the second face 102.
And at least one first conductive-type fin 310 on a side of the first conductive-type well layer 300 facing away from the second conductive-type deep well layer 200, and at least one second conductive-type fin 410 on a side of the second conductive-type well layer 400 facing away from the second conductive-type deep well layer 200.
It can be understood that according to the technical scheme provided by the embodiment of the invention, the diode structure consisting of the first conduction type well layer, the second conduction type deep well layer and the second conduction type well layer is formed in the diode in the fin field effect transistor manufacturing process, so that the leakage current condition of the diode in the fin field effect transistor manufacturing process can be reduced; and the performance of the diode in the fin field effect transistor manufacturing process is further improved through the optimization design of the occupied areas of the first conduction type well layer, the second conduction type well layer and the second conduction type deep well layer.
In an embodiment of the present invention, an orthographic projection of the second conductivity type deep well layer on the second surface provided by the embodiment of the present invention covers an orthographic projection of the second conductivity type well layer on the second surface, and an orthographic projection of the second conductivity type well layer on the second surface completely covers an orthographic projection of the first conductivity type well layer on the second surface; that is, the occupied area of the second conductivity type deep well layer provided in the embodiment of the present invention is greater than or equal to the occupied area of the second conductivity type well layer, and the occupied area of the second conductivity type well layer is greater than the occupied area of the first conductivity type well layer. The first conduction type well layer, the second conduction type well layer and the second conduction type deep well layer can be prepared by doping the first conduction type substrate.
As shown in fig. 2, a schematic diagram of area relationships of a first conductivity type well layer, a second conductivity type well layer and a second conductivity type deep well layer provided in the embodiment of the present invention is shown, wherein an orthographic projection 200 'of the second conductivity type deep well layer on the second surface provided in the embodiment of the present invention coincides with an orthographic projection 400' of the second conductivity type well layer on the second surface; and an orthographic projection 400 'of the second conductivity type well layer at the second face completely covers an orthographic projection 300' of the first conductivity type well layer at the second face. It can be understood that the occupation area of the second conductivity type deep well layer provided by the embodiment of the present invention may be equal to that of the second conductivity type well layer, and the occupation area of the second conductivity type well layer is larger than that of the first conductivity type well layer.
As shown in fig. 3, a schematic diagram of area relationships of another first conductivity type well layer, a second conductivity type well layer and a second conductivity type deep well layer provided in the embodiment of the present invention is shown, wherein an orthographic projection 200 'of the second conductivity type deep well layer on the second surface provided in the embodiment of the present invention completely covers an orthographic projection 400' of the second conductivity type well layer on the second surface; and an orthographic projection 400 'of the second conductivity type well layer at the second face completely covers an orthographic projection 300' of the first conductivity type well layer at the second face. It can be understood that the occupation area of the second conductivity type deep well layer provided by the embodiment of the present invention may be larger than that of the second conductivity type well layer, and the occupation area of the second conductivity type well layer may be larger than that of the first conductivity type well layer.
In an embodiment of the present invention, the first conductive type provided in the embodiment of the present invention is a P type, and the second conductive type is an N type. That is, the first conductivity-type substrate, the first conductivity-type well layer, and the first conductivity-type fin provided in the embodiment of the present invention are all P-type structures, and the second conductivity-type well layer, the second conductivity-type deep well layer, and the second conductivity-type fin are all N-type structures.
Alternatively, the first conductivity type provided in the embodiment of the present invention is an N type, and the second conductivity type is a P type. That is, the first conductive type substrate, the first conductive type well layer, and the first conductive type fin portion provided in the embodiment of the present invention are all N-type structures, and the second conductive type well layer, the second conductive type deep well layer, and the second conductive type fin portion are all P-type structures.
As shown in fig. 4, another structural diagram of a diode in a finfet process according to an embodiment of the present invention is shown, wherein the diode in the finfet process includes:
a first conductivity type substrate 100, said first conductivity type substrate 100 comprising opposing first 101 and second 102 faces.
A second conductive type deep well layer 200 in the first conductive type substrate 100.
A first conductivity type well layer 300 and a second conductivity type well layer 400 in the first conductivity type substrate 100 and on a surface of the second conductivity type deep well layer 200 on a side facing the first face 101, the first conductivity type well layer 300 and the second conductivity type well layer 400 being flush with the first face 101 on a surface facing away from the second conductivity type deep well layer 200; wherein an orthographic projection of the second conductivity-type deep well layer 200 on the second face 102 covers an orthographic projection of the second conductivity-type well layer 400 on the second face 102, and an orthographic projection of the second conductivity-type well layer 400 on the second face 102 completely covers an orthographic projection of the first conductivity-type well layer 300 on the second face 102.
And at least one first conductive-type fin 310 on a side of the first conductive-type well layer 300 facing away from the second conductive-type deep well layer 200, and at least one second conductive-type fin 410 on a side of the second conductive-type well layer 400 facing away from the second conductive-type deep well layer 200.
In addition, the diode in the fin field effect transistor process provided by the embodiment of the invention further comprises:
the shallow trench isolation layer 500 is located on the first surface 101, and the shallow trench isolation layer 500 includes shallow trenches corresponding to the first conductive type fins 310 and the second conductive type fins 410 one to one, where the first conductive type fins 310 and the second conductive type fins 410 are in contact with respective corresponding well layers through the shallow trenches, respectively.
In an embodiment of the present invention, the shallow trench isolation layer provided in the present invention is an oxide shallow trench isolation layer; the oxide shallow trench isolation layer can be a silicon oxide shallow trench isolation layer, and the material of the present invention is not particularly limited.
It can be understood that according to the technical scheme provided by the embodiment of the invention, the diode structure consisting of the first conduction type well layer, the second conduction type deep well layer and the second conduction type well layer is formed in the diode in the fin field effect transistor manufacturing process, so that the leakage current condition of the diode in the fin field effect transistor manufacturing process can be reduced; and the performance of the diode in the fin field effect transistor manufacturing process is further improved through the optimization design of the occupied areas of the first conduction type well layer, the second conduction type well layer and the second conduction type deep well layer.
As shown in fig. 5, another structural diagram of a diode in a finfet process according to an embodiment of the present invention is shown, wherein the diode in the finfet process includes:
a first conductivity type substrate 100, said first conductivity type substrate 100 comprising opposing first 101 and second 102 faces.
A second conductive type deep well layer 200 in the first conductive type substrate 100.
A first conductivity type well layer 300 and a second conductivity type well layer 400 in the first conductivity type substrate 100 and on a surface of the second conductivity type deep well layer 200 on a side facing the first face 101, the first conductivity type well layer 300 and the second conductivity type well layer 400 being flush with the first face 101 on a surface facing away from the second conductivity type deep well layer 200; wherein an orthographic projection of the second conductivity-type deep well layer 200 on the second face 102 covers an orthographic projection of the second conductivity-type well layer 400 on the second face 102, and an orthographic projection of the second conductivity-type well layer 400 on the second face 102 completely covers an orthographic projection of the first conductivity-type well layer 300 on the second face 102.
And at least one first conductive-type fin 310 on a side of the first conductive-type well layer 300 facing away from the second conductive-type deep well layer 200, and at least one second conductive-type fin 410 on a side of the second conductive-type well layer 400 facing away from the second conductive-type deep well layer 200.
In addition, the diode in the fin field effect transistor process provided by the embodiment of the invention further comprises:
a first conductivity type epitaxial layer 320 on a side of the first conductivity type fin 310 facing away from the first conductivity type substrate 100, and a second conductivity type epitaxial layer 420 on a side of the second conductivity type fin 410 facing away from the first conductivity type substrate 100.
As further shown in fig. 5, the diode in the fin field effect transistor process according to the embodiment of the present invention may further include:
the shallow trench isolation layer 500 is located on the first surface 101, and the shallow trench isolation layer 500 includes shallow trenches corresponding to the first conductive type fins 310 and the second conductive type fins 410 one to one, where the first conductive type fins 310 and the second conductive type fins 410 are in contact with respective corresponding well layers through the shallow trenches, respectively.
It can be understood that according to the technical scheme provided by the embodiment of the invention, the diode structure consisting of the first conduction type well layer, the second conduction type deep well layer and the second conduction type well layer is formed in the diode in the fin field effect transistor manufacturing process, so that the leakage current condition of the diode in the fin field effect transistor manufacturing process can be reduced; and the performance of the diode in the fin field effect transistor manufacturing process is further improved through the optimization design of the occupied areas of the first conduction type well layer, the second conduction type well layer and the second conduction type deep well layer.
In an embodiment of the present invention, the first conductive type substrate provided in the present invention is a silicon substrate, and the material of the first conductive type substrate is not particularly limited in the present invention.
Correspondingly, the embodiment of the invention also provides a semiconductor device, and the semiconductor device comprises the diode in the fin field effect transistor manufacturing process provided by any one of the embodiments.
Compared with the prior art, the technical scheme provided by the embodiment of the invention at least has the following advantages:
the embodiment of the invention provides a diode and a semiconductor device in a fin field effect transistor manufacturing process, which comprises the following steps: a first conductivity type substrate including opposing first and second faces; a second conductivity type deep well layer in the first conductivity type substrate; a first conductivity type well layer and a second conductivity type well layer located in the first conductivity type substrate and located on a surface of the second conductivity type deep well layer on a side facing the first face, the first conductivity type well layer and the second conductivity type well layer being flush with the first face on a surface facing away from the second conductivity type deep well layer; wherein an orthographic projection of the second conductivity-type deep well layer on the second face covers an orthographic projection of the second conductivity-type well layer on the second face, and an orthographic projection of the second conductivity-type well layer on the second face completely covers an orthographic projection of the first conductivity-type well layer on the second face; and the fin part is positioned on one side, away from the second conduction type deep well layer, of the first conduction type well layer, and the fin part is positioned on one side, away from the second conduction type deep well layer, of the second conduction type well layer.
As can be seen from the above, according to the technical scheme provided by the embodiment of the invention, the diode structure composed of the first conductive type well layer, the second conductive type deep well layer and the second conductive type well layer is formed in the diode in the fin field effect transistor manufacturing process, so that the leakage current condition of the diode in the fin field effect transistor manufacturing process can be reduced; and through the optimization design of the occupied areas of the first conduction type well layer, the second conduction type well layer and the second conduction type deep well layer, the performance of the diode in the fin field effect transistor manufacturing process is improved, meanwhile, the design of the diode in the fin field effect transistor is optimized, and the limitation of the layout design is reduced.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A fin field effect transistor, comprising:
a first conductivity type substrate including opposing first and second faces;
a second conductivity type deep well layer in the first conductivity type substrate;
a first conductivity type well layer and a second conductivity type well layer located in the first conductivity type substrate and located on a surface of the second conductivity type deep well layer on a side facing the first face, the first conductivity type well layer and the second conductivity type well layer being flush with the first face on a surface facing away from the second conductivity type deep well layer; wherein an orthographic projection of the second conductivity-type deep well layer on the second face covers an orthographic projection of the second conductivity-type well layer on the second face, and an orthographic projection of the second conductivity-type well layer on the second face completely covers an orthographic projection of the first conductivity-type well layer on the second face;
and the fin part is positioned on one side, away from the second conduction type deep well layer, of the first conduction type well layer, and the fin part is positioned on one side, away from the second conduction type deep well layer, of the second conduction type well layer.
2. The in-fin field effect transistor (FinFET) diode of claim 1, wherein an orthographic projection of the second conductivity type deep well layer on the second face coincides with an orthographic projection of the second conductivity type well layer on the second face.
3. The in-fin field effect transistor (FinFET) diode of claim 1, wherein an orthographic projection of the second conductivity type deep well layer on the second side completely covers an orthographic projection of the second conductivity type well layer on the second side.
4. The in-fin field effect transistor (FinFET) process diode of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.
5. The in-fin field effect transistor (FinFET) process diode of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
6. The in-fin field effect transistor (FinFET) in-process diode of claim 1, further comprising:
the shallow trench isolation layer is located on the first face and comprises shallow trenches corresponding to the first conduction type fin portions and the second conduction type fin portions one to one.
7. The device of claim 6, wherein the shallow trench isolation layer is a shallow trench oxide isolation layer.
8. The in-fin field effect transistor (FinFET) in-process diode of claim 1, further comprising:
the fin part comprises a first conduction type epitaxial layer and a second conduction type epitaxial layer, wherein the first conduction type epitaxial layer is positioned on one side, away from the first conduction type substrate, of the first conduction type fin part, and the second conduction type epitaxial layer is positioned on one side, away from the first conduction type substrate, of the second conduction type fin part.
9. The in-fin field effect transistor (FinFET) process diode of claim 1, wherein the first conductivity type substrate is a silicon substrate.
10. A semiconductor device comprising the finfet in-process diode of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110224048.0A CN113035957A (en) | 2021-03-01 | 2021-03-01 | Fin type field effect transistor and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110224048.0A CN113035957A (en) | 2021-03-01 | 2021-03-01 | Fin type field effect transistor and semiconductor device |
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| US20090085163A1 (en) * | 2007-09-27 | 2009-04-02 | Christian Russ | Vertical diode using silicon formed by selective epitaxial growth |
| US20150014809A1 (en) * | 2013-07-15 | 2015-01-15 | United Microelectronics Corp. | Fin diode structure |
| CN109216470A (en) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111863933A (en) * | 2019-04-29 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090085163A1 (en) * | 2007-09-27 | 2009-04-02 | Christian Russ | Vertical diode using silicon formed by selective epitaxial growth |
| US20150014809A1 (en) * | 2013-07-15 | 2015-01-15 | United Microelectronics Corp. | Fin diode structure |
| CN109216470A (en) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111863933A (en) * | 2019-04-29 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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Application publication date: 20210625 |