CN214411207U

CN214411207U - Groove type MOS device

Info

Publication number: CN214411207U
Application number: CN202120432681.4U
Authority: CN
Inventors: 李振道; 孙明光
Original assignee: Jiangsu Applied Power Microelectronics Co ltd
Current assignee: Jiangsu Applied Power Microelectronics Co ltd
Priority date: 2021-02-26
Filing date: 2021-02-26
Publication date: 2021-10-15
Anticipated expiration: 2031-02-26

Abstract

The utility model discloses a trench type MOS device, including N type epitaxial layer, be located the lightly doped P type well layer of upper portion in the N type epitaxial layer, the region that the lightly doped P type well layer is located between first heavily doped N type source region, the second heavily doped N type source region is provided with a heavily doped P type district, heavily doped P type district upper surface is located lightly doped P type well layer upper surface, and heavily doped P type district lower surface extend to inside the N type epitaxial layer, the lower extreme in this heavily doped P type district is located the below of lightly doped P type well layer lower surface, heavily doped P type district extends to first heavily doped N type source region, second heavily doped N type source region under to the end in opposite directions transversely, the width in heavy doped P type district middle part is greater than the width of its upper portion and lower part; the contact surface of the heavily doped P-type region and the lightly doped P-type well layer is an outer convex arc surface. The utility model discloses slot type MOS device has both reduced the switching loss of device, has also improved the shock-resistant ability that the device switch switched under the high frequency.

Description

Groove type MOS device

Technical Field

The utility model relates to a MOS device especially relates to a ditch cell type MOS device.

Background

The trench power MOS device is developed on the basis of a planar power MOS device. Compared with a planar power MOS device, the planar power MOS device has the advantages of low on-resistance, low saturation voltage, high switching speed, high channel density, small chip size and the like; the groove type structure is adopted, and the parasitic JFET (junction field effect transistor) effect existing in the planar power MOS device is eliminated. At present, deep trench power MOS devices have been developed to become the mainstream of middle-low voltage high-power MOS devices. However, the conventional trench high-power MOS device still has many technical problems to be improved.

Disclosure of Invention

The utility model provides a ditch slot type MOS device, this ditch slot type MOS device had both reduced the switching loss of device, had also improved the shock-resistant ability that the device switch switched under the high frequency.

In order to achieve the above purpose, the utility model adopts the technical scheme that: a groove type MOS device comprises an N-type epitaxial layer and a lightly doped P-type well layer positioned on the middle upper part of the N-type epitaxial layer, wherein a first groove and a second groove are formed in the middle of the lightly doped P-type well layer at intervals, the first groove and the second groove positioned in the lightly doped P-type well layer extend into the N-type epitaxial layer from the upper surface of the lightly doped P-type well layer, a gate polycrystalline silicon part is arranged in each of the first groove and the second groove, and the first groove and the second groove are respectively isolated from the gate polycrystalline silicon parts through a gate oxide layer;

the lightly doped P-type well layer is positioned at the upper part of a region between the first groove and the second groove and is provided with a first heavily doped N-type source region and a second heavily doped N-type source region at intervals, and the first heavily doped N-type source region and the second heavily doped N-type source region are respectively positioned at the periphery of the first groove and the second groove;

the lightly doped P-type well layer is provided with a heavily doped P-type region in a region between a first heavily doped N-type source region and a second heavily doped N-type source region, the upper surface of the heavily doped P-type region is positioned on the upper surface of the lightly doped P-type well layer, the lower surface of the heavily doped P-type region extends into the N-type epitaxial layer, the lower end of the heavily doped P-type region is positioned below the lower surface of the lightly doped P-type well layer, the heavily doped P-type region transversely extends to the position right below opposite ends of the first heavily doped N-type source region and the second heavily doped N-type source region, a channel region is arranged between the middle part of the heavily doped P-type region and the first groove and the second heavily doped groove, and the width of the middle part of the heavily doped P-type region is greater than the widths of the upper part and the lower part of the heavily doped P-type region; the contact surface of the heavily doped P-type region and the lightly doped P-type well layer is an outer convex arc surface, and the contact surface of the heavily doped P-type region and the N-type epitaxial layer is an arc surface which is convex downwards;

a dielectric layer covers the upper portions of the first groove and the second groove and the upper portions of the first heavily doped N-type source region and the second heavily doped N-type source region close to the grooves, and a metal layer covers the upper portions of the heavily doped P-type region and the upper portions of the first heavily doped N-type source region and the second heavily doped N-type source region far away from the grooves.

The relevant content in the above technical solution is explained as follows:

1. in the above scheme, the depth ratio of the lightly doped P-type well layer to the heavily doped P-type region is 10: 3 to 5.

2. In the above scheme, the first heavily doped N-type source region and the second heavily doped N-type source region are both high-concentration arsenic-doped N-type source regions.

3. In the above scheme, the metal layer is an aluminum metal layer.

Because of the application of the technical scheme, compared with the prior art, the utility model has the following advantages:

1. the utility model discloses slot type MOS device, its light doping P type well position is provided with a heavy doping P type district in the region between first heavy doping N type source region, the second heavy doping N type source region, heavy doping P type district upper surface is located light doping P type well layer upper surface, and heavy doping P type district lower surface extend to inside the N type epitaxial layer, the lower extreme in this heavy doping P type district is located the below of light doping P type well layer lower surface, the heavy doping P type district is the evagination arcwall face with the contact surface of light doping P type well layer, the width at heavy doping P type district middle part is greater than the width of its upper portion and lower part, the heavy doping P type district is the bellied arcwall face downwards with the contact surface of N type epitaxial layer, shifts the biggest electric field to in the N type epitaxial layer that is located heavy doping P type district below to the switching loss of device has been reduced.

2. The utility model discloses ditch groove type MOS device, its light doping P type trap level is provided with a heavy doping P type district in the region between first heavy doping N type source region, the second heavy doping N type source region, heavy doping P type district extends to first heavy doping N type source region, second heavy doping N type source region under to the end on horizontal, be the channel region between the lower part in heavy doping P type district and first slot and the second slot, improved the shock-resistant ability that the device switch switches under the high frequency to the life of device has been prolonged.

Drawings

Fig. 1 is the structure diagram of the trench type MOS device of the present invention.

In the above drawings: 1. an N-type epitaxial layer; 2. a lightly doped P-type well layer; 3. a first trench; 4. a second trench; 5. a gate polysilicon portion; 6. isolating the gate oxide layer; 7. a first heavily doped N-type source region; 8. a second heavily doped N-type source region; 9. heavily doped P-type region; 10. a dielectric layer; 11. a metal layer; 12. a metal layer.

Detailed Description

The invention will be further described with reference to the following examples:

example 1: a groove type MOS device comprises an N-type epitaxial layer 1 and a lightly doped P-type well layer 2 positioned on the middle upper part of the N-type epitaxial layer 1, wherein a first groove 3 and a second groove 4 are formed in the lightly doped P-type well layer 2 in a spaced mode, the first groove 3 and the second groove 4 positioned in the lightly doped P-type well layer 2 extend into the N-type epitaxial layer 1 from the upper surface of the lightly doped P-type well layer 2, a gate polycrystalline silicon part 5 is arranged in each of the first groove 3 and the second groove 4, and the first groove 3 and the second groove 4 are isolated from the respective gate polycrystalline silicon part 5 through a gate oxide layer 6;

the lightly doped P-type well layer 2 is provided with a first heavily doped N-type source region 7 and a second heavily doped N-type source region 8 at intervals at the upper part of the region between the first trench 3 and the second trench 4, and the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 are respectively arranged at the periphery of the first trench 3 and the second trench 4;

a heavily doped P-type region 9 is arranged in a region, located between the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8, of the lightly doped P-type well layer 2, the upper surface of the heavily doped P-type region 9 is located on the upper surface of the lightly doped P-type well layer 2, the lower surface of the heavily doped P-type region 9 extends into the N-type epitaxial layer 1, the lower end of the heavily doped P-type region 9 is located below the lower surface of the lightly doped P-type well layer 2, the heavily doped P-type region 9 extends to the position right below opposite ends of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 in the transverse direction, a channel region 12 is arranged between the middle part of the heavily doped P-type region 9 and the first trench 3 and the second trench 4, and the width of the middle part of the heavily doped P-type region 9 is greater than the widths of the upper part and the lower part thereof; the contact surface of the heavily doped P-type region 9 and the lightly doped P-type well layer 2 is an outward convex arc surface, and the contact surface of the heavily doped P-type region 9 and the N-type epitaxial layer 1 is a downward convex arc surface;

a dielectric layer 10 covers the first trench 3 and the second trench 4 and the areas of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 close to the trenches, and a metal layer 11 covers the heavily doped P-type region 9 and the areas of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 far away from the trenches.

The depth ratio of the lightly doped P-type well layer 2 to the heavily doped P-type region 9 is 10: 3.2.

the metal layer 11 is an aluminum metal layer.

Example 2: a groove type MOS device comprises an N-type epitaxial layer 1 and a lightly doped P-type well layer 2 positioned on the middle upper part of the N-type epitaxial layer 1, wherein a first groove 3 and a second groove 4 are formed in the lightly doped P-type well layer 2 in a spaced mode, the first groove 3 and the second groove 4 positioned in the lightly doped P-type well layer 2 extend into the N-type epitaxial layer 1 from the upper surface of the lightly doped P-type well layer 2, a gate polycrystalline silicon part 5 is arranged in each of the first groove 3 and the second groove 4, and the first groove 3 and the second groove 4 are isolated from the respective gate polycrystalline silicon part 5 through a gate oxide layer 6;

The depth ratio of the lightly doped P-type well layer 2 to the heavily doped P-type region 9 is 10: 4.5.

the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 are both high-concentration arsenic-doped N-type source regions.

When the groove type MOS device is adopted, a heavily doped P type region is arranged in a region, between a first heavily doped N type source region and a second heavily doped N type source region, of a lightly doped P type well layer, the upper surface of the heavily doped P type region is located on the upper surface of the lightly doped P type well layer, the lower surface of the heavily doped P type region extends into the N type epitaxial layer, the lower end of the heavily doped P type region is located below the lower surface of the lightly doped P type well layer, the contact surface of the heavily doped P type region and the lightly doped P type well layer is an outward convex arc surface, the width of the middle part of the heavily doped P type region is larger than the width of the upper part and the lower part of the heavily doped P type region, the contact surface of the heavily doped P type region and the N type epitaxial layer is an arc surface which protrudes downwards, the maximum electric field is transferred into the N type epitaxial layer located below the heavily doped P type region, and therefore the switching loss of the device is reduced; also, it improves the impact resistance of the switching of the device at high frequencies, thereby extending the lifetime of the device.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.

Claims

1. A trench type MOS device is characterized in that: the light-doped P-type well structure comprises an N-type epitaxial layer (1) and a light-doped P-type well layer (2) positioned on the middle upper part of the N-type epitaxial layer (1), wherein a first groove (3) and a second groove (4) are formed in the light-doped P-type well layer (2) at intervals, the first groove (3) and the second groove (4) positioned in the light-doped P-type well layer (2) extend into the N-type epitaxial layer (1) from the upper surface of the light-doped P-type well layer (2), a gate polycrystalline silicon part (5) is arranged in each of the first groove (3) and the second groove (4), and the first groove (3) and the second groove (4) are isolated from the respective gate polycrystalline silicon part (5) through a gate oxide layer (6);

the upper part of the lightly doped P-type well layer (2) in the region between the first groove (3) and the second groove (4) is provided with a first heavily doped N-type source region (7) and a second heavily doped N-type source region (8) at intervals, and the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8) are respectively arranged at the periphery of the first groove (3) and the second groove (4);

a heavily doped P-type region (9) is arranged in the region of the lightly doped P-type well layer (2) between the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8), the upper surface of the heavily doped P-type region (9) is positioned on the upper surface of the lightly doped P-type well layer (2), the lower surface of the heavily doped P-type region (9) extends into the N-type epitaxial layer (1), the lower end of the heavily doped P-type region (9) is positioned below the lower surface of the lightly doped P-type well layer (2), the heavily doped P-type region (9) extends to the position right below the opposite ends of the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8) in the transverse direction, a channel region (12) is arranged between the middle part of the heavily doped P-type region (9) and the first groove (3) and the second groove (4), the width of the middle part of the heavily doped P-type region (9) is larger than the widths of the upper part and the lower part of the heavily doped P-type region; the contact surface of the heavily doped P-type region (9) and the lightly doped P-type well layer (2) is an outward convex arc surface, and the contact surface of the heavily doped P-type region (9) and the N-type epitaxial layer (1) is an downward convex arc surface;

a dielectric layer (10) covers the upper portions of the first groove (3) and the second groove (4) and the areas, close to the grooves, of the first heavily doped N-type source area (7) and the second heavily doped N-type source area (8), and a metal layer (11) covers the upper portions of the heavily doped P-type area (9) and the areas, far away from the grooves, of the first heavily doped N-type source area (7) and the second heavily doped N-type source area (8).

2. The trench MOS device of claim 1, wherein: the depth ratio of the lightly doped P-type well layer (2) to the heavily doped P-type region (9) is 10: 3 to 5.

3. The trench MOS device of claim 1, wherein: the first heavily-doped N-type source region (7) and the second heavily-doped N-type source region (8) are both high-concentration arsenic-doped N-type source regions.

4. The trench MOS device of claim 1, wherein: the metal layer (11) is an aluminum metal layer.