CN212342637U - Vertical power MOS semiconductor device - Google Patents
Vertical power MOS semiconductor device Download PDFInfo
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- CN212342637U CN212342637U CN202021210089.1U CN202021210089U CN212342637U CN 212342637 U CN212342637 U CN 212342637U CN 202021210089 U CN202021210089 U CN 202021210089U CN 212342637 U CN212342637 U CN 212342637U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 9
- 238000004898 kneading Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The utility model discloses a vertical power MOS semiconductor device, include: the semiconductor device comprises a silicon chip, a heavily doped N-type drain region and a middle doped P-type base region, wherein the heavily doped N-type drain region is positioned on the lower surface of the silicon chip, the middle doped P-type base region is positioned on the upper surface of the silicon chip, a lightly doped N-type drift region is arranged between the heavily doped N-type drain region and the middle doped P-type base region, and a groove positioned in the middle doped P-type base region extends to the lower; a P-type doped diffusion region is arranged on the outer side wall which is positioned in the N-type drift region and wraps the lower part of the groove, and the upper end surface of the P-type doped diffusion region is contacted with the lower surface of the P-type base region; the trench has a second N-type source portion at its lower portion and a gate portion at its upper portion. The utility model discloses vertical power MOS semiconductor device can improve the doping concentration in lightly doped N type drift region, increases under the withstand voltage's the condition, will turn-on resistance reduce when cutting off.
Description
Technical Field
The utility model relates to a MOSFET device technical field especially relates to a vertical power MOS semiconductor device.
Background
The MOSFET (metal oxide semiconductor field effect transistor) has its transistor in the off state, and when a suitable VGS is applied, the majority carriers are attracted to the gate, thereby enhancing the carriers under the poly gate and forming a conductive channel.
Disclosure of Invention
The utility model aims at providing a vertical power MOS semiconductor device, this vertical power MOS semiconductor device can improve the doping concentration in lightly doped N type drift region, increases under the withstand voltage's the condition, will turn-on resistance reduce when cutting off.
In order to achieve the above purpose, the utility model adopts the technical scheme that: a vertical power MOS semiconductor device, comprising: the semiconductor device comprises a silicon chip, a heavily doped N-type drain region and a middle doped P-type base region, wherein the heavily doped N-type drain region is positioned on the lower surface of the silicon chip, the middle doped P-type base region is positioned on the upper surface of the silicon chip, a lightly doped N-type drift region is arranged between the heavily doped N-type drain region and the middle doped P-type base region, a groove in the middle doped P-type base region extends to the lower part of the lightly doped N-type drift region, a first heavily doped N-type source region is arranged in the upper part of the middle doped P-type base region and positioned at the periphery of the groove, a dielectric layer covers the groove and extends to the upper part of the inner side edge of the first heavily doped N-type source region, an upper metal layer is positioned above the;
a P-type doped diffusion region is arranged on the outer side wall which is positioned in the N-type drift region and wraps the lower part of the groove, and the upper end surface of the P-type doped diffusion region is contacted with the lower surface of the P-type base region;
the lower part in the groove is provided with a second N-type source part, the upper part in the groove is provided with a grid part, a first silicon oxide layer is filled between the second N-type source part and the grid part and the groove, and the second N-type source part and the grid part are isolated through a second silicon oxide layer.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the depth ratio of the depth of the medium-doped P-type base region to the depth of the first heavily doped N-type source region is 10: 2 to 4.
2. In the above scheme, the thickness of the first silicon oxide layer between the gate portion and the trench is smaller than the thickness of the first silicon oxide layer between the second N-type source portion and the trench.
Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:
the utility model discloses vertical power MOS semiconductor device, its ditch inslot lower part has second N type source portion, and this ditch inslot upper portion has grid portion, it has first silicon oxide layer to fill between second N type source portion and grid portion and the ditch groove, keep apart through the second silicon oxide layer between second N type source portion and the grid portion, can improve the doping concentration in light doping N type drift region, under the withstand voltage condition of increase, will turn-on resistance reduces when cutting off; in addition, a P-type doped diffusion region is arranged in the N-type drift region and on the outer side wall covering the lower part of the groove, and the upper end face of the P-type doped diffusion region is in contact with the lower surface of the P-type base region, so that the reverse voltage blocking capability of the device is improved.
Drawings
FIG. 1 is a schematic structural diagram of a vertical power MOS semiconductor device according to the present invention;
fig. 2 is a schematic view of a local structure of the vertical power MOS semiconductor device according to the present invention.
In the above drawings: 1. a silicon wafer; 2. heavily doped N-type drain region; 3. a medium doped P-type base region; 4. a lightly doped N-type drift region; 5. a trench; 6. a first heavily doped N-type source region; 7. an upper metal layer; 8. a second N-type source portion; 9. a gate portion; 10. a first silicon oxide layer; 11. a second silicon dioxide layer; 12. a dielectric layer; 13. a lower metal layer; 14. and P-type doped diffusion regions.
Detailed Description
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1: a vertical power MOS semiconductor device, comprising: a heavily doped N-type drain region 2 positioned on the lower surface of the silicon wafer 1 and a middle doped P-type base region 3 positioned on the upper surface of the silicon wafer 1, wherein a lightly doped N-type drift region 4 is arranged between the heavily doped N-type drain region 2 and the middle doped P-type base region 3, a groove 5 positioned in the middle doped P-type base region 3 extends to the lower part of the lightly doped N-type drift region 4, a first heavily doped N-type source region 6 is arranged in the upper part of the middle doped P-type base region 3 and positioned at the periphery of the groove 5, a dielectric layer 12 covers the groove 5 and extends to the upper part of the inner side edge of the first heavily doped N-type source region 6, an upper metal layer 7 is positioned above the outer side edges of the middle doped P-type base region 3 and the first heavily doped N-type source region 6, and a lower metal layer 13 is positioned;
a P-type doped diffusion region 14 is arranged on the outer side wall which is positioned in the N-type drift region 4 and wraps the lower part of the groove 5, and the upper end surface of the P-type doped diffusion region 14 is contacted with the lower surface of the P-type base region 3;
the trench 5 has a second N-type source portion 8 at the lower portion thereof, a gate portion 9 at the upper portion thereof, a first silicon oxide layer 10 is filled between the second N-type source portion 8 and the gate portion 9 and the trench 5, and the second N-type source portion 8 and the gate portion 9 are isolated from each other by a second silicon oxide layer 11.
The depth ratio of the depth of the middle-doped P-type base region 3 to the depth of the first heavily doped N-type source region 6 is 10: 2.5.
example 2: a vertical power MOS semiconductor device, comprising: a heavily doped N-type drain region 2 positioned on the lower surface of the silicon wafer 1 and a middle doped P-type base region 3 positioned on the upper surface of the silicon wafer 1, wherein a lightly doped N-type drift region 4 is arranged between the heavily doped N-type drain region 2 and the middle doped P-type base region 3, a groove 5 positioned in the middle doped P-type base region 3 extends to the lower part of the lightly doped N-type drift region 4, a first heavily doped N-type source region 6 is arranged in the upper part of the middle doped P-type base region 3 and positioned at the periphery of the groove 5, a dielectric layer 12 covers the groove 5 and extends to the upper part of the inner side edge of the first heavily doped N-type source region 6, an upper metal layer 7 is positioned above the outer side edges of the middle doped P-type base region 3 and the first heavily doped N-type source region 6, and a lower metal layer 13 is positioned;
a P-type doped diffusion region 14 is arranged on the outer side wall which is positioned in the N-type drift region 4 and wraps the lower part of the groove 5, and the upper end surface of the P-type doped diffusion region 14 is contacted with the lower surface of the P-type base region 3;
the trench 5 has a second N-type source portion 8 at the lower portion thereof, a gate portion 9 at the upper portion thereof, a first silicon oxide layer 10 is filled between the second N-type source portion 8 and the gate portion 9 and the trench 5, and the second N-type source portion 8 and the gate portion 9 are isolated from each other by a second silicon oxide layer 11.
The depth ratio of the depth of the middle-doped P-type base region 3 to the depth of the first heavily doped N-type source region 6 is 10: 3.
the thickness of the first silicon oxide layer 10 between the gate portion 9 and the trench 5 is smaller than the thickness of the first silicon oxide layer 10 between the second N-type source portion 8 and the trench 5.
When the vertical power MOS semiconductor device is adopted, the lower part in the groove is provided with a second N-type source part, the upper part in the groove is provided with a grid part, a first silicon oxide layer is filled between the second N-type source part and the grid part and the groove, and the second N-type source part and the grid part are isolated by a second silicon oxide layer, so that the doping concentration of a lightly doped N-type drift region can be improved, and the on-resistance is reduced when the vertical power MOS semiconductor device is turned off under the condition of increasing the withstand voltage; in addition, a P-type doped diffusion region is arranged in the N-type drift region and on the outer side wall covering the lower part of the groove, and the upper end face of the P-type doped diffusion region is in contact with the lower surface of the P-type base region, so that the reverse voltage blocking capability of the device is improved.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
Claims (3)
1. A vertical power MOS semiconductor device, characterized by: the method comprises the following steps: the transistor comprises a heavily doped N-type drain region (2) positioned on the lower surface of a silicon wafer (1) and a middle doped P-type base region (3) positioned on the upper surface of the silicon wafer (1), wherein a lightly doped N-type drift region (4) is arranged between the heavily doped N-type drain region (2) and the middle doped P-type base region (3), a groove (5) positioned in the middle doped P-type base region (3) extends to the lower part of the lightly doped N-type drift region (4), a first heavily doped N-type source region (6) is arranged in the upper part of the middle doped P-type base region (3) and positioned at the periphery of the groove (5), a dielectric layer (12) covers the groove (5) and extends to the upper part of the inner side edge of the first heavily doped N-type source region (6), an upper metal layer (7) is positioned above the outer side edges of the middle doped P-type base region (3) and the first heavily doped N-type source region (6), and a lower metal layer (13) is positioned on the Kneading;
a P-type doped diffusion region (14) is arranged on the outer side wall which is positioned in the N-type drift region (4) and wraps the lower part of the groove (5), and the upper end surface of the P-type doped diffusion region (14) is contacted with the lower surface of the P-type base region (3);
the trench (5) is internally provided with a second N-type source part (8) at the lower part, a gate part (9) is arranged at the upper part in the trench (5), a first silicon oxide layer (10) is filled between the second N-type source part (8) and the trench (5) and between the gate part (9) and the second N-type source part (8), and the second N-type source part (8) and the gate part (9) are isolated by a second silicon oxide layer (11).
2. The vertical power MOS semiconductor device of claim 1, wherein: the depth ratio of the depth of the middle-doped P-type base region (3) to the depth of the first heavily-doped N-type source region (6) is 10: 2 to 4.
3. The vertical power MOS semiconductor device of claim 1, wherein: the thickness of the first silicon oxide layer (10) between the grid part (9) and the groove (5) is smaller than that of the first silicon oxide layer (10) between the second N-type source part (8) and the groove (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021210089.1U CN212342637U (en) | 2020-06-28 | 2020-06-28 | Vertical power MOS semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021210089.1U CN212342637U (en) | 2020-06-28 | 2020-06-28 | Vertical power MOS semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212342637U true CN212342637U (en) | 2021-01-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021210089.1U Active CN212342637U (en) | 2020-06-28 | 2020-06-28 | Vertical power MOS semiconductor device |
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| CN (1) | CN212342637U (en) |
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2020
- 2020-06-28 CN CN202021210089.1U patent/CN212342637U/en active Active
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Effective date of registration: 20240206 Address after: 518000 Room 201, building A, 1 front Bay Road, Shenzhen Qianhai cooperation zone, Shenzhen, Guangdong Patentee after: Shenzhen Hemeiyuan Technology Co.,Ltd. Country or region after: China Address before: Room 501, building nw20, Suzhou nano City, 99 Jinjihu Avenue, Suzhou Industrial Park, 215000, Jiangsu Province Patentee before: SUZHOU SILIKRON SEMICONDUCTOR TECHNOLOGY CO.,LTD. Country or region before: China |
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Effective date of registration: 20240322 Address after: Room 306, Building 2, No.1 Qingshan Road, High tech Zone, Suzhou City, Jiangsu Province, 215100 Patentee after: New Silicon Microelectronics (Suzhou) Co.,Ltd. Country or region after: China Address before: 518000 Room 201, building A, 1 front Bay Road, Shenzhen Qianhai cooperation zone, Shenzhen, Guangdong Patentee before: Shenzhen Hemeiyuan Technology Co.,Ltd. Country or region before: China |