CN213583799U

CN213583799U - Vertical MOSFET device

Info

Publication number: CN213583799U
Application number: CN202022576105.5U
Authority: CN
Inventors: 黄彦智; 俞仲威
Original assignee: Kaitai Semiconductor Shenzhen Co ltd
Current assignee: Kaitai Semiconductor Shenzhen Co ltd
Priority date: 2020-11-09
Filing date: 2020-11-09
Publication date: 2021-06-29
Anticipated expiration: 2030-11-09

Abstract

The utility model discloses a vertical type metal oxide semiconductor field effect transistor device, include: the semiconductor device comprises a P-type base layer, a lightly doped N-type drift layer and a heavily doped N-type substrate layer, wherein a groove in the P-type base layer extends from the upper surface of the P-type base layer to the inside of the lightly doped N-type drift layer, and a grid polysilicon part is arranged in the groove; the upper surface of the heavily doped N-type source electrode layer is provided with a groove, an insulating medium layer covers the upper surfaces of the groove and the grid polysilicon part and extends to cover a part of the groove, and a source electrode metal layer covers the upper surface of the heavily doped P-type implantation area and extends to cover the rest part of the groove of the heavily doped N-type source electrode layer. The utility model provides the high cohesion of heavy doping N type source electrode region and source electrode metal level, insulating medium layer to ohmic contact resistance has been reduced.

Description

Vertical MOSFET device

Technical Field

The utility model relates to a semiconductor device technical field especially relates to a vertical type metal oxide semiconductor field effect transistor device.

Background

A power MOSFET is a metal-oxide semiconductor field effect transistor, abbreviated as a MOSFET, which can be widely used in analog and digital circuits. A power MOSFET generally includes a source, a gate, a source, and a drain, where the gate is also referred to as the gate, the source is also referred to as the field effect transistor, and the drain is also referred to as the field effect transistor.

Disclosure of Invention

The present invention provides a vertical mosfet device, which improves the bonding force between the heavily doped N-type source region and the source metal layer, the insulating dielectric layer, and reduces the ohmic contact resistance.

In order to achieve the above purpose, the utility model adopts the technical scheme that: a vertical mosfet device, comprising: the N-type silicon wafer comprises a P-type base layer positioned on the upper part of an N-type silicon wafer body, a lightly doped N-type drift layer positioned in the middle of the N-type silicon wafer body and a heavily doped N-type substrate layer positioned on the lower part of the N-type silicon wafer body, wherein a groove positioned in the P-type base layer extends into the lightly doped N-type drift layer from the upper surface of the P-type base layer, a grid polycrystalline silicon part is arranged in the groove, and a grid oxidation isolation layer is arranged between the grid polycrystalline silicon part and the groove;

the upper surface of the heavily doped N-type source electrode layer is provided with a groove, an insulating medium layer covers the upper surfaces of the groove and the grid polysilicon part and extends to cover a part of the groove, and a source electrode metal layer covers the upper surface of the heavily doped N-type source electrode layer and extends to cover the rest part of the groove of the heavily doped N-type source electrode layer.

The further improved scheme in the technical scheme is as follows:

1. in the above scheme, the gate oxide isolation layer is a silicon dioxide layer.

2. In the above scheme, the depth ratio of the P-type base layer to the lightly doped N-type drift layer is 1: 1.5 to 4.

3. In the above scheme, the width of the opening of the groove is greater than the width of the bottom.

Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:

the utility model discloses vertical type metal oxide semiconductor field effect transistor device, its heavy doping N type source electrode zone upper surface is opened there is a recess, and an insulating medium layer covers slot and grid polycrystalline silicon portion upper surface cover recess partly with extending, and a source metal level covers in implanting the district upper surface with heavy doping P type and extends the recess remainder that covers heavy doping N type source electrode zone, has improved the cohesion of heavy doping N type source electrode zone and source metal level, insulating medium layer to ohmic contact resistance has been reduced.

Drawings

Fig. 1 is a schematic structural diagram of a vertical mosfet device according to the present invention.

In the above drawings: 1. an N-type silicon wafer body; 2. a P-type substrate layer; 3. lightly doping the N-type drift layer; 4. heavily doping an N-type substrate layer; 5. a trench; 6. a gate polysilicon portion; 7. oxidizing the isolation layer by the grid electrode; 8. heavily doped N type source region; 9. a groove; 11. an insulating dielectric layer; 12. a drain metal layer; 13. and a source metal layer.

Detailed Description

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or component to which the reference is made must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1: a vertical mosfet device, comprising: the structure comprises a P-type base layer 2 positioned on the upper part of an N-type silicon wafer body 1, a lightly doped N-type drift layer 3 positioned in the middle of the N-type silicon wafer body 1, and a heavily doped N-type substrate layer 4 positioned on the lower part of the N-type silicon wafer body 1, wherein a groove 5 positioned in the P-type base layer 2 extends into the lightly doped N-type drift layer 3 from the upper surface of the P-type base layer 2, a grid polycrystalline silicon part 6 is arranged in the groove 5, and a grid oxidation isolation layer 7 is arranged between the grid polycrystalline silicon part 6 and the groove 5;

a heavily doped N-type source region 8 is arranged on the upper part of the P-type base layer 2 and at the periphery of the groove 5, a drain metal layer 12 is arranged on the surface of the heavily doped N-type substrate layer 4 opposite to the lightly doped N-type drift layer 3, a groove 9 is formed in the upper surface of the heavily doped N-type source region 8, an insulating medium layer 11 covers the upper surfaces of the groove 5 and the gate polysilicon portion 6 and extends to cover a part of the groove 9, and a source metal layer 13 covers the upper surface of the heavily doped N-type source region 8 and extends to cover the rest part of the groove 9 of the heavily doped N-type source region 8.

The gate oxide isolation layer 7 is a silicon dioxide layer.

The depth ratio of the P-type base layer 2 to the lightly doped N-type drift layer 3 is 1: 1.8.

example 2: a vertical mosfet device, comprising: the structure comprises a P-type base layer 2 positioned on the upper part of an N-type silicon wafer body 1, a lightly doped N-type drift layer 3 positioned in the middle of the N-type silicon wafer body 1, and a heavily doped N-type substrate layer 4 positioned on the lower part of the N-type silicon wafer body 1, wherein a groove 5 positioned in the P-type base layer 2 extends into the lightly doped N-type drift layer 3 from the upper surface of the P-type base layer 2, a grid polycrystalline silicon part 6 is arranged in the groove 5, and a grid oxidation isolation layer 7 is arranged between the grid polycrystalline silicon part 6 and the groove 5;

The depth ratio of the P-type base layer 2 to the lightly doped N-type drift layer 3 is 1: 3.

the width of the opening of the groove 9 is larger than the width of the bottom.

When the vertical metal-oxide-semiconductor field effect transistor device is adopted, the upper surface of the heavily doped N-type source electrode region is provided with a groove, an insulating medium layer covers the upper surfaces of the groove and the grid polycrystalline silicon part and extends to cover a part of the groove, and a source electrode metal layer covers the upper surface of the heavily doped P-type implantation region and extends to cover the rest part of the groove of the heavily doped N-type source electrode region, so that the bonding force of the heavily doped N-type source electrode region, the source electrode metal layer and the insulating medium layer is improved, and the ohmic contact resistance is reduced.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.

Claims

1. A vertical mosfet device, comprising: the method comprises the following steps: the silicon wafer comprises a P-type base layer (2) positioned on the upper part of an N-type silicon wafer body (1), a lightly doped N-type drift layer (3) positioned in the middle of the N-type silicon wafer body (1), a heavily doped N-type substrate layer (4) positioned on the lower part of the N-type silicon wafer body (1), a groove (5) positioned in the P-type base layer (2) extends into the lightly doped N-type drift layer (3) from the upper surface of the P-type base layer (2), a grid polycrystalline silicon part (6) is arranged in the groove (5), and a grid oxidation isolation layer (7) is arranged between the grid polycrystalline silicon part (6) and the groove (5);

the structure is characterized in that a heavily doped N-type source region (8) is arranged on the upper portion of the P-type base body layer (2) and on the periphery of the groove (5), a drain metal layer (12) is arranged on the surface of the heavily doped N-type substrate layer (4) opposite to the lightly doped N-type drift layer (3), a groove (9) is formed in the upper surface of the heavily doped N-type source region (8), an insulating medium layer (11) covers the upper surfaces of the groove (5) and the grid polycrystalline silicon portion (6) and extends to cover one part of the groove (9), and a source metal layer (13) covers the upper surface of the heavily doped N-type source region (8) and extends to cover the rest part of the groove (9) of the heavily doped N-type source region.

2. The vertical mosfet device of claim 1, wherein: the grid oxidation isolation layer (7) is a silicon dioxide layer.

3. The vertical mosfet device of claim 1, wherein: the depth ratio of the P-type base layer (2) to the lightly doped N-type drift layer (3) is 1: 1.5 to 4.

4. The vertical mosfet device of claim 1, wherein: the opening width of the groove (9) is larger than the width of the bottom.