KR20230118257A - Semiconductor devices - Google Patents

Abstract

A semiconductor device includes: active patterns that protrude to the upper part of a substrate, have a lower sidewall covered by a device isolation pattern, extend in a first direction parallel to the upper surface of the substrate, and are spaced apart from each other in a first direction parallel to the upper surface of the substrate and a second direction intersecting the first direction; gate structures that extend in the second direction on the active patterns and the device isolation pattern and are spaced apart from each other in the second direction; and an isolation pattern formed between the gate structures on the substrate to separate them from each other and include polysilicon. Therefore, it is possible to provide a semiconductor device with excellent characteristics.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICES}

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device including a metal gate electrode and a manufacturing method thereof.

As the degree of integration of semiconductor devices increases, electrical short circuits or interference between gate electrodes included in the semiconductor devices are becoming more severe. For example, when an opening is formed by removing a central portion of a gate electrode extending in one direction and a separation pattern filling the opening is formed, the gate electrode may not be easily removed as the aspect ratio of the opening increases. Accordingly, gate electrodes formed on both sides of the separation pattern may be electrically connected to each other.

One object of the present invention is to provide a semiconductor device having excellent characteristics.

Another object of the present invention is to provide a method for manufacturing a semiconductor device having excellent characteristics.

A semiconductor device according to example embodiments for achieving one object of the present invention protrudes above a substrate and has a lower sidewall covered by an element isolation pattern, each in a first direction parallel to the upper surface of the substrate. active patterns extending and spaced apart from each other in a second direction parallel to the upper surface of the substrate and crossing the first direction; gate structures extending in the second direction on the active patterns and the device isolation pattern and spaced apart from each other in the second direction; and a separation pattern formed between the gate structures on the substrate to separate them from each other and including polysilicon.

In the method of fabricating a semiconductor device according to other embodiments of the present disclosure, a dummy gate structure extending in a first direction parallel to an upper surface of the substrate may be formed on a substrate. A mask may be formed on the dummy gate structure. An isolation pattern may be formed by etching the dummy gate structure by performing an etching process using the mask, and first openings may be formed on both sides of the isolation pattern in the first direction, respectively. A gate structure filling each of the first openings may be formed.

In the semiconductor device according to example embodiments, a phenomenon in which gate structures formed to be spaced apart from each other by a short distance are partially connected to each other may prevent an electrical short circuit from occurring.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously extended without departing from the spirit and scope of the present invention.

1 to 17 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.
18 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

[Example]

1 to 17 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. Specifically, Figs. 1, 4, 7 and 13 are plan views, and Figs. 2-3, 5-6, 8-12 and 14-17 are cross-sectional views.

At this time, FIGS. 2, 8-12, 14 and 16 are cross-sectional views taken along line A-A' of corresponding plan views, and FIGS. 3, 5, 15 and 17 are cross-sectional views taken along line BB' of corresponding plan views. These are cross-sectional views, respectively, and FIG. 6 is a cross-sectional view taken along the line C-C' of the corresponding plan view.

In the following detailed description of the invention, two directions that are parallel to the top surface of the substrate 100 and cross each other are defined as first and second directions D1 and D2, respectively, and a direction perpendicular to the top surface of the substrate 100 is defined as first and second directions D1 and D2. It is defined as the third direction (D3). In example embodiments, the first and second directions D1 and D2 may be orthogonal to each other.

Referring to FIGS. 1 to 3 , an upper portion of the substrate 100 may be partially etched to form a trench, and an element isolation pattern 110 filling the lower portion of the trench may be formed.

The substrate 100 may include a semiconductor material such as silicon, germanium, silicon-germanium, or a group III-V compound such as GaP, GaAs, or GaSb. According to some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

In example embodiments, the device isolation pattern 110 may be formed by forming a device isolation layer filling the trench on the substrate 100 and planarizing the device isolation layer until an upper surface of the substrate 100 is exposed. It may be formed by removing an upper portion of the isolation layer to expose an upper portion of the trench. The device isolation layer may include, for example, an oxide such as silicon oxide.

As the device isolation pattern 110 is formed, the substrate 100 has a field region whose upper surface is covered by the device isolation pattern 110 and a field region whose upper surface is not covered by the device isolation pattern 110 and which is not covered by the device isolation pattern 110 . An active area 105 protruding upward from ) may be defined. Since the active region 105 has a fin shape, it may be referred to as an active fin or, since it is a kind of pattern, it may be referred to as an active pattern. In addition, to distinguish from the active pattern 105 , only the field region and the portion of the substrate 100 formed under the active pattern 105 will be defined as the substrate 100 .

The active pattern 105 may include a lower active pattern 105a whose sidewall is covered by the device isolation pattern 110 and an upper active pattern 105b whose sidewall is not covered by the device isolation pattern 110. . In example embodiments, the active pattern 105 may extend in the first direction D1 and may be formed in plural to be spaced apart from each other along the second direction D2.

Thereafter, a dummy gate structure 150 may be formed on the substrate 100 on which the active pattern 105 and the device isolation pattern 110 are formed. The dummy gate structure 150 may include a dummy gate insulating pattern 120 , a dummy gate electrode 130 , and a dummy gate mask 140 sequentially stacked.

The dummy gate insulating pattern 120 may include, for example, an oxide such as silicon oxide, the dummy gate electrode 130 may include, for example, polysilicon, and the dummy gate mask 140 may include, for example, polysilicon. For example, it may include a nitride such as silicon nitride.

In example embodiments, the dummy gate structure 150 may extend in the second direction D2 and may be formed in plurality to be spaced apart from each other along the first direction D2.

Thereafter, gate spacers 160 may be formed on sidewalls of the dummy gate structure 150 in the first direction D1 , and at this time, fin spacers 160 may be formed on sidewalls of the active pattern 105 in the second direction D2. 170) may be formed.

The gate spacer 160 and the fin spacer 170 may be formed by forming a spacer film on the substrate 100 on which the active pattern 105, the device isolation pattern 110, and the dummy gate structure 150 are formed and anisotropically etching the spacer film. can The spacer layer may include, for example, a nitride such as silicon nitride (SiN) or silicon oxycarbonitride (SiOCN).

4 to 6 , the first recess 180 is formed by etching the upper portion of the active pattern 105 not covered by the dummy gate structure 150 and the gate spacer 160 as an etch mask. can form

In the drawing, it is shown that the first recess 180 is formed by partially removing only the upper active pattern 105b, but the concept of the present invention is not limited thereto, and the first recess 180 may be formed by partially removing the upper active pattern 105b ( 105b) may also be formed by partially removing the lower active pattern 105a.

Meanwhile, the etching process for forming the first recess 180 may be performed in-situ with the anisotropic etching process for the spacer layer described with reference to FIGS. 1 to 3 .

Thereafter, by performing a selective epitaxial growth (SEG) process using the upper surface of the active pattern 105 exposed by the first recess 180 as a seed, a source/material layer is formed on the active pattern 105. A drain layer 190 may be formed.

The selective epitaxial growth (SEG) process may be performed using, for example, a dichlorosilane (SiH ₂ Cl ₂ ) gas, a germanium tetrahydrogenide (GeH ₄ ) gas, or the like as a source gas, and accordingly, single-crystal silicon- A germanium (SiGe) layer may be formed. In this case, a single crystal silicon-germanium layer doped with a p-type impurity may be formed by using a p-type impurity source gas, such as diborane (B ₂ H ₆ ) gas. Accordingly, the source/drain layer 190 may function as a source/drain region of the PMOS transistor.

Alternatively, the selective epitaxial growth (SEG) process may be performed using, for example, disilane (Si ₂ H ₆ ) gas and SiH ₃ CH ₃ gas as a source gas, and accordingly, single crystal silicon carbide ( SiC) layer may be formed. In this case, a single crystal silicon carbide layer doped with an n-type impurity may be formed by using an n-type impurity source gas, for example, a phosphine (PH ₃ ) gas. In contrast, the selective epitaxial growth (SEG) process uses only a silicon source such as a disilane (Si ₂ H ₆ ) gas together with the n-type impurity source gas to form a single crystal doped with an n-type impurity. A silicon layer may also be formed. Accordingly, the source/drain layer 190 may function as a source/drain region of the NMOS transistor.

The source/drain layer 190 may fill the first recess 180 and may further grow upward to contact the lower sidewall of the gate spacer 160 . In this case, the source/drain layer 190 may grow not only in the vertical direction but also in the horizontal direction, and a cross section cut along the second direction D2 may have a shape similar to a pentagon. Meanwhile, when the separation distance between the active patterns 105 adjacent to each other in the second direction D2 is small, the source/drain layers 190 respectively grown from the upper surfaces of the active patterns 105 may be partially merged with each other. can

Thereafter, a first interlayer insulating film ( 200) may be formed and planarized until the upper surface of the dummy gate electrode 130 included in the dummy gate structure 150 is exposed. Accordingly, the dummy gate mask 140 included in the dummy gate structure 150 may be removed, and the upper portion of the gate spacer 160 may also be removed. The interlayer insulating layer 200 may include, for example, an oxide such as silicon oxide.

7 and 8 , a sacrificial layer 210 and a photoresist layer are sequentially formed on the interlayer insulating layer 200, the dummy gate electrode 130, and the gate spacer 160, and the photoresist layer is patterned to form the photoresist layer. patterns can be formed.

The sacrificial layer 210 includes, for example, an oxide such as TetraEthyl OrthoSilicate (TEOS), a spin-on-hardmask (SOH), an amorphous carbon layer (ACL), and the like. can do.

Thereafter, the sacrificial layer 210 may be etched by performing an etching process using the photoresist pattern as an etch mask, thereby exposing the upper surface of the dummy gate electrode 130 through the sacrificial layer 210 . One opening 230 may be formed.

In example embodiments, the first opening 230 overlaps a portion of the device isolation pattern 110 formed between the active patterns 105 disposed in the second direction D2 in the third direction D3. It may be formed to extend by a predetermined length in the first direction D1, for example, by a length equal to or greater than the width of the dummy gate electrode 130 in the first direction D1. Accordingly, in one embodiment, the first opening 230 is formed not only on the top surface of the dummy gate electrode 130 but also on the gate spacer 160 and/or the interlayer insulating film 200 adjacent thereto in the first direction D1. The top surface can also be exposed.

Referring to FIG. 9 , the top surface of the dummy gate electrode 130, the gate spacer 160 and/or the interlayer insulating film 200 exposed by the first opening 230, the sidewall of the first opening 230, and the sacrificial film A sacrificial spacer layer including, for example, silicon oxide may be formed on the upper surface of the 210 , and then the sacrificial spacer layer 240 may be formed on the sidewall of the first opening 230 by anisotropically etching the sacrificial spacer layer. .

In example embodiments, the sacrificial spacer layer may be formed through an atomic layer deposition (ALD) process and thus may have a thin thickness.

As the sacrificial spacer 240 is formed in the first opening 230 , the width of the first opening 230 in the second direction D2 may be reduced.

Referring to FIG. 10 , the top surface of the dummy gate electrode 130, the gate spacer 160 and/or the interlayer insulating film 200 exposed by the first opening 230, the sacrificial spacer 240, and the sacrificial film 210 A mask film filling the first opening 230 may be formed on the top surface of the mask film, and the mask film may be planarized until the upper surface of the sacrificial film 210 is exposed.

Accordingly, a mask 250 may be formed in the first opening 230 , and sidewalls of the mask 250 may be covered by the sacrificial spacer 240 .

Mask 250 may include, for example, a nitride such as silicon nitride.

Referring to FIG. 11 , the sacrificial layer 210 and the sacrificial spacer 240 may be removed.

In one embodiment, the sacrificial layer 210 and the sacrificial spacer 240 may be removed through a wet etching process. Alternatively, when the sacrificial layer 210 includes SOH or ACL, it may be removed through an ashing and/or stripping process.

As the sacrificial layer 210 and the sacrificial spacer 240 are removed, only the mask 250 may remain on the top surface of the dummy gate electrode 130 , the gate spacer 160 and/or the interlayer insulating layer 200 .

Referring to FIG. 12 , the dummy gate electrode 130 formed on the lower portion may be etched through an etching process using the mask 250 as an etching mask, and accordingly, the first separation pattern 135 is formed on the lower portion of the mask 250 . this may remain.

After performing the etching process, the mask 250 may be removed.

The first separation pattern 135 may be formed between the active patterns 105 disposed in the second direction D2 to separate them from each other.

Meanwhile, a portion where the dummy gate electrode 130 is removed may form a second opening 260 , and the dummy gate insulating pattern 120 may be exposed by the second opening 260 .

In one embodiment, the surface of the active pattern 105 may be exposed by additionally removing the exposed dummy gate insulating pattern 120. For example, a thermal oxidation process may be performed on the upper surface to form an interface pattern including silicon oxide.

Alternatively, the dummy gate insulating pattern 120 may not be removed and may be used as a part of a gate insulating pattern of a gate structure 300 (see FIGS. 13 to 15) to be formed later. Hereinafter, by way of example, only using the dummy gate insulating pattern 120 as a part of the gate insulating pattern without removing it will be described.

Referring to FIGS. 13 to 15 , a gate structure 300 filling the second opening 260 may be formed.

Specifically, the top surface of the dummy gate insulating pattern 120 exposed by the second opening 260, the sidewall and top surface of the first isolation pattern 135, the sidewall and top surface of the gate spacer 160, and the interlayer insulating layer 200 ), and a gate electrode film that sufficiently fills the remaining portion of the second opening 260 may be formed on the high-k dielectric layer.

The high dielectric layer may include, for example, a metal oxide having a high dielectric constant, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), or zirconium oxide (ZrO2).

The gate electrode film is, for example, a low-resistance metal such as tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or titanium aluminum acid. metal alloys, metal carbides, metal oxynitrides, metal carbonitrides, metal oxycarbonitrides such as nitride (TiAlON), titanium aluminum carbonitride (TiAlCN), titanium aluminum oxycarbonitride (TiAlOCN), and the like.

In an embodiment, before forming the gate electrode layer, a gate barrier layer may be further formed on the high dielectric layer. In this case, the gate barrier layer may include, for example, a metal nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), and tantalum aluminum nitride (TaAlN).

Thereafter, the gate electrode film, the gate barrier film, and the high dielectric film are planarized until the upper surfaces of the first separation pattern 135, the gate spacer 160, and the interlayer insulating film 200 are exposed, thereby opening a second opening ( The gate structure 300 may be formed in 260 .

The gate structure 300 may include a dummy gate insulating pattern 120, a high dielectric pattern 270, and a gate electrode 280 that are sequentially stacked, and between the high dielectric pattern 270 and the gate electrode 280 A gate barrier pattern may be further formed. In this case, the dummy gate insulating pattern 120 and the high dielectric pattern 270 may serve as a gate insulating pattern of the gate structure 300 together.

Referring to FIGS. 16 and 17 , a first capping layer 310 may be formed on the gate structure 300 , the gate spacer 160 , the first separation pattern 135 , and the interlayer insulating layer 200 .

The first capping layer 310 may include, for example, a nitride such as silicon nitride.

Then, by forming a contact plug and wires electrically connected to the source/drain layer 190 and/or the gate electrode 280, the gate electrode 280 including metal is provided and the first separation pattern 135 is formed. Manufacturing of the semiconductor device including the gate structures 300 separated from each other may be completed.

As described above, the gate structure 300 extending in the second direction D2 may be separated through the first separation pattern 135, and the first separation pattern 135 is, for example, in the second direction ( Instead of forming an opening by etching the dummy gate electrode 130 extending to D2) and filling the opening, it may be formed by leaving a portion of the dummy gate electrode 130 formed in the region to be separated. .

That is, as the degree of integration of the device increases, the distance between the active patterns 105 disposed in the second direction D2 decreases, and the dummy gate electrode 130 is formed in the region between the active patterns 105 through an etching process. ) may be etched to form an opening, the aspect ratio of the opening may be large, and accordingly, the dummy gate electrode 130 may not be properly etched during the etching process. As a result, when the dummy gate electrode 130 is removed and replaced with the gate electrode 280, the gate electrodes 280 to be separated from each other in the second direction D2 are not separated, and an electrical short may occur. .

However, in exemplary embodiments, an opening having a large aspect ratio is formed by etching the dummy gate electrode 130 extending in the second direction D2 and a separation pattern is not formed to fill the opening, but in an area to be separated. Second openings 260 separated in the second direction D2 by the first separation pattern 135 by removing portions other than the formed dummy gate electrode 130 through an etching process using a mask 250 , and forming the gate electrode 280 in each of the second openings 260 , the gate electrodes 280 adjacent to each other may not be connected to each other.

Accordingly, in the method of manufacturing the semiconductor device according to example embodiments, occurrence of an electrical short between gate electrodes 280 adjacent to each other in the second direction D2 may be prevented.

Meanwhile, by forming the sacrificial spacer 240 in the first opening 230, the width of the first separation pattern 135 formed with the dummy gate electrode 130 remaining can be adjusted in the second direction D2. Accordingly, even if the distance between the active patterns 105 adjacent to each other in the second direction D2 is reduced, the first separation pattern 135 having an appropriate width can be easily formed.

Meanwhile, the semiconductor device formed by the above processes may have the following structural characteristics.

That is, the semiconductor device protrudes from the top of the substrate 100, has a lower sidewall covered by the device isolation pattern 110, and extends in the first direction D1 and is spaced apart from each other in the second direction D2. patterns 105; gate structures 300 extending in the second direction D2 on the active patterns 105 and the device isolation pattern 110 and spaced apart from each other in the second direction D2; and a first separation pattern 135 formed between the gate structures 300 on the substrate 100 to separate them from each other and including polysilicon.

In example embodiments, the first separation pattern 135 may directly contact ends of the gate structures 300 in the second direction D2 .

In example embodiments, each of the gate structures 300 may include a first gate insulating pattern 120, a second gate insulating pattern 270, and a gate electrode 280 sequentially stacked. The first gate insulating pattern 120 may include silicon oxide, and the second gate insulating pattern 270 may include a high-k material such as metal oxide.

In example embodiments, the first separation pattern 135 may directly contact the second gate insulating pattern 270 .

18 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. Specifically, FIGS. 18 and 20 are cross-sectional views taken along the line A-A' of the corresponding plan views, and FIG. 19 is a cross-sectional view taken along the line BB' of the corresponding plan views.

Since the method of manufacturing the semiconductor device includes substantially the same or similar processes as those described with reference to FIGS. 1 to 17 , redundant descriptions will be omitted.

Referring to FIGS. 18 and 19 , after processes substantially the same as or similar to those described with reference to FIGS. 1 to 15 are performed, an upper portion of the gate structure 300 may be removed to form a second recess. .

Thereafter, a second capping layer filling the second recess is formed on the gate structure 300 , the gate spacer 160 , the first separation pattern 135 and the interlayer insulating layer 200 , and the gate spacer 160 The second capping layer may be planarized until upper surfaces of the first separation pattern 135 and the interlayer insulating layer 200 are exposed.

Accordingly, the second capping pattern 315 may be formed on the gate structure 300 . The second capping pattern 315 may include, for example, a nitride such as silicon nitride.

Referring to FIG. 20 , the first separation pattern 135 is removed to form a third opening exposing the upper surface of the dummy gate insulating pattern 120, and a second separation film filling the opening is formed to expose the exposed dummy gate insulating pattern 120. ) After forming on the upper surface, the second capping pattern 315, the gate spacer 160, and the interlayer insulating film 200, the upper surface of the second capping pattern 315, the gate spacer 160, and the interlayer insulating film 200 is By flattening it until it is exposed, the second separation pattern 320 may be formed.

The second separation pattern 320 may include, for example, a nitride such as silicon nitride.

Unlike the formation of the first isolation pattern 135 containing polysilicon in the semiconductor device described with reference to FIGS. 1 to 17 through the above process, the second isolation pattern 320 containing nitride may be formed. can

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand that you can.

The above-described semiconductor device includes, for example, a logic device such as a central processing unit (CPU, MPU), an application processor (AP), and the like, a volatile memory device such as an SRAM device and a DRAM device, and For example, in a method of manufacturing a nonvolatile memory device such as a flash memory device, a PRAM device, an MRAM device, and an RRAM device, a separation pattern forming process for separating a gate electrode including a metal The separation pattern may be applied not only to the illustratively described finFET, but also to a Multi-Bridge Channel FET (MBCFET) or a Gate All Around (GAA) transistor.

100: substrate 105: active region, active pattern
105a, 105b: lower, upper active patterns
110: element isolation pattern
120: dummy gate insulating pattern, first gate insulating pattern
130: dummy gate electrode 135, 320: first and second separation patterns
140: dummy gate mask 150: dummy gate structure
160: gate spacer 170: pin spacer
180: first recess 190: source/drain layer
200: interlayer insulating film 210: sacrificial film
230, 260: first and second openings
270: high dielectric pattern, second gate insulation pattern
270: gate insulation pattern 280: gate barrier
280: gate electrode 300: gate structure
310: first capping layer 315: second capping pattern

Claims (10)

The device isolation pattern protrudes from the top of the substrate and covers the lower sidewall, each extends in a first direction parallel to the upper surface of the substrate, and mutually extends in a second direction parallel to the upper surface of the substrate and intersecting the first direction. active patterns spaced apart;
gate structures extending in the second direction on the active patterns and the device isolation pattern and spaced apart from each other in the second direction; and
A semiconductor device comprising: an isolation pattern formed between the gate structures on the substrate to separate the gate structures from each other and including polysilicon. The semiconductor device of claim 1 , wherein the separation pattern directly contacts ends of the gate structures in the second direction. The method of claim 1 , wherein each of the gate structures includes a first gate insulating pattern, a second gate insulating pattern, and a gate electrode sequentially stacked,
The semiconductor device of claim 1 , wherein the first gate insulating pattern includes silicon oxide, and the second gate insulating pattern includes metal oxide. The semiconductor device of claim 3 , wherein the isolation pattern directly contacts the second gate insulating pattern. forming a dummy gate structure on a substrate and extending in a first direction parallel to an upper surface of the substrate;
forming a mask on the dummy gate structure;
forming an isolation pattern by etching the dummy gate structure by performing an etching process using the mask, wherein first openings are formed on both sides of the isolation pattern in the first direction; and
and forming a gate structure filling each of the first openings. The method of claim 5 , wherein the dummy gate structure includes a dummy gate electrode made of polysilicon, and thus the separation pattern includes polysilicon. 6. The method of claim 5, wherein forming the mask on the dummy gate structure
forming a sacrificial layer including a second opening on the dummy gate structure;
forming a sacrificial spacer on a sidewall of the second opening in the first direction;
forming the mask filling the second opening; and
A method of manufacturing a semiconductor device comprising removing the sacrificial layer and the sacrificial spacer. 8. The method of claim 7, wherein forming the sacrificial spacer
forming a sacrificial spacer layer on a bottom surface and a sidewall of the second opening and on the sacrificial layer; and
A method of manufacturing a semiconductor device comprising anisotropically etching the sacrificial spacer layer. 6. The method of claim 5, before forming the dummy gate structure.
partially removing an upper portion of the substrate to form trenches parallel to the upper surface of the substrate and extending in a second direction crossing the first direction; and
forming device isolation patterns under the trenches to define active patterns that protrude above the substrate, extend in the second direction, and are spaced apart from each other in the first direction;
The dummy gate structure is formed on the active patterns and the device isolation pattern. The method of claim 9 , wherein the mask overlaps a region between adjacent active patterns in a third direction perpendicular to the upper surface of the substrate in the first direction.