DE102019117707B4 - Semiconductor die and antenna tuner - Google Patents

Abstract

Semiconductor die (10) comprising at least one first sealing wall (30) adjacent to an edge (35) of the semiconductor die (10), the first sealing wall (30) having at least partially a periodically alternating path, based on the periodically alternating path an overall length of the first sealing wall (30) is increased compared to a non-periodically alternating path, the first sealing wall (30) being at least partially formed by vias (60) and at least some of the vias (60) of the first sealing wall ( 30) are through-silicon vias that extend completely through the semiconductor die (10).

Description

Technical area

The present application relates to a semiconductor die and an antenna tuner including the semiconductor die.

background

In the manufacture of 3D integrated ICs manufactured at the wafer level, the semiconductor dies are assembled in a 3D stack by bonding complete semiconductor wafers, with each wafer comprising several dies on its surface to form a wafer stack to form, followed by the separation of the stack into separate 3D chips. Separating a stack of wafers is particularly difficult when using standard dicing methods, such as laser dicing or dicing using a cutter. One particular problem is that low-k dielectrics and ultra-low-k dielectrics used in integrated circuits today are increasingly porous and fragile. The answer to this challenge today is the use of sealing rings around an outer circumference of such dies. Several stabilizing frames are used to improve stability. 1 shows a semiconductor die 1 with two sealing rings 2 according to the state of the art. The semiconductor die 1 comprises a substrate 3 and two sealing rings 2 . The sealing rings 2 are arranged near substrate edges. The sealing rings run in a straight line parallel to the respective substrate edges. The sealing rings surround the semiconductor die.

Since these frames are usually closed loops, they can act as a coil, which can adversely affect the electrical performance of an electrical circuit of the semiconductor die.

The state of the art document KR 10 0 444 012 B1 discloses a guard ring of a semiconductor chip for distributing stress to a side portion of the semiconductor chip and protecting the inside of the semiconductor from moisture by forming a pattern of the guard ring with a zigzag pattern. The state of the art document US 2006/0 220 250 A1 discloses a pattern for a crack stop and moisture barrier for a semiconductor device including a plurality of discrete conductive features formed on the edge of an integrated circuit near a scribe line. The discrete conductive features can include a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.

The state of the art document US 2016/0 172 359 A1 discloses a moisture barrier structure including an active fin disposed on a sealing area of a substrate, the substrate including a chip area and the sealing area surrounding a periphery of the chip area, the active fin continuously surrounding the chip area and having a sinuous line shape in plan view. The state of the art document US 2016/0 233 178 A1 discloses an RF transmission device including at least one substrate having first and second surfaces facing each other; a first electronic RF transmission circuit which is arranged on and / or in the substrate; a first antenna disposed on the side of the first surface of the substrate, spaced from the first surface of the substrate, and electrically connected to the first RF electronic transmission circuit; a first reflector for electromagnetic waves, which is coupled to the first antenna and a first high-resistance surface with at least a plurality of first electrically conductive elements that form a first periodic structure and are arranged on the first surface of the substrate opposite the first antenna and a first electrically conductive base plate, which is at least partially arranged opposite the first antenna, comprises.

One object of the present disclosure is to provide a semiconductor die with strong mechanical support which has little or no effect on the electrical performance of an electrical circuit arranged on the semiconductor die.

short version

According to the present disclosure, one or more of the above-mentioned objects are achieved by a semiconductor die according to the features of claim 1.

One or more of the above-mentioned objects can also be achieved by an antenna tuner according to the features of the present claim 15.

Advantageous embodiments are given in the subclaims.

In a first aspect of the present disclosure, a semiconductor die is presented. The semiconductor die comprises at least one first sealing wall next to an edge of the semiconductor die, the first sealing wall at least partially having a periodically alternating path, wherein, based on the periodically alternating path, a total length of the first sealing wall im Compared to a non-periodically alternating path, the first sealing wall is at least partially formed by vias and at least some of the vias of the first sealing wall are through silicon vias that extend completely through the semiconductor die. The lengthening of the overall length of the first sealing wall advantageously increases the mechanical support function of the first sealing wall.

According to embodiments of the first aspect, the semiconductor die comprises, in addition to the first sealing wall, a second sealing wall which is arranged parallel to the first sealing wall. Thus, the semiconductor die preferably includes a pair of sealing walls. This advantageously further improves the mechanical support function.

According to embodiments of the first aspect, the first sealing wall comprises multiple interruptions in at least one section of the first sealing wall and / or the second sealing wall comprises multiple interruptions in at least one section of the second sealing wall. This means that the respective sealing wall is not continuous, but rather has several openings. The interruptions or openings can have a positive effect on the electrical performance of an electrical circuit of the semiconductor die, since there are no closed loops that can act as coils.

According to embodiments of the first aspect, a distance between respective adjacent interruptions of at least some of the interruptions of the first sealing wall is dependent on the periodicity of the alternately shaped path of the first sealing wall. Alternatively or additionally, a distance between respective adjacent interruptions of at least some of the interruptions in the second sealing wall is dependent on the periodicity of the alternately shaped path of the second sealing wall. In particular, the distance corresponds to the respective periodicity or corresponds to a multiple of the respective periodicity. In this way, a constant maximum distance can be achieved between the respective interruptions, whereby a maximum or very good mechanical support function of the sealing walls can be maintained.

According to embodiments of the first aspect, the interruptions in the first sealing wall and the second wall are arranged alternately with respect to an axis running along the edges of the semiconductor die. The supporting function of the sealing walls can advantageously be improved in this way.

According to embodiments of the first aspect, the interruptions of the first sealing wall and the second sealing wall are offset by a half period of the periodicity of the alternately shaped path or by an integral multiple of a half period of the periodicity of the alternately shaped path.

According to embodiments of the first aspect, the interruptions are arranged at vertices or in vertex regions of the alternately shaped path of the first sealing wall and / or the second sealing wall.

In this way, a constant maximum distance between the interruptions in the first sealing wall and the second sealing wall can be achieved, as a result of which the mechanical support function of the sealing walls is further improved.

According to embodiments of the first aspect, the semiconductor die comprises a semiconductor substrate and a plurality of low-k dielectric layers on the semiconductor substrate. Advantageously, this allows flexible circuit design on the semiconductor die, and very good analog performance can be achieved.

According to embodiments of the first aspect, the first sealing wall and / or the second sealing wall is / are at least partially formed by vias, and the vias of the first sealing wall and / or the second sealing wall are through silicon vias that extend completely through the semiconductor die extend. It goes without saying that the term “through silicon via” is a technical term that is used in technology. The term is used to describe a via through a substrate that is used in the manufacture of an integrated circuit and is not necessarily limited to a "silicon" substrate. A via is a through connection that can have any shape. Thus, a via does not necessarily have a round or elliptical cross-sectional shape with respect to an upper or lower side of the semiconductor die. Furthermore, the plated-through holes preferably have a tapering profile with regard to a cross section running vertically to the top or bottom of the semiconductor die. Tapered plated-through holes are more effective in transmitting stress in the direction of the end comprising the smaller diameter.

According to embodiments of the first aspect, at least some of the vias of the first sealing wall and / or the second sealing wall comprise a respective filled one Trench that forms a respective metal wall part. An advantageous feature of such trenches is that they perform better than a sealing ring of in-line through hole mounting vias when a crack occurs and spreads, for example during die sawing. The rift is stopped by the trenches. Even if the crack spreads beyond the trenches, the stress on the crack from the trenches is significantly reduced. The trenches can also be formed by a “through silicon via”.

According to embodiments of the first aspect, the semiconductor die comprises a ring of layer vias in each of its layers for each of the sealing walls, the layer vias of the various layers being connected to one another to form respective through silicon vias. In this way, the manufacturing process can be simplified. The layer vias preferably have a tapering profile with regard to a cross section running vertically to the top or bottom of the semiconductor die.

According to embodiments of the first aspect, the first sealing wall and / or the second sealing wall is / are at least partially formed by stacked metal layer traces.

According to embodiments of the first aspect, the semiconductor die comprises, in addition to the first sealing wall and the second sealing wall, at least one pair of sealing walls. In this way, the mechanical support function of the sealing walls can be further improved.

According to embodiments of the first aspect, the at least one more pair of sealing walls is arranged and configured in such a way that the periodicity of the interruption arrangement from the outer part to the inner part along a direction running vertically to the respective edge and parallel to the top and bottom of the semiconductor die Part of the semiconductor die is continuous.

According to a second aspect, the present disclosure provides an antenna tuner comprising a semiconductor die according to the first aspect or according to any of the embodiments of the first aspect. Due to their stack of bonded wafers and very brittle low-k materials (for example hydrogen-rich SiOx), antenna tuners are usually very brittle constructions. In the antenna tuner according to the second aspect, these components can be used as disk components.

Figure list

It should be understood that both the preceding general description and the following detailed description are exemplary only and are intended to provide an overview or framework for understanding the nature and essence of the claims. The accompanying drawings are included to facilitate understanding and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiments and, together with the description, serve to explain the principles and mode of operation of the various embodiments. The same elements in different figures of the drawings are denoted by the same reference symbols.

• 1 ein Halbleiter-Die, das zwei Dichtungswände gemäß dem Stand der Technik umfasst,
• 2 ein Ausführungsbeispiel eines Halbleiter-Dies,
• 3a und 3b das Verhalten eines Spannungsfelds hinsichtlich geradliniger Dichtungswände,
• 4a und 4b das Verhalten eines Spannungsfelds hinsichtlich wellenförmiger Doppeldichtungswände,
• 5a und 5b das Verhalten eines Spannungsfelds hinsichtlich wellenförmiger Multidichtungswände und
• 6 einen Querschnitt eines Ausführungsbeispiels einer Dichtungswandanordnung.

In the figures show:

• 1 a semiconductor die comprising two sealing walls according to the prior art,
• 2 an embodiment of a semiconductor die,
• 3a and 3b the behavior of a stress field with regard to rectilinear sealing walls,
• 4a and 4b the behavior of a stress field with regard to undulating double sealing walls,
• 5a and 5b the behavior of a stress field with regard to undulating multi-sealing walls and
• 6th a cross section of an embodiment of a sealing wall assembly.

DETAILED DESCRIPTION OF THE DRAWINGS

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings showing embodiments of the disclosure. However, the disclosure can take many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, it is intended that these embodiments are provided so that this disclosure will fully convey the scope of the disclosure to those skilled in the art. While features of the present disclosure may be discussed with respect to particular embodiments and figures below, all embodiments of the present disclosure may include one or more of the advantageous features discussed herein. In other words, although possibly having one or more embodiments as certain advantageous features As discussed, one or more such features may also be used in accordance with the various embodiments of the disclosure discussed herein. While exemplary embodiments are discussed below as device, system, or method embodiments, it should be understood that such exemplary embodiments can be implemented in various devices, systems, and methods.

The drawings are not necessarily drawn to scale, but are designed to clearly illustrate the disclosure.

2 shows an embodiment of a semiconductor die 10 .

The semiconductor die 10 comprises a substrate 20th . Optionally, the semiconductor die 10 multiple dielectric layers on the semiconductor substrate 20th . For example, at least one of the semiconductor dielectric layers is a low-k dielectric layer.

The semiconductor die also includes 10 at least one first sealing wall 30th . The first sealing wall 30th is next to an edge 35 of the semiconductor die 10 arranged. The first sealing wall 30th has at least partially a periodically alternating path. A periodicity of such an alternately shaped path corresponds, for example, to 10 μm to 150 μm, preferably 10 μm to 50 μm. Assuming a certain chip length, for example a length of 300 µm to 2 mm, there are more than two “half waves” per die edge.

The embodiment of the in 2 shown semiconductor dies 10 preferably comprises in addition to the first sealing wall 30th a second sealing wall 40 .

The sealing walls 30th , 40 stabilize in particular the circumference of the die and reduce the tendency of a brittle layer stack to delaminate and tear under external thermo-mechanical load.

The first sealing wall 30th and the second sealing wall 40 are near the edges 35 of the semiconductor die 10 arranged. The first sealing wall 30th and the second sealing wall 40 at least partially surround the semiconductor die 10 . The first sealing wall 30th and / or the second sealing wall 40 each have at least partially a periodically alternating path. The path comprises at least partially a wave-like shape, for example a sinusoidal shape or a zigzag shape or a rectangular pulse shape. However, mixtures of shapes are also possible, for example one half-wave comprises a sinusoidal shape and the other half-wave comprises a zigzag shape. Alternatively, it is possible that one half-wave comprises a sinusoidal shape or zigzag shape and the other half-wave comprises a straight line.

Preferably the first sealing wall 30th and the second sealing wall 40 arranged parallel to each other, that is, the first sealing wall 30th and the second sealing wall 40 have a constant distance from each other.

The first sealing wall 30th and / or the second sealing wall 40 includes metal vias 60 . In particular, the first sealing wall will be 30th and / or the second sealing wall 40 each formed by vias arranged one behind the other. The construction of the vias 60 will be referred to later on 6th described.

Optionally comprises the first sealing wall 30th and / or the second sealing wall 40 several interruptions 50 , that is, the walls are not continuous, but have several openings that the continuous path of the sealing walls 30th , 40 interrupt. Thus, the interruptions 50 also referred to as "openings" or "holes".

The interruptions 50 the sealing walls 30th , 40 have a positive effect on the electrical behavior of a semiconductor die 10 arranged electrical circuit.

A sealing wall comprising a continuous metal wall can act like a coil causing inductive interference, which adversely affects the electrical performance of the electrical circuit of the semiconductor die 10 can affect.

Thus, breaking the sealing wall can interrupt the electric performance of the electric circuit of the semiconductor die 10 , especially in high frequency applications.

However, such discontinuous sealing walls, which are not constrained by inductive interference, may not be as stable due to shorter path lengths and may also perform poorly in preventing cracking or delamination along a stress field. The influence of a configuration of the sealing wall on the behavior of the stress field is described below with reference to FIG 3a and 3b explained.

A field of tension that occurs on a perimeter of the semiconductor die 10 is reduced if it is applied to a straight, continuous sealing wall, in particular a continuous metal wall, meets. In the case of the interrupted wall, the field of tension is concentrated and thereby decreases at the opening or interruption 50 and also curves locally and follows the direction of the shortest path between two adjacent openings, while deviating only slightly from the effective vector of the stress field. The effective vector of the stress field results from a superposition of different stress vectors.

the 4a and 4b represent the behavior of a stress field with regard to undulating double sealing walls, whereby the sealing walls 30th , 40 appropriate interruptions 50 include.

The first sealing wall 30th and the second sealing wall 40 each include a path with a wave-like shape. The first sealing wall 30th and the second sealing wall 40 are at least partially at a constant distance from one another. The first sealing wall 30th and the second sealing wall 40 form a double-row outer frame.

For a construction of a double-row outer frame, the interruptions 50 for example generated so that the distance from any inner wall interruption 50 (in the 2 , 4a and 4b the interruption of the second sealing wall 40 ) to the next interruption 50 in the outer wall (in the 2 , 4a and 4b the interruption 50 the first sealing wall 30th ) is as big as possible. The distance itself can vary depending on the period of the alternating function, for example the sine function or zigzag shape of the walls themselves.

In at least a portion of the first sealing wall 30th is the distance between adjacent breaks 50 the first sealing wall 30th constant or approximately constant, and also in at least a portion of the second sealing wall 40 is the distance between adjacent breaks 50 the second sealing wall 40 constant or approximately constant. For example are the interruptions 50 at vertices or in vertex areas of the respective sealing wall 30th , 40 , for example at every other vertex or in every other vertex area.

The interruptions 50 the first sealing wall 30th and the second sealing wall 40 are offset by a half-wave or a half-period, for example.

In the event that each of the adjacent sealing walls 30th , 40 a waveform and the breaks 50 , as described above, the stress field emanating from the circumference follows the shape of the outermost sealing wall (in the 2 , 4a and 4b the first sealing wall 30th ) until the interruption occurs 50 of two adjacent segments of this sealing wall 30th concentrated. From here the local field vector has to be curved in an opposite or reversed direction of the effective vector of the stress field, around the next neighboring interruption 50 in the sealing wall 30th to find. The resulting effective vector is the vector sum of both the local and the effective vector, which is greatly diminished due to the small angle between them and ultimately disappears completely. This means that any on the perimeter of the semiconductor die 10 formed crack or delamination, which follows the effective stress field, on the innermost sealing wall (in the 2 , 4a and 4b the second sealing wall 40 ) is effectively stopped. A risk of mechanical failure of the internal structures can be reduced to a minimum, thereby increasing the overall reliability of the semiconductor die 10 is greatly increased.

the 5a and 5b illustrate the behavior of a stress field with regard to undulating multi-sealing walls, the sealing walls with suitably arranged interruptions 50 include.

As in the 5a and 5b is shown for more than two sealing walls, the periodicity is repeated. Starting with the counting at the innermost sealing wall, the wall which comprises the greatest distance from the substrate edge, every other odd-numbered sealing wall has the same opening periodicity or multiples or fractions thereof. For example, the third sealing wall has only half the number of openings compared to the sealing wall counted first. If there are openings in the third wall, then they are nonetheless also present in the first wall counted. The same logic applies to even numbers, starting from the second innermost sealing wall.

6th Figure 13 shows a cross-sectional view of one embodiment of a sealing wall assembly.

The vias 60 the first sealing wall 30th and / or the second sealing wall 40 are, for example, through-silicon vias that extend completely through the semiconductor die 10 extend.

At least some of the vias 60 the first sealing wall 30th and / or the second sealing wall 40 include, for example, a respective filled trench which forms a respective metal wall part. For example, the semiconductor die includes 10 in each of its layers for each of the sealing walls 30th , 40 a ring of layer vias 65 , with the layer vias 65 of the different layers are connected to one another and thus form respective through-silicon vias. Thus the vias are 60 the first sealing wall 30th and / or the second sealing wall 40 Through silicon vias, which are formed by offset layer vias, each of which includes a metal-filled trench.

List of reference symbols

1, 10

Semiconductor die

2, 20

Substrate

3, 30

first sealing wall

35

Edge of semiconductor die

40

second sealing wall

50

Interruption

60

Via

65

Layer via

A.

axis

D.

direction

Claims (15)

Semiconductor die (10) comprising at least one first sealing wall (30) adjacent to an edge (35) of the semiconductor die (10), wherein the first sealing wall (30) has at least partially a periodically alternating path, based on the periodically alternating path an overall length of the first sealing wall (30) is increased compared to a non-periodically alternating path, the first sealing wall (30) being at least partially formed by vias (60) and at least some of the vias (60) of the first sealing wall ( 30) are through silicon vias that extend completely through the semiconductor die (10). Semiconductor Die (10) according to Claim 1 wherein the semiconductor die (10) comprises, in addition to the first sealing wall (30), a second sealing wall (40) which is arranged parallel to the first sealing wall (30). Semiconductor Die (10) according to Claim 1 or Claim 2 wherein the first sealing wall (30) comprises several interruptions (50) in at least one section of the first sealing wall (30) and / or the second sealing wall (40) comprises several interruptions (50) in at least one section of the second sealing wall (40). Semiconductor Die (10) according to Claim 3 , wherein - in at least some of the interruptions (50) of the first sealing wall (30), a distance between respective adjacent interruptions (50) of the first sealing wall (30) is dependent on the periodicity of the alternately shaped path of the first sealing wall (30), and / or - in at least some of the interruptions (50) of the second sealing wall (40), a distance between respective adjacent interruptions (50) of the second sealing wall (40) is dependent on the periodicity of the alternately shaped path of the second sealing wall (40). Semiconductor die (10) according to one of the Claims 3 until 4th wherein the interruptions (50) of the first sealing wall (30) and the second wall are arranged alternately with respect to an axis (A) running along the edges (35) of the semiconductor die (10). Semiconductor Die (10) according to Claim 5 wherein the interruptions (50) of the first sealing wall (30) and the second sealing wall (40) are offset by a half period of the periodicity of the alternately shaped path or by an integral multiple of a half period of the periodicity of the alternately shaped path. Semiconductor Die (10) according to Claim 5 or 6th wherein the interruptions (50) are arranged at vertices or in vertex regions of the alternately shaped path of the first sealing wall (30) and / or the second sealing wall (40). Semiconductor die (10) according to one of the Claims 1 until 7th wherein the semiconductor die (10) comprises a semiconductor substrate (20) and a plurality of low-k dielectric layers on the semiconductor substrate (20). Semiconductor die (10) according to one of the Claims 2 until 8th wherein the first sealing wall (30) and the second sealing wall (40) are at least partially formed by vias (60) and at least some of the vias (60) of the first sealing wall (30) and the second sealing wall (40) are formed by silicon vias which extend completely through the semiconductor die (10). Semiconductor die (10) according to one of the Claims 2 until 9 , wherein the first sealing wall (30) and / or the second sealing wall (40) is / are at least partially formed by vias (60) and at least some of the vias (60) of the first sealing wall (30) and / or the second sealing wall (40) ) a respective include filled trench, which forms a respective metal wall part. Semiconductor die (10) according to one of the Claims 1 until 10 wherein the semiconductor die (10) comprises a ring of layer vias (65) in each of its layers for each of the sealing walls, the layer vias (65) of the various layers being connected to one another to form respective through-silicon vias . Semiconductor die (10) according to one of the Claims 2 until 11th , wherein the first sealing wall (30) and / or the second sealing wall (40) is / are at least partially formed by stacked metal layer traces. Semiconductor die (10) according to one of the Claims 2 until 12th , wherein the semiconductor die (10) comprises at least one pair of sealing walls in addition to the first sealing wall (30) and the second sealing wall (40). Semiconductor Die (10) according to Claim 13 , wherein the at least one more pair of sealing walls is arranged and configured in such a way that the interruption periodicity repeats along a direction (D) extending vertically to the respective edge (35) of the semiconductor die (10). Antenna tuner which the semiconductor die (10) after one of the Claims 1 until 14th includes.

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