KR102450571B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention provides a memory provided on a first substrate, a peripheral circuit region including circuit elements, and a second substrate disposed on the first substrate, the memory including memory cells a cell region, and a through-wiring region extending in a first direction through the memory cell region and the second substrate and including a through contact plug electrically connecting the memory cell region and circuit elements and an insulating region surrounding the through contact plug; wherein the insulating region penetrates through the second substrate and is disposed between the first insulating layer disposed in parallel with the second substrate, the second insulating layers disposed to extend in the first direction, and the second insulating layers, and a third insulating layer having a vertical extension extending in a first direction and horizontal extensions extending in a second direction parallel to the upper surface of the second substrate from a side surface of the vertical extension so as to be in contact with the second insulating layers.

Description

semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device.

Semiconductor devices require high-capacity data processing while their volume is getting smaller. In particular, in the case of a memory semiconductor device, an arrangement structure and/or a wiring structure of operating circuits included in the semiconductor device are becoming more complicated as the size of a memory cell for high integration is reduced. Accordingly, there is a demand for a semiconductor device that is easy to process while improving the degree of integration of the semiconductor device.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device with improved integration and reliability.

A semiconductor device according to example embodiments is provided on a first substrate, a peripheral circuit region including circuit elements, a second substrate disposed on the first substrate, and including memory cells. a memory cell region, a through contact plug extending in a first direction through the memory cell region and the second substrate and electrically connecting the memory cell region and the circuit elements, and an insulating region surrounding the through contact plug; a through wiring region including: a first insulating layer penetrating the second substrate and disposed in parallel with the second substrate; second insulating layers extending in the first direction; and a second direction parallel to the upper surface of the second substrate from a side surface of the vertical extension part disposed between the second insulating layers and in contact with the vertical extension part extending in the first direction and the second insulating layers. and a third insulating layer having extended horizontal extensions.

A semiconductor device according to example embodiments is provided on a first substrate, a peripheral circuit region including circuit elements, a second substrate disposed on the first substrate, and on the second substrate a memory cell region including gate electrodes stacked vertically spaced apart from each other, channels passing through the gate electrodes and extending vertically on the second substrate, and an insulation penetrating the gate electrodes and the second substrate and a through wiring region including a through contact plug extending vertically through the region and the insulating region, wherein the insulating region includes vertical extensions extending in a first direction perpendicular to the first and second substrates; Horizontal extensions extending in a second direction perpendicular to the first direction from side surfaces of the vertical extensions may be provided.

A semiconductor device according to example embodiments includes a first region including first elements, a second region provided at one side of the first region, and a second region including second elements, and an upper portion of the second region and a through wiring region including a through wiring structure electrically connecting the first elements and the second elements and an insulating region surrounding the through wiring structure, wherein the insulating region is disposed in a first direction It may include vertical insulating layers extending and horizontal insulating layers extending in a second direction perpendicular to the first direction between the vertical insulating layers.

A semiconductor device having improved integration and reliability can be provided by forming a through wiring region including a plurality of insulating layers in the memory cell region.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic block diagram of a semiconductor device according to example embodiments.
2 is an equivalent circuit diagram of a cell array of a semiconductor device according to example embodiments.
3 is a schematic layout diagram for explaining the arrangement of semiconductor devices according to example embodiments.
4 is a schematic plan view of a semiconductor device according to example embodiments.
5A and 5B are schematic cross-sectional views of semiconductor devices according to example embodiments.
6A and 6B are partially enlarged views of a semiconductor device according to example embodiments.
7A to 7D are schematic layout diagrams of semiconductor devices according to example embodiments.
8 is a schematic cross-sectional view of a semiconductor device according to example embodiments.
9 is a schematic cross-sectional view of a semiconductor device according to example embodiments.
10 is a schematic cross-sectional view of a semiconductor device according to example embodiments.
11A to 11J are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
12A to 12G are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments.
13 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of a semiconductor device according to example embodiments.

Referring to FIG. 1 , a semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30 . The peripheral circuit 30 may include a row decoder 32 , a page buffer 34 , an input/output buffer 35 , a control logic 36 , and a voltage generator 37 .

The memory cell array 20 includes a plurality of memory blocks, and each memory block may include a plurality of memory cells. The plurality of memory cells may be connected to the row decoder 32 through a string select line SSL, word lines WL, and a ground select line GSL, and may be connected to a page buffer 32 through bit lines BL. 34) can be connected. In example embodiments, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

The row decoder 32 may decode the input address ADDR to generate and transmit driving signals of the word line WL. The row decoder 32 may provide the word line voltage generated from the voltage generator 37 to the selected word line WL and the unselected word lines WL in response to the control of the control logic 36 , respectively.

The page buffer 34 may be connected to the memory cell array 20 through bit lines BL to read information stored in the memory cells. The page buffer 34 may temporarily store data to be stored in the memory cells or sense data stored in the memory cells according to an operation mode. The page buffer 34 may include a column decoder and a sense amplifier. The column decoder may selectively activate the bit lines BL of the memory cell array 20 , and the sense amplifier senses a voltage of the bit line BL selected by the column decoder during a read operation to select the selected bit line BL. Data stored in the memory cell can be read.

The input/output buffer 35 may receive data DATA during a program operation and transmit it to the page buffer 34 , and may output the data DATA received from the page buffer 34 during a read operation to the outside. The input/output buffer 35 may transfer an input address or command to the control logic 36 .

The control logic 36 may control operations of the row decoder 32 and the page buffer 34 . The control logic 36 may receive a control signal and an external voltage transmitted from the outside, and operate according to the received control signal. The control logic 36 may control read, write, and/or erase operations in response to the control signals.

The voltage generator 37 may generate voltages necessary for an internal operation, for example, a program voltage, a read voltage, and an erase voltage, by using an external voltage. The voltage generated by the voltage generator 37 may be transmitted to the memory cell array 20 through the row decoder 32 .

2 is an equivalent circuit diagram of a cell array of a semiconductor device according to example embodiments.

Referring to FIG. 2 , the memory cell array 20 includes memory cells MC that are serially connected to each other, a ground select transistor GST and a string select transistor SST1 that are connected in series across both ends of the memory cells MC; A plurality of memory cell strings S including SST2 may be included. The plurality of memory cell strings S may be connected in parallel to respective bit lines BL0 - BL2. The plurality of memory cell strings S may be commonly connected to a common source line CSL. That is, a plurality of memory cell strings S may be disposed between the plurality of bit lines BL0 - BL2 and one common source line CSL. In an exemplary embodiment, a plurality of common source lines CSL may be two-dimensionally arranged.

The memory cells MC connected in series with each other may be controlled by word lines WL0 - WLn for selecting the memory cells MC. Each of the memory cells MC may include a data storage element. Gate electrodes of the memory cells MC disposed at substantially the same distance from the common source line CSL may be commonly connected to one of the word lines WL0 - WLn to be in an equipotential state. Alternatively, even if the gate electrodes of the memory cells MC are disposed at substantially the same distance from the common source lines CSL, the gate electrodes disposed in different rows or columns may be independently controlled.

The ground select transistor GST is controlled by the ground select line GSL and may be connected to the common source line CSL. The string select transistor SST is controlled by the string select lines SSL1 and SSL2 and may be connected to the bit lines BL0 - BL2. FIG. 2 illustrates a structure in which one ground select transistor GST and two string select transistors SST1 and SST2 are connected to a plurality of memory cells MC connected in series with each other, respectively. The transistors SST1 and SST2 may be connected, or a plurality of ground select transistors GST may be connected. One or more dummy lines DWL or buffer lines may be further disposed between the uppermost word line WLn and the string selection lines SSL1 and SSL2 among the word lines WL0 - WLn. In an exemplary embodiment, one or more dummy lines DWL may also be disposed between the lowest word line WL0 and the ground selection line GSL.

When a signal is applied to the string select transistors SST1 and SST2 through the string select lines SSL1 and SSL2 , the signal applied through the bit lines BL0 - BL2 is transmitted to the memory cells MC connected in series with each other, so that data Read and write operations may be executed. Also, an erase operation of erasing data written in the memory cells MC may be performed by applying a predetermined erase voltage through the substrate. In an exemplary embodiment, the memory cell array 20 may include at least one dummy memory cell string electrically isolated from the bit lines BL0 - BL2 .

3 is a schematic layout diagram for explaining the arrangement of semiconductor devices according to example embodiments.

Referring to FIG. 3 , the semiconductor device 10A may include first and second regions R1 and R2 stacked in a vertical direction. The first region R1 may constitute the peripheral circuit 30 of FIG. 1 , and the second region R2 may constitute the memory cell array 20 .

The first region R1 may include a row decoder DEC, page buffers PB1 and PB2 , a pad circuit PAD, and other peripheral circuits PERI. The second region R2 may include memory cell arrays MCA1 and MCA2 and first and second through-line regions TB1 and TB2.

In the first region R1 , the row decoder DEC may correspond to the row decoder 32 described above with reference to FIG. 1 , and the page buffers PB1 and PB2 may correspond to the page buffer 34 . . Also, the other peripheral circuit PERI may be a region that includes the control logic 36 and voltage generator 37 of FIG. 1 , such as a latch circuit, a cache circuit, or a sense amplifier. (sense amplifier) may be included. The pad circuit PAD may be an area including the input/output buffer 35 of FIG. 1 , and may include an electrostatic discharge (ESD) device or a data input/output circuit.

At least some of the various circuit regions DEC, PB1, PB2, PERI, and PAD in the first region R1 may be disposed below the memory cell arrays MCA1 and MCA2 in the second region R2. have. For example, as indicated by a dotted line in FIG. 3 , the page buffers PB1 and PB2 and other peripheral circuits PERI are disposed under the memory cell arrays MCA1 and MCA2 in the memory cell arrays MCA1 and MCA2. It may be arranged to overlap. However, in embodiments, the circuits and arrangement form included in the first region R1 may be variously changed, and accordingly, circuits disposed to overlap the memory cell arrays MCA1 and MCA2 are also variously changed. can be

In the second region R2 , the memory cell arrays MCA1 and MCA2 may be spaced apart from each other and disposed in parallel. However, in embodiments, the number and arrangement of the memory cell arrays MCA1 and MCA2 disposed in the first region R2 may be variously changed, for example, the memory cell arrays MCA1 of the present embodiment. , MCA2) may be continuously and repeatedly arranged.

The first and second through wiring regions TB1 and TB2 may be regions including a wiring structure connected to the first region R1 through the second region R2 . The first through wiring regions TB1 may be disposed on both sides of the memory cell arrays MCA1 and MCA2 , for example, a contact plug electrically connected to the row decoder DEC of the first region R1 . It may include a wiring structure such as The second through wiring regions TB2 may be disposed at regular intervals in the memory cell arrays MCA1 and MCA2 , for example, electrically connected to the page buffers PB1 and PB2 of the first region R1 . It may include a wiring structure. Although the number of the first through wiring regions TB1 may be greater than that of the second through wiring regions TB2 , the shape, number, arrangement position, etc. of the first and second through wiring regions TB1 and TB2 , etc. may be variously changed in the embodiments.

4 is a schematic plan view of a semiconductor device according to example embodiments. In FIG. 4 , only the main configuration of the semiconductor device 100 is illustrated for better understanding.

5A and 5B are schematic cross-sectional views of semiconductor devices according to example embodiments. 5A and 5B show cross-sections taken along cutting lines I-I' and II-II' of FIG. 4, respectively.

4 to 5B , the semiconductor device 100 may include a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may be disposed on top of the peripheral circuit region PERI. Conversely, in example embodiments, the cell region CELL may be disposed below the peripheral circuit region PERI.

The memory cell region CELL includes a substrate 101 having a first region A and a second region B, gate electrodes 130 stacked on the substrate 101 , and gate electrodes 130 . The first and second separation regions MS1 and MS2 extending through the stacked structure GS, the upper separation regions SS penetrating a part of the stacked structure GS, and the stacked structure GS. It includes the disposed channels CH, and first and second through interconnection regions TB1 and TB2 that pass through the stack structure GS and the substrate 101 and are connected to the peripheral circuit region PERI. The memory cell region CELL includes interlayer insulating layers 120 alternately stacked with the gate electrodes 130 on the substrate 101 , a gate dielectric layer 145 , a channel region 140 in the channels CH; A channel pad 155 , a channel insulating layer 150 , a wiring line 175 , and a cell region insulating layer 190 may be further included.

The first region A of the substrate 101 is a region in which the gate electrodes 130 are vertically stacked and the channels CH are disposed. The memory cell array 20 of FIG. 1 and the memory cell arrays of FIG. 3 are It may be a region corresponding to (MCA1, MCA2), and the second region B is a region in which the gate electrodes 130 extend to have different lengths, and the memory cell array 20 and the peripheral circuit 30 of FIG. 1 . may correspond to an area for electrically connecting the The second area A may be disposed at at least one end of the first area A in at least one direction, for example, the x direction.

The substrate 101 may have an upper surface extending in the x-direction and the y-direction. The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound oxide semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer or as an epitaxial layer.

The gate electrodes 130 may be vertically spaced apart and stacked on the substrate 101 to form a stacked structure GS. The gate electrodes 130 include the lower gate electrode 130G forming the gate of the ground select transistor GST of FIG. 2 , the memory gate electrodes 130M forming the plurality of memory cells MC, and the string select transistor SST1 . , SST2 may include upper gate electrodes 130S forming the gate. The number of memory gate electrodes 130M forming the memory cells MC may be determined according to the capacity of the semiconductor device 100 . According to an embodiment, there may be one or more than one upper and lower gate electrodes 130S and 130G of the string select transistors SST1 and SST2 and the ground select transistor GST, respectively, and gates of the memory cells MC. The electrodes 130 may have the same or different structures as those of the electrodes 130 . Some of the gate electrodes 130 , for example, the memory gate electrodes 130M adjacent to the upper or lower gate electrodes 130S and 130G may be dummy gate electrodes.

The gate electrodes 130 may be stacked vertically spaced apart from each other on the first region A, and may extend from the first region A to the second region B at different lengths to form a step-shaped step difference. have. The gate electrodes 130 may have a step as shown in FIG. 5A along the x-direction, and may be disposed to form a step at the end in the y-direction as well. Due to the step, the lower gate electrode 130 may extend longer than the upper gate electrode 130 to provide the upper exposed contact regions CP. The gate electrodes 130 may be connected to separate contact plugs in the contact regions CP to be connected to upper wiring lines. Of the gate electrodes 130 , except for the upper and lower gate electrodes 130S and 130G, at least some of the memory gate electrodes 130M form a stack of a certain number, for example, four. A step may be formed between the laminates. The four memory gate electrodes 130M forming one stack may be disposed to have a step difference in the y-direction.

As illustrated in FIG. 4 , the gate electrodes 130 may be disposed to be separated from each other in the y direction by the first separation region MS1 extending in the x direction. The gate electrodes 130 between the pair of first isolation regions MS1 may form one memory block, but the scope of the memory block is not limited thereto. Some of the gate electrodes 130, for example, the memory gate electrodes 130M, may form one layer in one memory block.

The gate electrodes 130 may include a metal material, for example, tungsten (W). In some embodiments, the gate electrodes 130 may include polycrystalline silicon or a metal silicide material. In example embodiments, the gate electrodes 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN). or a combination thereof.

The interlayer insulating layers 120 may be disposed between the gate electrodes 130 . Like the gate electrodes 130 , the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the top surface of the substrate 101 and may be disposed to extend in the x direction. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

The first and second separation regions MS1 and MS2 may be disposed to extend in the x-direction through the gate electrodes 130 in the first region A and the second region B. The first and second separation regions MS1 and MS2 may be disposed parallel to each other. The first and second separation regions MS1 and MS2 may pass through the entire gate electrodes 130 stacked on the substrate 101 to be connected to the substrate 101 . In embodiments, the arrangement order and number of the first and second separation regions MS1 and MS2 are not limited to those illustrated in FIG. 4 .

The common source line CSL described with reference to FIG. 2 may be disposed in the first separation regions MS1 , and a dummy common source line may be disposed in the second separation regions MS2 . As shown in FIGS. 5A and 5B , in the first and second isolation regions MS1 and MS2 , the source insulating layer 107 and the source insulating layer 107 are insulated from the gate electrodes 130 . A conductive layer 110 may be disposed. The source conductive layer 110 may have a shape in which a width is decreased while facing the substrate 101 due to a high aspect ratio, but is not limited thereto, and may have a side surface perpendicular to the top surface of the substrate 101 . In example embodiments, an impurity region may be disposed on the substrate 101 in contact with the source conductive layer 110 . The source conductive layer 110 of the first isolation regions MS1 may correspond to the common source line CSL, and the source conductive layer 110 of the second isolation regions MS2 may correspond to the dummy common source line. can do. Accordingly, the source conductive layer 110 constituting the second isolation regions MS2 may be in a floating state that is not connected to devices driving the semiconductor device 100 or an electrical signal is not applied thereto.

The upper separation regions SS may extend in the x direction between the first separation regions MS1 and the second separation region MS2 . The upper separation regions SS may be disposed parallel to a portion of the second separation region MS2 . The upper isolation regions SS pass through a portion of the gate electrodes 130 including the upper gate electrodes 130S among the gate electrodes 130 , and include a portion of the second region B and a portion of the first region A. ) can be placed in The upper gate electrodes 130S separated by the upper isolation regions SS may form different string selection lines SSL (refer to FIG. 2 ). The upper isolation regions SS may include an insulating layer. The upper isolation regions SS may separate a total of three gate electrodes 130 including the upper gate electrodes 130S from each other in the y-direction. However, the number of gate electrodes 130 separated by the upper isolation regions SS may be variously changed in some embodiments. In example embodiments, the semiconductor device 100 may further include insulating layers separating the lower gate electrodes 130G among the gate electrodes 130 . For example, the insulating layer may be disposed to separate the lower gate electrodes 130G in a region between the second isolation regions MS2 spaced apart from each other on a straight line in the x-direction.

The channels CH may be disposed to be spaced apart from each other while forming rows and columns on the first region A. The channels CH may be disposed to form a grid pattern or may be disposed in a zigzag shape in one direction. The channels CH may have a columnar shape, and may have inclined sides that become narrower as they get closer to the substrate 101 according to an aspect ratio. In example embodiments, dummy channels may be further disposed at an end of the first area A adjacent to the second area B and in the second area B.

A channel region 140 may be disposed in the channels CH. In the channels CH, the channel region 140 may be formed in an annular shape surrounding the channel insulating layer 150 therein. It may have the same column shape. The channel region 140 may be connected to the epitaxial layer 105 at the bottom. The channel region 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material containing p-type or n-type impurities. The channels CH disposed on a straight line in the y-direction between the first or second isolation regions MS1 and MS2 and the upper isolation region SS are of the upper wiring structure connected to the channel pad 155 . Depending on the arrangement, they may be respectively connected to different bit lines BL0-BL2 (see FIG. 2 ).

In the channels CH, channel pads 155 may be disposed on the channel region 140 . The channel pads 155 may be disposed to cover the upper surface of the channel insulating layer 150 and be electrically connected to the channel region 140 . The channel pads 155 may include, for example, doped polycrystalline silicon.

The gate dielectric layer 145 may be disposed between the gate electrodes 130 and the channel region 140 . Although not specifically illustrated, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel region 140 . The tunneling layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof. have. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 145 may extend in a horizontal direction along the gate electrodes 130 .

The epitaxial layer 105 is disposed on the substrate 101 at the lower end of the channels CH, and may be disposed on a side surface of the at least one gate electrode 130 . The epitaxial layer 105 may be disposed in the recessed region of the substrate 101 . The height of the upper surface of the epitaxial layer 105 may be higher than the upper surface of the lowermost gate electrode 130 and lower than the lower surface of the upper gate electrode 130 , but is not limited thereto. In example embodiments, the epitaxial layer 105 may be omitted, and in this case, the channel region 140 may be directly connected to the substrate 101 or connected to another conductive layer on the substrate 101 .

The first and second through wiring regions TB1 and TB2 may be regions including a wiring structure for connecting the memory cell region CELL and the peripheral circuit region PERI to each other. The first and second through wiring regions TB1 and TB2 may include a through contact plug 170 and a through contact extending in the z direction through the stack structure GS of the gate electrodes 130 and the substrate 101 . An insulating region 160 surrounding the plug 170 may be included. The first through wiring area TB1 may be disposed in the second area B, and may be disposed one per memory block. The second through wiring area TB2 may be disposed in the first area A, and may be disposed one per plurality of memory blocks. However, the number, size, arrangement, and shape of the first and second through-wiring areas TB1 and TB2 illustrated in FIG. 4 may be variously changed in the embodiments.

The insulating region 160 may be a region in which the gate electrode 130 is not extended or disposed and made of an insulating material. The insulating region 160 may have a greater width at the upper portion of the substrate 101 than between the substrate 101 , and thus may have bent portions along the upper surface and side surfaces of the substrate 101 . The insulating region 160 includes a first insulating layer 161 disposed on the same level as the substrate 101 , second insulating layers 162 extending perpendicular to the upper surface of the substrate 101 , and second insulating layers ( It may include third insulating layers 163A and 163B disposed between the 162 , and fourth insulating layers 164 positioned at the same level as the interlayer insulating layers 120 .

The first insulating layer 161 may be disposed in a region from which a portion of the substrate 101 is removed and may be disposed to be surrounded by the substrate 101 . The first insulating layer 161 may have an upper surface substantially coplanar with the upper surface of the substrate 101 , and the lower surface may be coplanar with the lower surface of the substrate 101 or located at a level lower than the lower surface of the substrate 101 . .

The second insulating layers 162 may be disposed on the first insulating layer 161 and in a peripheral region of the first insulating layer 161 . The second insulating layers 162 may function as a support structure when the third insulating layers 163A and 163B are formed, and may have, for example, a pillar shape. Some of the second insulating layers 162 may pass through the first insulating layer 161 and may extend to a lower portion of the first insulating layer 161 , but the present invention is not limited thereto. It may be arranged to penetrate only a part of the upper part. Also, according to embodiments, the second insulating layers 162 may extend on a separate stop layer under the first insulating layer 161 or extend to the circuit wiring lines 280 . Another portion of the second insulating layers 162 may be disposed on the substrate 101 and may be disposed to recess a portion of the substrate 101 . Some of the second insulating layers 162 disposed at the outermost of the second insulating layers 162 disposed on the substrate 101 may pass through the gate electrodes 130 in the periphery of the insulating region 160 . can be placed. Since these second insulating layers 162 are disposed around the insulating region 160 , they may be referred to as a dummy insulating layer or a dummy structure.

The third insulating layers 163A and 163B are parallel to the upper surface of the substrate 101 from the vertical extensions 163A extending perpendicular to the upper surface of the substrate 101 and the side surfaces of the vertical extensions 163A, for example For example, it may have horizontal extensions 163B extending in the x-direction. The vertical extensions 163A may be disposed between the second insulating layers 162 . The vertical extensions 163A may have a line shape on a plane, but are not limited thereto, and may have a circular shape or a rectangular shape. Some of the vertical extensions 163A may pass through the first insulating layer 161 and may extend to a lower portion of the first insulating layer 161 , but is not limited thereto, and only a portion of the upper portion of the first insulating layer 161 . It may be arranged to penetrate. Also, in some embodiments, the vertical extension 163A penetrating the first insulating layer 161 may extend from the lower portion of the first insulating layer 161 onto a separate stop layer or the circuit wiring lines 280 . ) may be extended. Other portions of the vertical extensions 163A may be disposed on the substrate 101 and may be disposed to recess a portion of the substrate 101 . The horizontal extensions 163B may be positioned at the same height level as the gate electrodes 130 , and may have side surfaces contacting the gate electrodes 130 at the boundary of the insulating region 160 . However, when some of the gate dielectric layers 145 in the channels CH are disposed along the gate electrodes 130 and around the gate electrodes 130 , the horizontal extensions 163B are formed in the insulating region 160 . It may contact the gate dielectric layer 145 at the boundary. In embodiments, the sizes of the second insulating layers 162 and the vertical extensions 163A are not limited to those shown in the drawings and may be variously changed, and may be larger or smaller than the sizes of the channels CH. have.

The fourth insulating layers 164 may be disposed to fill spaces between the first to third insulating layers 161 , 162 , 163A, and 163B. The fourth insulating layers 164 are positioned at the same level as the interlayer insulating layers 120 , and the interlayer insulating layers 120 may extend. Accordingly, a region located in the insulating region 160 among the interlayer insulating layers 120 may be interpreted as forming the fourth insulating layers 164 .

The first to fourth insulating layers 161 , 162 , 163A, 163B, and 164 forming the insulating region 160 may be formed of an insulating material. For example, the first to fourth insulating layers 161 , 162 , 163A, 163B, and 164 may include silicon oxide or silicon oxynitride. For example, even when the first to fourth insulating layers 161, 162, 163A, 163B, and 164 are made of the same material, physical properties may be different depending on the formation process, composition, etc., whereby the boundary may be separated from each other. can The insulating region 160 generally has a first width corresponding to the width of the first insulating layer 161 in the substrate 101 , and is determined by the horizontal extensions 163B on the substrate 101 , and the first insulating region 160 . It may have a second width greater than the width.

The through contact plugs 170 penetrate the insulating region 160 and extend perpendicularly to the top surface of the substrate 101 , and electrically connect the circuit elements 220 of the memory cell region CELL and the peripheral circuit region PERI. can be connected to However, a wiring structure electrically connecting the circuit elements 220 of the memory cell region CELL and the peripheral circuit region PERI is not limited to the through contact plugs 170 , and for example, the second region An additional wiring structure may be further disposed outside (B), that is, in a region where the substrate 101 is not disposed. The through contact plugs 170 may be connected to the wiring lines 175 at an upper portion thereof, but may also be connected to a separate contact plug according to embodiments. The through contact plugs 170 may be connected to the circuit wiring lines 280 at the bottom.

The through contact plugs 170 may extend through the first insulating layer 161 of the insulating region 160 and pass through at least some of the second to fourth insulating layers 162 , 163A, 163B, and 164 . can For example, as shown in FIG. 5B , one through-contact plug 170 includes a second insulating layer 162 , third insulating layers 163A and 163B, and fourth insulating layers 164 . It may pass through a portion of the first insulating layer 161 at the lower portion. However, in the insulating region 160 , the arrangement of the through contact plugs 170 may be determined regardless of the positions of the vertical extension portions 163A of the second insulating layer 162 and the third insulating layers 163A and 163B. can The number, shape, and shape of the through contact plugs 170 that are disposed to pass through one insulating region 160 may be variously changed in some embodiments. In some embodiments, the through contact plugs 170 may have a form in which a plurality of layers are connected. Also, in some embodiments, in addition to the through contact plugs 170 , wiring structures in the form of wiring lines may be further disposed in the insulating region 160 . The through contact plugs 170 may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), or the like.

The wiring line 175 may constitute a wiring structure electrically connected to the memory cells in the memory cell region CELL. The wiring line 175 may be electrically connected to, for example, the gate electrodes 130 or the channels CH. The number of contact plugs and wiring lines constituting the wiring structure may be variously changed in some embodiments. The wiring line 175 may include metal, for example, tungsten (W), copper (Cu), aluminum (Al), or the like.

The cell region insulating layer 190 may be disposed to cover the substrate 101 , the gate electrodes 130 on the substrate 101 , and the peripheral region insulating layer 290 . The cell region insulating layer 190 may be made of an insulating material.

The peripheral circuit region PERI may include a base substrate 201 , circuit elements 220 disposed on the base substrate 201 , circuit contact plugs 270 , and circuit wiring lines 280 . .

The base substrate 201 may have an upper surface extending in the x-direction and the y-direction. In the base substrate 201 , separate device isolation layers may be formed to define an active region. Source/drain regions 205 including impurities may be disposed in a portion of the active region. The base substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound oxide semiconductor.

The circuit elements 220 may include horizontal transistors. Each of the circuit elements 220 may include a circuit gate dielectric layer 222 , a spacer layer 224 , and a circuit gate electrode 225 . Source/drain regions 205 may be disposed in the base substrate 201 at both sides of the circuit gate electrode 225 .

A peripheral region insulating layer 290 may be disposed on the circuit device 220 on the base substrate 201 . The circuit contact plugs 270 may pass through the peripheral region insulating layer 290 to be connected to the source/drain regions 205 . An electrical signal may be applied to the circuit device 220 by the circuit contact plugs 270 . In an area not shown, circuit contact plugs 270 may also be connected to the circuit gate electrode 225 . The circuit wiring lines 280 may be connected to the circuit contact plugs 270 and may be arranged in a plurality of layers.

6A and 6B are partially enlarged views of a semiconductor device according to example embodiments. 6A and 6B are enlarged views of a region corresponding to region 'C' of FIG. 5A .

Referring to FIG. 6A , first to fourth insulating layers 161 , 162 , 163A, 163B and 164 constituting the insulating region 160 are illustrated. Among the second insulating layers 162 and the third insulating layers 163A and 163B, the vertical extension portions 163A may partially penetrate the first insulating layer 161 and partially be disposed on the substrate 101 . can Horizontal extensions 163B of the third insulating layers 163A and 163B may extend from side surfaces of the vertical extensions 163A to contact the gate electrodes 130 . A fourth insulating layer 164 extending from the interlayer insulating layer 120 may be disposed on upper and lower surfaces of the horizontal extension parts 163B.

Referring to FIG. 6B , unlike the embodiment of FIG. 6A , the insulating region 160 may have a seam S in which the third insulating layers 163A and 163B are formed. For example, the shim S may be formed in the vertical extensions 163A, inside regions in which the horizontal extensions 163B are disposed. However, the shape and arrangement of the shim S may vary depending on the widths of the vertical extensions 163A and the horizontal extensions 163B. For example, in exemplary embodiments, the shim S may be located in the central region of the vertical extensions 163A and/or the central region of the horizontal extensions 163B.

7A to 7D are schematic layout diagrams of semiconductor devices according to example embodiments. 7A-7D show the layout of the main layers in the insulating region 160 .

Referring to FIG. 7A , the second insulating layers 162 may be arranged in columns and rows at regular intervals in the region including the region where the first insulating layer 161 is disposed. The second insulating layers 162 may have, for example, a circular shape on a plane. The second insulating layers 162 are spaced apart from the adjacent second insulating layer 162 in the x-direction in a region where the vertically extended portions 163A of the third insulating layers 163A and 163B are disposed. It may be arranged to have a distance. A portion of the second insulating layers 162 disposed outside the horizontal extension portion 163B of the third insulating layers 163A and 163B has a dummy pattern penetrating the gate electrodes 130 (refer to FIG. 5A ). can be

The vertical extension portion 163A of the third insulating layers 163A and 163B may have a line shape extending in one direction, for example, the y-direction. The vertical extension portions 163A may be disposed at predetermined intervals along the x-direction perpendicular to the extension direction within the boundary of the insulating region 160 , that is, within the boundary of the horizontal extension portion 163B.

Referring to FIG. 7B , the second insulating layers 162 may have, for example, an elliptical shape, an elongated shape, or a bar shape on a plane. The second insulating layers 162 are relative to the second insulating layer 162 adjacent in the x-direction and the y-direction in the region where the vertical extension portions 163A of the third insulating layers 163A and 163B are disposed. It can be arranged to have a large separation distance.

The vertical extension portion 163A of the third insulating layers 163A and 163B may have a rectangular outer surface and may have a shape including a plurality of lines. For example, the vertical extension portion 163A may include both a line pattern extending along the x-direction and a line pattern extending along the y-direction within the boundary of the insulating region 160 . In example embodiments, the line pattern extending along the x-direction and the line pattern extending along the y-direction are not necessarily arranged to be connected to each other as in the present embodiment, but may be spaced apart from each other.

Referring to FIG. 7C , the second insulating layers 162 may be arranged in columns and rows in a circular shape, as in FIG. 7A . The vertical extension 163A of the third insulating layers 163A and 163B may have a circular or elliptical shape. The vertical extension portions 163A may be disposed at predetermined intervals along the x-direction and the y-direction within the boundary of the insulating region 160 , that is, within the boundary of the horizontal extension portion 163B.

Referring to FIG. 7D , the second insulating layers 162 may be arranged in columns and rows in a circular shape as in FIG. 7A . The vertical extension 163A of the third insulating layers 163A and 163B may have a rectangular or elongated shape. For example, the vertical extension portion 163A may include both patterns extending along the x-direction and the patterns extending along the y-direction within the boundary of the insulating region 160 , and the patterns are spaced apart from each other. can be placed.

As such, in exemplary embodiments, the second insulating layers 162 and the third insulating layers 163A and 163B may have various shapes, and the second insulating layer in the embodiment of FIGS. 7A to 7D . It may also be possible for the shapes of the layers 162 and the third insulating layers 163A and 163B to be combined with each other.

8 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

Referring to FIG. 8 , in the semiconductor device 100a , the channel CH may have a U-shape unlike the embodiments of FIGS. 5A and 5B . The channel CH penetrates the stack structure GS of the gate electrodes 130 and may have a curved shape in the substrate 101 . The channel CH may include a channel region 140 , a gate dielectric layer 145 , a channel insulating layer 150 , and a channel pad 155 , the channel region 140 , the gate dielectric layer 145 , and the channel. The insulating layer 150 may also be disposed in a U-shape. An isolation insulating layer 195 may be further disposed between the bent regions of the channel CH.

Also, unlike the embodiment of FIG. 5A , in the semiconductor device 100a , the source conductive layer 110 is not disposed to extend to the substrate 101 , and in an area not shown, on one end of the channel CH can be placed.

9 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

Referring to FIG. 9 , unlike the embodiment of FIGS. 5A and 5B , the semiconductor device 100b may further include a wiring insulating layer 172 surrounding the outer surfaces of the through contact plugs 170 .

The wiring insulating layer 172 may be disposed between the through contact plugs 170 and the insulating region 160 . Accordingly, for example, even when a conductive region is partially disposed in the insulating region 160 or the insulating region 160 includes a conductive layer therein, the through contact plugs 170 are electrically connected to the peripheral region. can be separated. Also, as in the embodiment of FIG. 6B , even when a shim is formed in a portion of the insulating region 160 , the through contact plugs 170 may be electrically isolated from the peripheral region. The wiring insulating layer 172 may extend into the substrate 101 and may also extend into the peripheral region insulating layer 290 . The wiring insulating layer 172 may be made of an insulating material, for example, silicon oxide and/or silicon nitride.

10 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

Referring to FIG. 10 , in the semiconductor device 100c , the second insulating layer 162a forming the insulating region 160a may have the same structure as the channel CH. That is, unlike the embodiment of FIGS. 5A and 5B , the second insulating layer 162a is formed inside the gate dielectric layer 145 , the channel region 140 , the channel insulating layer 150 , and the channel pad 155 . Corresponding layers may be included. In particular, the second insulating layer 162a may include a conductive layer such as the channel region 140 and the channel pad 155 . The structure of the second insulating layer 162a may be obtained by forming the second insulating layer 162a together with the channel CH.

In this case, the through contact plug 170 may be disposed so as not to penetrate the second insulating layer 162a as shown. Alternatively, as in the embodiment described above with reference to FIG. 9 , by further disposing the wiring insulating layer 172 surrounding the sidewall of the through contact plug 170 , the through contact plug 170 is formed with the second insulating layer 162a. ) and can be arranged to be electrically separated from each other.

11A to 11J are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments. 11A to 11J , regions corresponding to the region shown in FIG. 5A are shown.

Referring to FIG. 11A , a peripheral circuit region PERI including circuit elements 220 and lower wiring structures is formed on a base substrate 201 , and a memory cell region is provided on the peripheral circuit region PERI The substrate 101 and the first insulating layer 161 may be formed.

First, a circuit gate dielectric layer 222 and a circuit gate electrode layer 225 may be sequentially formed on the base substrate 201 . The circuit gate dielectric layer 222 and the circuit gate electrode layer 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode layer 225 may be formed of at least one of polycrystalline silicon or a metal silicide layer, but is not limited thereto. Next, a spacer layer 224 and source/drain regions 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode layer 225 . In some embodiments, the spacer layer 224 may be formed of a plurality of layers. Next, an ion implantation process may be performed to form the source/drain regions 205 .

Among the lower wiring structures, the circuit contact plugs 270 may be formed by partially forming the peripheral region insulating layer 290 , then removing the portion by etching and then filling the conductive material. The lower wiring lines 280 may be formed by, for example, depositing a conductive material and then patterning it.

The peripheral region insulating layer 290 may include a plurality of insulating layers. A portion of the peripheral region insulating layer 290 is formed in each step of forming the lower wiring structures, and a portion is formed on the uppermost lower wiring line 280 , so that the circuit elements 220 and the lower portion are finally formed. It may be formed to cover the wiring structures.

Next, the substrate 101 may be formed on the peripheral region insulating layer 290 . The substrate 101 may be made of, for example, polycrystalline silicon, and may be formed by a CVD process. Polycrystalline silicon constituting the substrate 101 may contain impurities. The substrate 101 may be formed smaller than the base substrate 201 , but is not limited thereto.

The first insulating layer 161 may be formed by removing a portion of the substrate 101 in the regions corresponding to the first and second through wiring regions TB1 and TB2 and then filling the insulating material with the insulating material. After the insulating material is buried, a planarization process may be further performed using a chemical mechanical polishing (CMP) process. Accordingly, the upper surface of the first insulating layer 161 may be substantially coplanar with the upper surface of the substrate 101 .

Referring to FIG. 11B , sacrificial layers 180 and interlayer insulating layers 120 are alternately stacked on a substrate 101 , and the sacrificial layers 180 extend to different lengths in the x-direction. Some of the layers 180 and the interlayer insulating layers 120 may be removed.

The sacrificial layers 180 may be replaced by the gate electrodes 130 (refer to FIG. 5A ) through a subsequent process. The sacrificial layers 180 may be made of a material different from that of the interlayer insulating layers 120 , and may be formed of a material that can be etched with etching selectivity for the interlayer insulating layers 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be made of at least one of silicon oxide and silicon nitride, and the sacrificial layers 180 may include an interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. and other materials. In embodiments, the thicknesses of the interlayer insulating layers 120 may not all be the same. For example, the lowermost interlayer insulating layer 120 may be formed to be relatively thin, and the uppermost interlayer insulating layer 120 may be formed to be relatively thick. The thickness of the interlayer insulating layers 120 and the sacrificial layers 180 and the number of layers constituting the interlayer insulating layers 120 and the sacrificial layers 180 may be variously changed from the illustrated ones.

In the second region B of FIG. 4 , a photolithography process for the sacrificial layers 180 using a mask layer so that the upper sacrificial layers 180 extend shorter than the lower sacrificial layers 180; The etching process may be repeated. Accordingly, the sacrificial layers 180 may form a step shape, and a contact region CP may be provided. The sacrificial layers 180 may include an upper stacked body ST1 , an intermediate stacked body ST2 , and a lower stacked body ST3 . The upper stacked body ST1 may include a dummy stack at a boundary with the intermediate stacked body ST2 , and the number of sacrificial layers 180 constituting the intermediate stacked body ST2 is determined by the number of gate electrodes 130 to be formed. can be increased or decreased according to the number of The upper stacked body ST1 and the lower stacked body ST3 may be lowered by a first step in the x direction, and the intermediate stacked body ST2 may be lowered by a second step greater than the first step. In embodiments, the number of sacrificial layers 180 forming the stacked bodies ST1 , ST2 , and ST3 , the size of the step, etc. may be variously changed.

Next, the first cell region insulating layer 192 covering the upper portion of the stack structure of the sacrificial layers 180 and the interlayer insulating layers 120 may be formed.

Referring to FIG. 11C , second insulating layers 162 penetrating through the stacked structure of the sacrificial layers 180 and the interlayer insulating layers 120 may be formed.

The second insulating layers 162 may be formed at regular intervals in the region including the first insulating layer 161 . The second insulating layers 162 are formed by removing portions of the first cell region insulating layer 192 , the sacrificial layers 180 , and the interlayer insulating layers 120 to form an opening, and then forming the opening with an insulating material. It can be formed by embedding with The second insulating layers 162 may be made of a material different from that of the sacrificial layers 180 .

Some of the second insulating layers 162 may penetrate the first insulating layer 161 and extend into the peripheral region insulating layer 290 . In this case, the depth to which the second insulating layers 162 extend may be controlled by using a separate etch stop layer disposed in the peripheral region insulating layer 290 . Alternatively, the second insulating layers 162 may be formed to extend to the circuit wiring line 280 by using the circuit wiring line 280 as an etch stop layer. Some of the second insulating layers 162 may be disposed to recess the upper portion of the substrate 101 around the first insulating layer 161 . Some of the second insulating layers 162 disposed at the outermost of the second insulating layers 162 may be a dummy structure for patterning other second insulating layers 162 . The second insulating layers 162 may have inclined sides according to the height of the stacked structure of the sacrificial layers 180 and the interlayer insulating layers 120 .

Referring to FIG. 11D , first openings OP1 passing through the stacked structure of the sacrificial layers 180 and the interlayer insulating layers 120 may be formed.

The first openings OP1 are formed in a region corresponding to the vertical extensions 163A of the third insulating layers 163A and 163B of FIG. 5A , and include the first cell region insulating layer 192 and the sacrificial layers 180 . , and may be formed by removing the interlayer insulating layers 120 . The first openings OP1 may be formed at regular intervals between the second insulating layers 162 . Some of the first openings OP1 may penetrate the first insulating layer 161 and extend into the peripheral region insulating layer 290 . Some of the first openings OP1 may be formed to recess the upper portion of the substrate 101 around the first insulating layer 161 . The first openings OP1 may have sides inclined according to the height of the stacked structure of the sacrificial layers 180 and the interlayer insulating layers 120 .

Referring to FIG. 11E , some of the sacrificial layers 180 exposed through the first openings OP1 may be removed.

A portion of the sacrificial layers 180 may be removed using, for example, a wet etching process. During the wet etching process, an etchant may flow through the first openings OP1 to remove the sacrificial layers 180 adjacent to the first openings OP1 . The sacrificial layers 180 are selectively removed with respect to the interlayer insulating layers 120 and the first and second insulating layers 161 and 162 , and the interlayer insulating layers 120 and the first and second insulating layers are removed. The fields 161 and 162 may remain without being removed. Accordingly, first tunnel portions LT1 extending horizontally between the interlayer insulating layers 120 from the first openings OP1 may be formed. The first tunnel parts LT1 may extend to substantially the same length from side surfaces of the first openings OP1 , and lengths of the first tunnel parts LT1 may be variously changed in some embodiments.

In this step, in the region where the sacrificial layers 180 are removed, the stacked structure of the interlayer insulating layer 120 may have poor stability, but the stacked structure is more stably supported by the second insulating layers 162 . can be

Referring to FIG. 11F , an insulating material may be deposited in the first openings OP1 and the first tunnel parts LT1 to form third insulating layers 163A and 163B.

The insulating material may be deposited to fill the first tunnel parts LT1 and fill the first openings OP1 . The insulating material may be deposited using, for example, an ALD process. Accordingly, horizontal extensions 163B of the third insulating layers 163A and 163B are formed in the region where the first tunnel parts LT1 are buried, and vertical extension parts are formed in the region where the first openings OP1 are buried. 163A may be formed. The horizontal extensions 163B may be connected to each other between the second insulating layers 162 , and outer surfaces of the second insulating layers 162 may be in contact with the sacrificial layers 180 in an edge region.

By forming the third insulating layers 163A and 163B, the insulating region 160 including the first to third insulating layers 161 , 162 , 163A and 163B and the fourth insulating layers 164 is finally formed. can be formed with The fourth insulating layers 164 may include regions disposed between the first to third insulating layers 161 , 162 , 163A and 163B of the interlayer insulating layers 120 . In the present embodiment, the insulating region 160 may be made of only an insulating material, and the second insulating layers 162 and vertical extensions 163A, which are vertical insulating layers extending perpendicular to the upper surface of the substrate 101 , and Horizontally extending horizontal insulating layers may be formed of horizontal extensions 163B and fourth insulating layers 164 .

The first to fourth insulating layers 161 , 162 , 163A, 163B, and 164 constituting the insulating region 160 may have different compositions or may have the same or similar composition. Even when the first to fourth insulating layers 161 , 162 , 163A, 163B, and 164 have substantially the same composition, since they are formed in different process steps, the boundary may be distinguished due to different physical properties. Alternatively, even when the first to fourth insulating layers 161 , 162 , 163A, 163B, and 164 are formed using different deposition methods, their physical properties may be different, and thus their boundaries may be distinguished.

Referring to FIG. 11G , channels CH passing through the stacked structure of the sacrificial layers 180 and the interlayer insulating layers 120 may be formed.

First, a string separation region SS (refer to FIG. 4 ) may be formed by removing a portion of the sacrificial layers 180 and the interlayer insulating layers 120 in an area not shown. The string isolation region SS uses a separate mask layer to expose a region where the string isolation region SS is to be formed, and a predetermined number of sacrificial layers 180 and interlayer insulating layers 120 are removed from the top. After removal, it can be formed by depositing an insulating material. The string separation region SS may extend below a region in which the upper gate electrodes 130S of FIG. 4 are formed.

The channels CH may be formed by anisotropically etching the sacrificial layers 180 and the interlayer insulating layers 120 , and may be formed in a hole shape. Due to the height of the stacked structure, sidewalls of the channels CH may not be perpendicular to the top surface of the substrate 101 . In example embodiments, the channels CH may be formed to recess a portion of the substrate 101 . Next, the epitaxial layer 105 , at least a portion of the gate dielectric layer 145 , the channel region 140 , the channel insulating layer 150 , and the channel pads 155 are sequentially formed in the channels CH. can When there are dummy channels additionally disposed in addition to the channels CH, the dummy channels may also be formed together with the channels CH in this step. In some embodiments, some of the dummy channels may be disposed to pass through the insulating region 160 .

The epitaxial layer 105 may be formed using a selective epitaxial growth (SEG) process. The epitaxial layer 105 may be formed of a single layer or a plurality of layers. The epitaxial layer 105 may include polycrystalline silicon, single crystal silicon, polycrystalline germanium, or single crystal germanium doped or undoped with impurities.

The gate dielectric layer 145 may be formed to have a uniform thickness using an ALD or CVD process. In this step, all or part of the gate dielectric layer 145 may be formed, and a portion extending perpendicular to the substrate 101 along the channels CH may be formed in this step. The channel region 140 may be formed on the gate dielectric layer 145 in the channels CH. The channel insulating layer 150 is formed to fill the channels CH, and may be an insulating material. However, in some embodiments, the channel region 140 may be filled with a conductive material other than the channel insulating layer 150 . The channel pad 155 may be made of a conductive material, for example, polycrystalline silicon.

In example embodiments, the channels CH may be formed before the formation of the second insulating layers 162 and the third insulating layers 163A and 163B described above with reference to FIGS. 11C to 11F . . In addition, the relative heights of the channels CH and the insulating region 160 may be variously changed in some embodiments. For example, in example embodiments, upper surfaces of the channels CH may be positioned higher or lower than upper surfaces of the second insulating layers 162 and the third insulating layers 163A and 163B.

In the case of the semiconductor device 100c of FIG. 10 , second insulating layers 162a may be formed together with the channels CH in this step. Next, the insulating region 160 may be formed by performing the same process as described above with reference to FIGS. 11D to 11F . However, when a part of the gate dielectric layer 145 is removed together with the sacrificial layers 180 depending on the material of the gate dielectric layer 145 , irregularities may be formed on the sidewalls of the second insulating layers 162a .

Referring to FIG. 11H , second openings OP2 passing through the stacked structure of the sacrificial layers 180 and the interlayer insulating layers 120 are formed, and the sacrificial layers OP2 are formed through the second openings OP2. 180 , the second tunnel parts LT2 may be formed.

First, before forming the second openings OP2 , a second cell region insulating layer 194 may be further formed on the channels CH. The second openings OP2 may be formed at positions of the first and second separation regions MS1 and MS2 of FIG. 4 . The second openings OP2 may be formed by forming a mask layer using a photolithography process and anisotropically etching the stack structure. The second openings OP2 may be formed in a trench shape extending in the y-direction, and the substrate 101 may be exposed under the second openings OP2 .

The sacrificial layers 180 may be selectively removed with respect to the interlayer insulating layers 120 and the insulating region 160 using, for example, wet etching. Accordingly, a plurality of second tunnel portions LT2 may be formed between the interlayer insulating layers 120 , and some sidewalls of the gate dielectric layer 145 of the channels CH may be formed through the second tunnel portions LT2 . and horizontal extensions 163B of the third insulating layers 163A and 163B may be exposed.

Referring to FIG. 11I , the gate electrodes 130 are formed by filling the second tunnel portions LT2 from which the sacrificial layers 180 are removed with a conductive material, and the source insulating layer ( ) is formed in the second openings OP2 . 107) and the source conductive layer 110 may be formed.

The conductive material may be buried in the second tunnel parts LT2 . The conductive material may include a metal, polycrystalline silicon, or a metal silicide material. After the gate electrodes 130 are formed, the conductive material deposited in the second openings OP2 may be removed through an additional process.

The source insulating layer 107 may be formed in the form of a spacer in the second openings OP2 . That is, after depositing the insulating material, the insulating material formed on the substrate 101 under the second openings OP2 may be removed to form the source insulating layer 107 .

Next, the source conductive layer 110 may be formed by depositing a conductive material on the source insulating layer 107 . The source insulating layer 107 and the source conductive layer 110 may be formed by the same process in the first and second isolation regions MS1 and MS2 to have the same structure. However, as described above, for example, in the first isolation regions MS1 , the source conductive layer 110 functions as a common source line CSL, and in the second isolation regions MS2 , the source conductive layer 110 . 110) may function as a dummy common source line.

Referring to FIG. 11J , third openings OP3 for forming through contact plugs 170 may be formed.

First, by forming a third cell region insulating layer 196 covering the source insulating layer 107 , the cell region insulating layer 190 including the first to third cell region insulating layers 192 , 194 , and 196 . can form.

Next, from the top of the insulating region 160 , the cell region insulating layer 190 and third openings OP3 passing through the insulating region 160 may be formed. The circuit wiring line 280 of the peripheral circuit area PERI may be exposed at lower ends of the third openings OP3 .

Next, referring to FIG. 5A , the through contact plugs 170 are formed by filling the third openings OP3 with a conductive material, and the wiring line 175 connected to the upper ends of the through contact plugs 170 . ) to form the semiconductor device 100 may be manufactured. However, the manufacturing method described above with reference to FIGS. 11A to 11J is an example for manufacturing the semiconductor device 100 of FIG. 5A , and the semiconductor device 100 may be manufactured by various manufacturing methods.

In the case of the semiconductor device 100b of FIG. 9 , in this step, the wiring insulating layer 172 may be first formed in the third openings OP3 . Next, after removing the wiring insulating layer 172 to expose the circuit wiring line 280 at the lower end of the third openings OP3 , the through contact plugs 170 may be formed.

12A to 12G are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device according to example embodiments. 12A to 12G, regions corresponding to the region shown in FIG. 8 are shown. Hereinafter, a description overlapping with the description with reference to FIGS. 11A to 11J will be omitted.

Referring to FIG. 12A , the peripheral circuit region PERI is first formed on the base substrate 201 , and the substrate 101 and the first insulating layer 161 on which the memory cell region is provided on the peripheral circuit region PERI ) can be formed. Next, the stacked structure GS including the gate electrodes 130 may be formed on the substrate 101 .

The peripheral circuit region PERI and the first insulating layer 161 may be formed similarly to those described above with reference to FIG. 11A .

Next, the stacked structure GS is formed by alternately stacking the gate electrodes 130 and the interlayer insulating layers 120 , and the gate electrodes 130 are extended to have different lengths in the x-direction. Part of 130 and the interlayer insulating layers 120 may be removed. Accordingly, the gate electrodes 130 may form a step shape, and a contact region CP may be provided. The gate electrodes 130 may be configured to include an upper stacked body ST1 , an intermediate stacked body ST2 , and a lower stacked body ST3 , but is not limited thereto. Next, a first cell region insulating layer 192 covering an upper portion of the stack structure GS may be formed.

Referring to FIG. 12B , second insulating layers 162 penetrating through the stacked structure GS of the gate electrodes 130 and the interlayer insulating layers 120 may be formed.

The second insulating layers 162 may be formed at regular intervals in the region including the first insulating layer 161 . In the second insulating layers 162 , openings are formed by removing portions of the first cell region insulating layer 192 , the gate electrodes 130 , and the interlayer insulating layers 120 , and then the openings are formed of an insulating material. The second insulating layers 162 may be formed of a material different from that of the gate electrodes 130 .

Referring to FIG. 12C , first openings OP1 passing through the stack structure GS of the gate electrodes 130 and the interlayer insulating layers 120 may be formed.

The first openings OP1 are formed in a region corresponding to the vertical extension portions 163A of the third insulating layers 163A and 163B of FIG. 8 , the first cell region insulating layer 192 and the gate electrodes 130 . , and may be formed by removing the interlayer insulating layers 120 . The first openings OP1 may be formed at regular intervals between the second insulating layers 162 .

Referring to FIG. 12D , the gate electrodes 130 exposed through the first openings OP1 may be partially removed.

The gate electrodes 130 may be partially removed using, for example, a wet etching process. During the wet etching process, an etchant may flow through the first openings OP1 to remove the gate electrodes 130 adjacent to the first openings OP1 . The gate electrodes 130 are selectively removed with respect to the interlayer insulating layers 120 and the first and second insulating layers 161 and 162 , and the interlayer insulating layers 120 and the first and second insulating layers are removed. The fields 161 and 162 may remain without being removed. Accordingly, first tunnel portions LT1 extending horizontally between the interlayer insulating layers 120 from the first openings OP1 may be formed.

Referring to FIG. 12E , an insulating material may be deposited in the first openings OP1 and the first tunnel parts LT1 to form third insulating layers 163A and 163B.

The insulating material may be deposited to fill the first tunnel parts LT1 and fill the first openings OP1 . The insulating material may be deposited using, for example, an ALD process. Accordingly, horizontal extensions 163B of the third insulating layers 163A and 163B are formed in the region where the first tunnel parts LT1 are buried, and vertical extension parts are formed in the region where the first openings OP1 are buried. 163A may be formed. The horizontal extensions 163B may be connected to each other between the second insulating layers 162 , and outer surfaces of the second insulating layers 162 may be in direct contact with the gate electrodes 130 in the edge region.

By forming the third insulating layers 163A and 163B, the insulating region 160 including the first to third insulating layers 161 , 162 , 163A and 163B and the fourth insulating layers 164 is finally formed. can be formed with The insulating region 160 may be made of only an insulating material, and may be a region in which the gate electrodes 130 are not disposed.

Referring to FIG. 12F , a channel CH passing through the stack structure GS of the gate electrodes 130 and the interlayer insulating layers 120 may be formed.

The channel CH may be formed by anisotropically etching the stacked structure GS, may be formed in a hole shape, and may be formed in a U shape penetrating through the substrate 101 . To this end, a separate sacrificial layer may be previously formed on the substrate 101 . Next, an epitaxial layer 105 , a gate dielectric layer 145 , a channel region 140 , a channel insulating layer 150 , and channel pads 155 may be formed in the channels CH. An isolation insulating layer 195 may be formed between the channels CH.

In example embodiments, the channel CH and the isolation insulating layer 195 may be formed first before the insulating region 160 is formed. For example, the channel CH may be formed first in the step described above with reference to FIG. 12A .

Referring to FIG. 12G , second openings OP2 for forming through contact plugs 170 may be formed.

First, the second cell region insulating layer 194 covering the source insulating layer 107 is formed to form the cell region insulating layer 190 including the first and second cell region insulating layers 192 and 194 . can do. Next, second openings OP2 passing through the cell region insulating layer 190 and the insulating region 160 may be formed from an upper portion of the insulating region 160 . The circuit wiring line 280 of the peripheral circuit area PERI may be exposed at lower ends of the third openings OP2 .

Next, referring to FIG. 8 , through-contact plugs 170 penetrating the cell region insulating layer 190 and the insulating region 160 are formed, and wiring connected to upper ends of the through contact plugs 170 . The semiconductor device 100a may be manufactured by forming the line 175 . However, the manufacturing method described above with reference to FIGS. 12A to 12G is an example for manufacturing the semiconductor device 100a of FIG. 8 , and the semiconductor device 100a may be manufactured by various manufacturing methods.

13 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

Referring to FIG. 13 , the semiconductor device 200 may include a memory cell region CELL and a peripheral circuit region PERI. In particular, in the semiconductor device 200 , the peripheral circuit region PERI may be disposed on at least one side of the memory cell region CELL. For the memory cell region CELL, the description of the first region A described above with reference to FIGS. 4 to 5B may be equally applied.

The peripheral circuit region PERI includes circuit elements 220 disposed on the same substrate 101 as the memory cell region CELL, source/drain regions 205 disposed in the substrate 101 , and circuit elements. The peripheral region insulating layer 290 disposed on the 220 , the etch stop layer 295 in the peripheral region insulating layer 290 at a predetermined height, and gate electrodes bent and extended onto the peripheral region insulating layer 290 ( The stacked structure GS of 130 may include a through wiring region TB that is electrically connected to the circuit elements 220 through the stacked structure GS. However, in example embodiments, the peripheral circuit region PERI includes the stacked structure GS of the gate electrodes 130 in addition to the region in which the stacked structure GS of the gate electrodes 130 is disposed as illustrated. This unplaced area may also be included.

For the source/drain regions 205 and the circuit elements 220 , the description described above with reference to FIGS. 4 to 5B may be equally applied. The peripheral region insulating layer 290 may be formed to have a relatively low height, and the gate electrodes 130 and the interlayer insulating layers 120 move from the memory cell region CELL to the upper portion of the peripheral region insulating layer 290 . It can be bent and extended.

The through wiring region TB may be a region including a wiring structure for connecting the source/drain regions 205 and the circuit devices 220 to the wiring line 175 thereon. The through wiring region TB includes a through contact plug 170a extending in the z direction through the stack structure GS of the gate electrodes 130 and an insulating region 160b surrounding the through contact plug 170a. can do.

The insulating region 160b may be a region in which the gate electrode 130 is not extended or disposed and made of an insulating material. The insulating region 160b includes second insulating layers 162 extending perpendicularly to the upper surface of the substrate 101 , third insulating layers 163A and 163B disposed between the second insulating layers 162 , and fourth insulating layers 164 positioned at the same level as the interlayer insulating layers 120 . That is, since the insulating region 160b does not penetrate the substrate 101 , the first insulating layer 161 may not be included, unlike the insulating region 160 described above with reference to FIGS. 4 to 5B . Vertical extensions 163A of the second insulating layers 162 and the third insulating layers 163A and 163B may extend to the top surface of the etch stop layer 295 . However, the etch stop layer 295 may be omitted or disposed on the upper surface of the peripheral region insulating layer 290 according to embodiments. Otherwise, the description of the insulating region 160 described above with reference to FIGS. 4 to 5B may be applied in the same manner.

The through contact plugs 170a may penetrate the insulating region 160b and extend perpendicularly to the upper surface of the substrate 101 . The through contact plugs 170a may connect the source/drain regions 205 and the circuit elements 220 of the peripheral circuit region PERI to an upper wiring structure such as the wiring line 175 , and the peripheral circuit region. (PERI) may be electrically connected to the memory cell region CELL through the wiring structure.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitution, modification and change will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and it is also said that it falls within the scope of the present invention. something to do.

101: substrate 105: epitaxial layer
107: source insulating layer 110: source conductive layer
120: interlayer insulating layer 130: gate electrode
140: channel region 145: gate dielectric layer
150: channel insulating layer 155: channel pad
160: insulating region 161: first insulating layer
162: second insulating layer 163A, 163B: third insulating layer
164: fourth insulating layer 170: contact plug
172: wiring insulating layer 175: wiring line
180: sacrificial layer 190: cell region insulating layer
201: base substrate 205: source/drain region
220: circuit element 222: circuit gate dielectric layer
224: spacer layer 225: circuit gate electrode layer
270: circuit contact plug 280: circuit wiring line
290: peripheral region insulating layer

Claims (10)

a peripheral circuit region provided on the first substrate and including circuit elements;
a memory cell region provided on a second substrate disposed on the first substrate and including memory cells; and
a through wiring region extending in a first direction through the memory cell region and the second substrate and including a through contact plug electrically connecting the memory cell region and the circuit elements, and an insulating region surrounding the through contact plug including,
The insulating area is
a first insulating layer penetrating the second substrate and disposed in parallel with the second substrate;
second insulating layers arranged to extend in the first direction; and
It is disposed between the second insulating layers and extends in a second direction parallel to the upper surface of the second substrate from a side surface of the vertical extension part so as to be in contact with the vertical extension part extending in the first direction and the second insulating layers. A semiconductor device comprising a third insulating layer having horizontal extensions.
The method of claim 1,
A part of the second insulating layers penetrates at least a part of the first insulating layer, and a part of the second insulating layer is disposed on the second substrate around the first insulating layer.
3. The method of claim 2,
The second substrate has a recess on its upper surface by some of the second insulating layers.
The method of claim 1,
The vertical extension portions of the third insulating layer are disposed at regular intervals and are disposed between the second insulating layers.
The method of claim 1,
The memory cell region is
gate electrodes vertically spaced apart from each other and stacked on the second substrate;
interlayer insulating layers alternately disposed with the gate electrodes; and
channels passing through the gate electrodes and extending vertically on the second substrate;
The horizontal extension portions of the third insulating layer are positioned at the same height level as the gate electrodes.
6. The method of claim 5,
The insulating region further includes a fourth insulating layer filling between the first to third insulating layers,
The fourth insulating layer is a semiconductor device in which the interlayer insulating layer extends.
a peripheral circuit region provided on the first substrate and including circuit elements;
It is provided on a second substrate disposed on the first substrate, and is vertically spaced apart from each other and stacked on the second substrate, and the gate electrodes pass through the gate electrodes and extend vertically on the second substrate. a memory cell region including channels; and
and an insulating region penetrating the gate electrodes and the second substrate, and a through-wiring region including a through contact plug penetrating the insulating region and extending vertically;
The insulating region is a semiconductor having vertical extension portions extending in a first direction perpendicular to the first and second substrates and horizontal extension portions extending in a second direction perpendicular to the first direction from side surfaces of the vertical extension portions. Device.
8. The method of claim 7,
The horizontal extension portions are in contact with side surfaces of the gate electrodes.
a first region including first elements;
a second region provided on one side of the first region and including second elements; and
a through-wiring region disposed on the second region and including a through-wiring structure electrically connecting the first elements and the second elements and an insulating region surrounding the through-wiring structure;
The insulating region may include vertical insulating layers extending in a first direction and horizontal insulating layers extending in a second direction perpendicular to the first direction between the vertical insulating layers.
10. The method of claim 9,
The insulating region is disposed to be surrounded by gate electrodes constituting the first elements.

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