KR100418923B1 - method for fabricating semiconductor device - Google Patents
method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR100418923B1 KR100418923B1 KR10-2001-0037122A KR20010037122A KR100418923B1 KR 100418923 B1 KR100418923 B1 KR 100418923B1 KR 20010037122 A KR20010037122 A KR 20010037122A KR 100418923 B1 KR100418923 B1 KR 100418923B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- forming
- pattern
- substrate
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Abstract
게이트산화막이 손실되지 않으며 메탈 잔여물에 의한 브리지 문제를 발생시키지 않는 반도체소자의 제조방법을 제공하기 위한 것으로, 이와 같은 목적을 달성하기 위한 본 발명 반도체소자의 제조방법은 마스크패턴을 이용하여 상기 마스크패턴 양측의 기판내에 불순물영역을 형성하는 단계, 상기 불순물영역이 형성되지 않은 상기 기판상에 제1절연막 패턴을 형성하는 단계, 상기 제1절연막패턴 양측의 상기 불순물영역상에 살리사이드층을 형성하는 단계, 상기 제1절연막 패턴과 상기 살리사이드층을 포함한 전면에 제2절연막을 형성하는 단계, 상기 기판이 드러나도록 상기 제1절연막 패턴상부의 상기 제2절연막과 상기 제1절연막을 차례대로 제거하는 단계, 상기 드러난 기판표면에 게이트절연막을 형성하는 단계, 상기 게이트절연막상에 메탈게이트를 형성하는 단계, 상기 제2절연막을 제거하는 단계를 포함함을 특징으로 한다.The present invention provides a method for manufacturing a semiconductor device in which a gate oxide film is not lost and does not cause a bridge problem due to metal residues. The present invention provides a method of manufacturing a semiconductor device using a mask pattern to provide a mask pattern. Forming an impurity region in the substrate on both sides of the pattern, forming a first insulating film pattern on the substrate on which the impurity region is not formed, and forming a salicide layer on the impurity regions on both sides of the first insulating film pattern Forming a second insulating film on the entire surface including the first insulating film pattern and the salicide layer, and sequentially removing the second insulating film and the first insulating film on the first insulating film pattern so that the substrate is exposed. Forming a gate insulating film on the exposed surface of the substrate; Forming, it characterized in that it comprises the step of removing said second insulating film.
Description
본 발명은 반도체소자에 대한 것으로, 특히 메탈 게이트를 형성하기 위한 반도체소자의 제조방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for forming a metal gate.
첨부 도면을 참조하여 종래 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a conventional semiconductor device is as follows.
도 1a 내지 도 1g는 종래 기술에 따른 반도체소자의 제조방법을 나타낸 공정단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
종래 기술에 따른 반도체소자의 제조방법은 도 1a에서와 같이 실리콘기판(1)의 격리영역에 트랜치를 형성하고, 트랜치내에만 매립되도록 격리절연막(2)을 형성한다.In the method of manufacturing a semiconductor device according to the related art, as shown in FIG. 1A, a trench is formed in an isolation region of the silicon substrate 1, and an isolation insulation layer 2 is formed so as to be embedded only in the trench.
이후에 실리콘기판(1)의 일영역에 웰 이온 주입공정을 진행하여서 제1도전형웰(3)을 형성한다. 이때 제1도전형웰(3)은 피모스 트랜지스터를 형성할 때는 N형의 웰을 형성하고, 앤모스 트랜지스터를 형성할 때는 P형의 웰을 형성한다.Thereafter, a well ion implantation process is performed in one region of the silicon substrate 1 to form the first conductive well 3. At this time, the first conductive well 3 forms an N type well when forming a PMOS transistor, and a P type well when forming an NMOS transistor.
다음에 도 1b에서와 같이 제1불순물영역(3)의 일영역에 게이트산화막(4)과 폴리실리콘패턴(5)을 적층 형성한다.Next, as shown in FIG. 1B, the gate oxide film 4 and the polysilicon pattern 5 are stacked in one region of the first impurity region 3.
그리고 도 1c에서와 같이 폴리실리콘패턴(5)양측의 제1도전형웰(3)내에 저농도 불순물영역(6)(P-)을 형성하고, 도 1d와 같이 폴리실리콘패턴(5)양측에 측벽스페이서(7)를 형성한후에 그 양측의 제1도전형웰(3)내에 고농도 불순물영역(8)(P+)을 형성한다.1C, low concentration impurity regions 6 (P−) are formed in the first conductive wells 3 on both sides of the polysilicon pattern 5, and sidewall spacers are formed on both sides of the polysilicon pattern 5 as shown in FIG. 1D. After (7) is formed, high concentration impurity regions 8 (P +) are formed in the first conductive wells 3 on both sides thereof.
이후에 도1e에서와 같이 고농도 불순물영역(8)과 폴리실리콘패턴(5) 상에 살리사이드층(9)을 형성하고, 도 1f에서와 같이 게이트산화막(4)이 드러나도록 폴리실리콘패턴(5) 및 그 상부의 살리사이드층(9)을 제거한다.Afterwards, the salicide layer 9 is formed on the high concentration impurity region 8 and the polysilicon pattern 5 as shown in FIG. 1E, and the polysilicon pattern 5 is exposed to expose the gate oxide film 4 as shown in FIG. 1F. ) And the salicide layer 9 thereon.
상기에서 폴리실리콘패턴(5)을 제거할 때 과도식각되어 게이트산화막(4)이 손상될 우려가 있다.When the polysilicon pattern 5 is removed, the gate oxide layer 4 may be damaged by excessive etching.
다음에 도 1g에서와 같이 전면에 메탈층을 증착한 후에 게이트산화막(4)상에만 형성되도록 메탈층을 선택 식각해서 게이트산화막(4)상에 메탈 게이트(10)를 형성한다.Next, as illustrated in FIG. 1G, the metal layer is selectively etched to be formed only on the gate oxide film 4, and then the metal gate 10 is formed on the gate oxide film 4.
소자가 고집적화될수록 선폭이 점점 작아져서 sub-70㎚ 정도의 소자에 상기 공정을 적용할 경우 메탈 게이트(10)를 식각하고 남은 잔여 메탈이 살리사이드(9)나 측벽스페이서(7)상에 잔존하여서 차후에 소자의 브리지 문제가 발생할 수 있다.As the device becomes more integrated, the line width becomes smaller, and when the above process is applied to a device having a sub-70 nm level, the remaining metal is etched after the metal gate 10 is left on the salicide (9) or the sidewall spacer (7). In the future, bridge problems may occur.
상기와 같은 종래 반도체소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 게이트산화막이 드러나도록 폴리실리콘패턴을 식각할 때 게이트산화막이 손실되어 소자 동작 신뢰성이 떨어지는 문제가 발생할 수 있다.First, when the polysilicon pattern is etched to reveal the gate oxide layer, the gate oxide layer may be lost, resulting in a deterioration of device operation reliability.
둘째, 메탈게이트를 형성하고 남은 잔여 메탈이 살리사이드층이나 측벽스페이서에 잔존해서 브리지 문제를 유발할 수 있다.Second, residual metal remaining after forming the metal gate may remain in the salicide layer or the sidewall spacers, which may cause a bridge problem.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 게이트산화막이 손실되지 않으며 메탈 잔여물에 의한 브리지 문제를 발생시키지 않는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in particular, it is an object of the present invention to provide a method for manufacturing a semiconductor device that does not lose the gate oxide film and does not cause bridge problems due to metal residues.
도 1a 내지 도 1g는 종래 기술에 따른 반도체소자의 제조방법을 나타낸 공정단면도1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2h는 본 발명에 따른 반도체소자의 제조방법을 나타낸 공정단면도2A through 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 실리콘기판 22 : 격리절연막21 silicon substrate 22 insulating film
23 : 제1도전형웰 24 : 제1감광막23: first conductive well 24: first photosensitive film
25 : 저농도 불순물영역 26 : 제2감광막25 low concentration impurity region 26 second photosensitive film
27 : 고농도 불순물영역 28 : 제1질화막27: high concentration impurity region 28: first nitride film
29 : 측벽스페이서 30 : 살리사이드층29 side wall spacer 30 salicide layer
31 : 제2질화막 32 : 게이트산화막31: second nitride film 32: gate oxide film
33 : 메탈 게이트33: metal gate
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 제조방법은 마스크패턴을 이용하여 상기 마스크패턴 양측의 기판내에 불순물영역을 형성하는 단계, 상기 불순물영역이 형성되지 않은 상기 기판상에 제1절연막 패턴을 형성하는 단계, 상기 제1절연막패턴 양측의 상기 불순물영역상에 살리사이드층을 형성하는 단계, 상기 제1절연막 패턴과 상기 살리사이드층을 포함한 전면에 제2절연막을 형성하는 단계, 상기 기판이 드러나도록 상기 제1절연막 패턴상부의 상기 제2절연막과 상기 제1절연막을 차례대로 제거하는 단계, 상기 드러난 기판표면에 게이트절연막을 형성하는 단계, 상기 게이트절연막상에 메탈게이트를 형성하는 단계, 상기 제2절연막을 제거하는 단계를 포함함을 특징으로 한다.In accordance with an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming an impurity region in a substrate on both sides of the mask pattern using a mask pattern, and forming a first insulating layer pattern on the substrate on which the impurity region is not formed. Forming a salicide layer on the impurity regions on both sides of the first insulating film pattern, and forming a second insulating film on the entire surface including the first insulating film pattern and the salicide layer. Removing the second insulating film and the first insulating film over the first insulating film pattern in order to expose the first insulating film; forming a gate insulating film on the exposed substrate surface; forming a metal gate on the gate insulating film; And removing the second insulating film.
첨부 도면을 참조하여 본 발명의 바람직한 실시예에 따른 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention will be described.
도 2a 내지 도 2h는 본 발명에 따른 반도체소자의 제조방법을 나타낸 공정단면도이다.2A through 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명에 따른 반도체소자의 제조방법은 도 2a에 도시한 바와 같이 격리영역과 활성영역이 정의된 실리콘기판(21)의 격리영역에 트랜치를 형성하고, 트랜치내에만 매립되도록 격리절연막(22)을 형성한다.According to the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. Form.
이후에 실리콘기판(21)의 일영역에 웰 이온 주입공정을 진행하여서 제1도전형웰(23)을 형성하는데, 이때 제1도전형웰(23)은 피모스 트랜지스터를 형성할 때는 N형의 웰을 형성하고, 앤모스 트랜지스터를 형성할 때는 P형의 웰을 형성한다.Thereafter, a well ion implantation process is performed in one region of the silicon substrate 21 to form the first conductive well 23, wherein the first conductive well 23 forms an N type well when forming a PMOS transistor. In forming the NMOS transistor, a P-type well is formed.
그리고 도 2b에 도시한 바와 같이 실리콘기판(21) 전면에 제1감광막(24)을 도포하고, 일정영역에만 남도록 노광 및 현상공정으로 선택적으로 패터닝한다.As shown in FIG. 2B, the first photosensitive film 24 is coated on the entire surface of the silicon substrate 21, and is selectively patterned by an exposure and developing process so as to remain only in a predetermined region.
이후에 패터닝된 제1감광막(24)을 마스크로 제1도전형웰(23)에 저농도의 제2도전형 이온을 주입해서 저농도 불순물영역(25)을 형성한다.Subsequently, a low concentration impurity region 25 is formed by implanting low concentration second conductive ions into the first conductive well 23 using the patterned first photoresist film 24 as a mask.
상기에서 제1도전형이 N형일 때 제2도전형은 P형이고, 제1도전형이 P형일때는 제2도전형은 N형이다.When the first conductive type is N type, the second conductive type is P type, and when the first conductive type is P type, the second conductive type is N type.
이하, 본 발명의 실시예에 따른 차후 도면에서는 제1도전형을 N형, 제2도전형을 P형으로 설명한다.In the following drawings according to an embodiment of the present invention, the first conductive type is described as N type, and the second conductive type is described as P type.
따라서 상기에서 저농도 불순물영역(25)은 P-이온으로 형성된다.Therefore, the low concentration impurity region 25 is formed of P-ion.
다음에 제1감광막(24)을 제거한 후에 도 2c에 도시한 바와 같이 제2감광막(26)을 도포하고, 노광 및 현상공정으로 상기 제1감광막(24)의 패턴된 폭보다 넓은 폭을 갖도록 제2감광막(26)을 선택적으로 패터닝한다.Next, after removing the first photoresist film 24, the second photoresist film 26 is applied as shown in FIG. 2C, and the exposure and development processes are performed to have a width wider than the patterned width of the first photoresist film 24. The second photosensitive film 26 is selectively patterned.
이어서 패터닝된 제2감광막(26)을 마스크로 드러난 제1도전형웰(23)내에 고농도 불순물영역(P+)(25)을 형성한다.Subsequently, a high concentration impurity region (P +) 25 is formed in the first conductive well 23 in which the patterned second photoresist layer 26 is exposed as a mask.
상기와 같은 공정에 의해서 LDD 구조의 소오스/드레인영역이 형성된다.By the above process, the source / drain regions of the LDD structure are formed.
도 2c의 점선은 차후에 메탈 게이트가 형성될 게이트 마스크 라인을 나타낸 것이다.The dashed line in FIG. 2C shows a gate mask line in which a metal gate will be formed later.
그리고 제2감광막(26)을 제거한 후에 도 2d에 도시한 바와 같이 실리콘기판(21) 전면에 제1질화막(28)을 증착하고, 저농도 불순물영역(25)과 고농도 불순물영역(27)이 형성되지 않은 제1도전형웰(23)이 드러나도록 제1질화막(28)을 선택적으로 식각한다.After removing the second photoresist film 26, the first nitride film 28 is deposited on the entire surface of the silicon substrate 21 as shown in FIG. 2D, and the low concentration impurity region 25 and the high concentration impurity region 27 are not formed. The first nitride film 28 is selectively etched to expose the first conductive well 23.
이후에 식각된 제1질화막(28)을 포함한 실리콘기판(21) 상에 질화막을 증착한 후에 에치백하여 제1질화막(28)의 측면에 측벽스페이서(29)를 형성한다.Thereafter, a nitride film is deposited on the silicon substrate 21 including the etched first nitride film 28 and then etched back to form sidewall spacers 29 on the side surfaces of the first nitride film 28.
이때 측벽스페이서(29)를 질화막으로 형성하는 이유는 차후에 게이트산화막을 형성하기 위한 산화공정시에 측벽스페이서(29)가 영향을 받지 않게 하기 위함이다.The reason why the sidewall spacers 29 are formed of a nitride film is to prevent the sidewall spacers 29 from being affected during the oxidation process for forming the gate oxide film later.
다음에 도 2e에 도시한 바와 같이 콘택저항을 줄이기 위해서 전면에 메탈층을 증착한 후에 열처리하여 고농도 불순물영역(27)상에 살리사이드층(30)을 형성하고, 잔존하는 메탈층을 제거한다.Next, as shown in FIG. 2E, a metal layer is deposited on the entire surface in order to reduce contact resistance, and then heat-treated to form the salicide layer 30 on the high concentration impurity region 27 to remove the remaining metal layer.
그리고 차후에 메탈게이트를 형성할 때 측벽스페이서(29)에 메탈 잔여불이 남지 않도록 도 2f에 도시한 바와 같이 전면에 대략 100Å 정도의 두께를 갖는 제2질화막(31)을 증착한다.When the metal gate is formed later, a second nitride film 31 having a thickness of about 100 μs is deposited on the entire surface of the sidewall spacer 29 so that no metal remaining light remains on the sidewall spacer 29.
도 2f의 점선은 차후에 메탈 게이트가 형성될 게이트 마스크 라인을 나타낸 것으로 이때 제1질화막(28)은 게이트 마스트 라인(차후에 형성될 메탈 게이트의 폭) 보다 0.1㎛정도 넓게 디파인하여서 차후에 게이트산화막을 형성하기 위한 습식 산화 공정시에 측벽스페이서(29)에 영향을 미치지 않게 하기 위함이다.The dotted line in FIG. 2F shows a gate mask line on which a metal gate will be formed later. In this case, the first nitride layer 28 is defined to be 0.1 μm wider than the gate mast line (the width of the metal gate to be formed later) to form a gate oxide layer later. This is to avoid affecting the sidewall spacer 29 during the wet oxidation process.
그리고 도 2g에 도시한 바와 같이 게이트 형성 마스크를 이용해서 제1질화막(29)상부의 제2질화막(31)을 선택적으로 식각하고, 이후에 제1도전형웰(23)이 드러나도록 제1질화막(28)을 선택적으로 식각한다.As shown in FIG. 2G, the second nitride film 31 over the first nitride film 29 is selectively etched using the gate forming mask, and then the first nitride well 23 is exposed to expose the first conductive well 23. Selectively etch 28).
다음에 도 2h에 도시한 바와 같이 습식 산화(wet oxidation)공정을 진행하여 드러난 제1도전형웰(23)의 표면에 게이트산화막(32)을 형성한다.Next, as shown in FIG. 2H, a gate oxide film 32 is formed on the surface of the first conductive well 23 exposed by the wet oxidation process.
이후에 게이트산화막(32)상의 측벽스페이서(29) 사이를 매립하도록 메탈층을 전면에 증착하고, 측벽스페이서(29)사이에만 매립되도록 선택적으로 메탈층을 식각하여 메탈 게이트(33)를 형성한다. 이때 메탈층을 과도식각해도 제2질화막(31)이 버퍼역할을 해준다.Subsequently, the metal layer is deposited on the entire surface of the gate oxide layer 32 so as to fill the space between the sidewall spacers 29, and the metal layer 33 is selectively etched so as to fill the space between the sidewall spacers 29 to form the metal gate 33. At this time, even if the metal layer is excessively etched, the second nitride layer 31 serves as a buffer.
이후에 잔여 메탈층과 제2질화막(31)을 제거한다.Thereafter, the remaining metal layer and the second nitride film 31 are removed.
상기와 같은 본 발명 반도체소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing the semiconductor device of the present invention as described above has the following effects.
첫째, 폴리실리콘대신에 제1질화막을 증착시키고, 제1질화막을 제거한 깨끗한 기판상에 게이트산화막을 성장시키기 때문에 게이트산화막의 결함이 발생하는 것을 방지하여서 소자 동작 신뢰성을 향상시킬 수 있다.First, since the first nitride film is deposited instead of polysilicon and the gate oxide film is grown on a clean substrate from which the first nitride film is removed, defects in the gate oxide film can be prevented from occurring, thereby improving device operation reliability.
둘째, 살리사이드 형성후에 보호막으로써 제2질화막을 형성하므로 메탈게이트 형성후에 차후에 메탈 잔여물이 남아서 브리지(bridge) 문제가 발생하는 것을 방지할 수 있다. 이와 같은 공정은 특히 고집적회로를 구현해야하는 sub-70㎚ 이하의 소자에 유용하게 쓰일 수 있다.Second, since the second nitride film is formed as a protective film after the salicide is formed, it is possible to prevent the occurrence of bridge problems due to the remaining metal residue after the formation of the metal gate. Such a process may be particularly useful for devices of sub-70 nm or less that require high integrated circuits.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0037122A KR100418923B1 (en) | 2001-06-27 | 2001-06-27 | method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0037122A KR100418923B1 (en) | 2001-06-27 | 2001-06-27 | method for fabricating semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030001764A KR20030001764A (en) | 2003-01-08 |
| KR100418923B1 true KR100418923B1 (en) | 2004-02-14 |
Family
ID=27711535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0037122A KR100418923B1 (en) | 2001-06-27 | 2001-06-27 | method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100418923B1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920015433A (en) * | 1991-01-15 | 1992-08-26 | 문정환 | MOS transistor process method |
| US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
| KR20000003478A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Production method of mosfet for semiconductor device |
| JP2000031291A (en) * | 1998-07-13 | 2000-01-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JP2001036083A (en) * | 1999-06-29 | 2001-02-09 | Hyundai Electronics Ind Co Ltd | Method for forming mos transistor using damascene and chemical mechanical polishing process |
-
2001
- 2001-06-27 KR KR10-2001-0037122A patent/KR100418923B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920015433A (en) * | 1991-01-15 | 1992-08-26 | 문정환 | MOS transistor process method |
| US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
| KR20000003478A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Production method of mosfet for semiconductor device |
| JP2000031291A (en) * | 1998-07-13 | 2000-01-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JP2001036083A (en) * | 1999-06-29 | 2001-02-09 | Hyundai Electronics Ind Co Ltd | Method for forming mos transistor using damascene and chemical mechanical polishing process |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030001764A (en) | 2003-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100731096B1 (en) | A semiconductor device and a method for fabricating the same | |
| KR100469913B1 (en) | Manufacturing method for semiconductor device | |
| KR20080026517A (en) | Semiconductor device and manufacturing method thereof | |
| KR100418923B1 (en) | method for fabricating semiconductor device | |
| KR100379531B1 (en) | method for manufacturing of semiconductor device | |
| KR100223920B1 (en) | Method of manufacturing semiconductor device | |
| KR100261682B1 (en) | Method for fabricating semiconductor device | |
| KR100944344B1 (en) | Manufacturing method for semiconductor device | |
| KR101167192B1 (en) | Manufacturing method for high voltage device | |
| KR100226753B1 (en) | Forming method for metallization of semiconductor device | |
| KR100778877B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR100743629B1 (en) | Method of manufacturing semiconductor device | |
| KR100910222B1 (en) | Method of manufacturing semiconductor device applied dual gate oxide | |
| KR101025919B1 (en) | Method for forming multi gate oxide layer | |
| KR100678009B1 (en) | Method for forming gate of a transister | |
| KR100325460B1 (en) | Method of fabricating semiconductor device for preventing bit line from being shorted to conducting layer of gate electrode | |
| KR20020058512A (en) | Method for fabricating semiconductor device | |
| KR0139575B1 (en) | Method of manufacture in semiconductor device | |
| KR100564432B1 (en) | Method for manufacturing Transistor | |
| KR100239452B1 (en) | Method for manufacturing semiconductor device | |
| KR20060108035A (en) | Method for fabricating flash memory device | |
| KR19990057055A (en) | Manufacturing method of semiconductor device | |
| KR20050056350A (en) | Method of manufacturing cmos image sensor | |
| KR20050014156A (en) | Manufacturing method for semiconductor device | |
| KR20040001485A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130122 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20140116 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20150116 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |