KR20050014156A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor deviceInfo
- Publication number
- KR20050014156A KR20050014156A KR1020030052648A KR20030052648A KR20050014156A KR 20050014156 A KR20050014156 A KR 20050014156A KR 1020030052648 A KR1020030052648 A KR 1020030052648A KR 20030052648 A KR20030052648 A KR 20030052648A KR 20050014156 A KR20050014156 A KR 20050014156A
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- KR
- South Korea
- Prior art keywords
- hard mask
- mask layer
- landing plug
- forming
- contact hole
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 모스 전계효과 트랜지스터(Metal Oxide Semi conductor Field Effect Transistor; 이하 MOS FET라 칭함)의 게이트전극 보호를 위한 하드마스크층에 의한 스트레스를 감소시켜 스트레스에 의한 누설전류를 감소시키고, 리플레쉬 특성 저하를 방지할 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, to reduce stress caused by a hard mask layer for protecting a gate electrode of a metal oxide semi-conductor field effect transistor (hereinafter referred to as a MOS FET). The present invention relates to a method for manufacturing a semiconductor device capable of reducing leakage current and preventing a decrease in refresh characteristics.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
이러한 감광막 패턴의 분해능(R)은 감광막 자체의 재질이나 기판과의 접착력등과도 밀접한 연관이 있으나, 일차적으로는 사용되는 축소노광장치의 광원 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture; NA, 개구수)에 반비례한다.The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.
[R=k*λ/NA, R=해상도, λ= 광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 라인/스페이스 패턴의 경우 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해서는 이보다 파장이 더 작은 원자외선(deep ultra violet; DUV), 예를들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하여야 한다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.
또한 축소노광장치와는 별도로 공정 상의 방법으로는 노광마스크(photo mask)로서 위상반전마스크(phase shift mask)를 사용하는 방법이나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법이나, 두층의 감광막 사이에 에스.오.지(spin on glass; SOG)등의 중간층을 개재시킨 삼층레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션방법 등이 개발되어 분해능 한계치를 낮추고 있다.In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photoresist film has been developed to lower the resolution limit.
또한 상하의 도전배선을 연결하는 콘택홀은 상기에서의 라인/스페이스 패턴에 비해 디자인룰이 더 크게 나타나는데, 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택 형성 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소돠거나, 여유가 전혀없이 공정을 진행하여야하는 어려움이 있다.In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.
이러한 콘택홀은 홀간의 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.
상기와 같은 콘택홀의 형성 방법으로는 직접 식각 방법과, 측벽 스페이서를 사용하는 방법 및 SAC 방법등이 있다.As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.
상기에서 직접 식각방법과 측벽 스페이서 형성 방법은 현재의 재반 기술 수준에서 0.3㎛ 이하의 디자인 룰을 갖는 소자 제조에는 사용할 수 없어 소자의 고집적화에 한계가 있다.In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.
또한 콘택홀 형성시 리소그래피(Lithography) 공정의 한계를 극복하기 위하여 고안된 SAC 방법은 식각장벽층으로 사용하는 물질에 따라 다결정실리콘층이나 질화막 또는 산화질화막등을 사용하는 것으로 나눌 수 있으며, 가장 유망한 것으로질화막을 식각 방어막으로 사용하는 방법이 있다.In addition, the SAC method, which is designed to overcome the limitations of the lithography process when forming contact holes, can be divided into polysilicon layer, nitride layer, or oxynitride layer, depending on the material used as the etch barrier layer. Can be used as an etch shield.
도 1은 종래 기술에 따른 반도체소자의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the prior art.
먼저, 반도체기판(10)상에 게이트산화막(12)을 형성하고, 상기 게이트산화막(12)상에 질화막 재질의 하드마스크층(16)과 중첩되어있는 게이트전극(14)을 형성한 후, 상기 게이트전극(14)과 하드마스크층(16)의 측벽에 질화막 재질의 스페이서(18)를 형성한다.First, a gate oxide film 12 is formed on the semiconductor substrate 10, and a gate electrode 14 overlapping the hard mask layer 16 made of a nitride film is formed on the gate oxide film 12. A spacer 18 made of a nitride film is formed on sidewalls of the gate electrode 14 and the hard mask layer 16.
그다음 상기 구조의 전표면에 층간절연막(도시되지 않음)을 형성한 후, 랜딩 플러그 마스크를 이용하여 상기 반도체기판(10)에서 콘택으로 예정되어있는 부분상의 층간절연막을 제거하여 콘택홀을 형성한 후, 전면에 랜딩 플러그용 다결정실리콘층(도시되지 않음)을 도포하고, 상기 다결정실리콘층의 상부를 CMP 등의 방법으로 식각하여 분리시켜 랜딩플러그(20)를 형성한다.Then, an interlayer insulating film (not shown) is formed on the entire surface of the structure, and then a contact hole is formed by removing the interlayer insulating film on the portion scheduled as a contact from the semiconductor substrate 10 using a landing plug mask. In addition, a polycrystalline silicon layer (not shown) for a landing plug is coated on the entire surface, and the upper portion of the polycrystalline silicon layer is etched and separated by a method such as CMP to form a landing plug 20.
이와 같이 형성된 반도체소자는 도 2에서와 같은 단면을 가지게 된다.The semiconductor device thus formed has a cross section as shown in FIG. 2.
상기와 같은 종래 기술에 따른 반도체소자의 제조방법은 게이트전극을 보호하고 자기정렬 콘택 형성을 위해 사용되는 질화막 재질의 하드마스크층을 구비하게되는데, 이러한 하드마스크층에 의해 도 3에 도시된 것과 같이 기계적인 스트레스가 게이트산화막에 주어지게되면, SILC(stress induced leakage current)가 가해지면 게이트산화막의 누설전류가 10배 이상 증가하게되고, DRAM의 보전시간을 감소시켜 리플레쉬 특성을 열화시키는 등의 문제점이 있다.The method of manufacturing a semiconductor device according to the related art as described above includes a hard mask layer made of a nitride film used for protecting a gate electrode and forming a self-aligned contact, as shown in FIG. 3 by such a hard mask layer. When mechanical stress is applied to the gate oxide layer, when a stress induced leakage current (SILC) is applied, the leakage current of the gate oxide layer is increased by 10 times or more, and the refresh time is reduced by reducing the DRAM maintenance time. There is this.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은랜딩플러그 형성 후에 하드마스크층의 일부를 산화막 재질로 대체하여 기계적 스트레스를 감소시켜 소자의 리플레쉬 특성 저하를 방지하여 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to replace the part of the hard mask layer with an oxide film after the landing plug is formed to reduce mechanical stress to prevent the degradation of the refresh characteristics of the device process yield and It is to provide a method of manufacturing a semiconductor device that can improve the reliability of device operation.
도 1은 종래 기술에 따른 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 2는 도1 상태 소자의 단면 TEM 사진.2 is a cross-sectional TEM photograph of the FIG. 1 state element;
도 3은 게이트산화막의 기계적 스트레스 유무에 따른 SILC 그래프.3 is a SILC graph according to the presence or absence of mechanical stress of the gate oxide film.
도 4a 내지 도 4c는 본 발명에 따른 반도체소자의 제조공정도.Figures 4a to 4c is a manufacturing process of the semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10, 30 : 반도체기판 12, 32 : 게이트산화막10, 30: semiconductor substrate 12, 32: gate oxide film
14, 34 : 게이트전극 16, 36, 41 : 하드마스크층14, 34: gate electrodes 16, 36, 41: hard mask layer
18, 38 : 스페이서용 질화막 20, 40 : 랜딩플러그18, 38: nitride film for spacer 20, 40: landing plug
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
반도체기판상에 게이트산화막을 형성하는 공정과,Forming a gate oxide film on the semiconductor substrate;
상기 게이트산화막 상에 질화막 재질의 제1하드마스크층 패턴과 중첩되어있는 게이트전극을 형성하는 공정과,Forming a gate electrode overlapping the first hard mask layer pattern of a nitride film on the gate oxide film;
상기 게이트전극과 제1하드마스크층 패턴의 측벽에 절연 스페이서를 형성하는 공정과,Forming an insulating spacer on sidewalls of the gate electrode and the first hard mask layer pattern;
상기 구조의 전표면에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the entire surface of the structure;
상기 랜딩플러그 콘택홀 마스크를 이용하여 상기 층간절연막을 선택식각하여 랜딩플러그용 콘택홀을 형성하는 공정과,Forming a landing plug contact hole by selectively etching the interlayer insulating layer using the landing plug contact hole mask;
상기 랜딩플러그용 콘택홀을 메우는 랜딩플러그를 형성하는 공정과,Forming a landing plug that fills the landing plug contact hole;
상기 제1하드마스크층을 일정 두께 제거하여 게이트 산화막의 스트레스를 감소시키는 공정과,Removing the first hard mask layer by a predetermined thickness to reduce stress of the gate oxide layer;
상기 제1하드마스크층 패턴상에 산화막 재질의 제2하드마스크층 패턴을 형성하는 공정을 구비함에 있다.And forming a second hard mask layer pattern of an oxide film on the first hard mask layer pattern.
또한 본 발명의 다른 특징은, 상기 제2하드마스크층 패턴은 BPSG, USG 또는플라즈마 유도 CVD 산화막으로 형성하는 것을 특징으로 한다.In addition, another feature of the present invention is characterized in that the second hard mask layer pattern is formed of BPSG, USG or plasma induced CVD oxide.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 4a 내지 도 4c는 본 발명에 따른 반도체소자의 제조공정도이다.4A to 4C are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 반도체기판(30)상에 게이트산화막(32)을 형성하고, 상기 게이트산화막(32) 상에 게이트전극(34) 및 상기 게이트전극(34)과 중첩되어있는 제1하드마스크층(36) 패턴을 형성한다. 여기서 상기 게이트전극(34)은 다결정실리콘 상에 W이나 텅스텐 실리사이드가 적층되어있는 저저항 구조로 형성하며, 상기 제1하드마스크층(36)은 질화막 재질로 형성한다.First, the gate oxide film 32 is formed on the semiconductor substrate 30, and the first hard mask layer 36 overlaps the gate electrode 34 and the gate electrode 34 on the gate oxide film 32. Form a pattern. The gate electrode 34 is formed of a low resistance structure in which W or tungsten silicide is stacked on polycrystalline silicon, and the first hard mask layer 36 is formed of a nitride film material.
그다음 상기 게이트전극(34)과 하드마스크층(36) 패턴의 측벽에 질화막 재질의 스페이서(38)를 형성하고, 상기 구조의 전표면에 산화막 재질의 층간절연막(도시되지 않음)을 도포한 후, 랜딩플러그 마스크를 이용하여 상기 반도체기판(30)에서 콘택으로 예정되어있는 부분상의 층간절연막을 제거하여 콘택홀을 형성한 후, 상기 구조의 전표면에 다결정실리콘층을 도포하고, 상기 다결정실리콘층의 상부를 CMP 식각하여 상기 제1하드마스크층(36)의 상부를 노출시켜 서로 분리된 랜딩플러그(40)를 형성한다.Then, a spacer 38 of nitride material is formed on sidewalls of the gate electrode 34 and the hard mask layer 36 pattern, and an interlayer insulating film (not shown) of an oxide film is applied to the entire surface of the structure. A contact hole is formed by removing an interlayer insulating film on a portion of the semiconductor substrate 30, which is supposed to be a contact, using a landing plug mask. Then, a polysilicon layer is coated on the entire surface of the structure, and the polysilicon layer is CMP etching the upper portion to expose the upper portion of the first hard mask layer 36 to form a landing plug 40 separated from each other.
그후 상기 제1하드마스크층(36)의 일부 두께, 예를 들어 총 두께의 10∼30% 정도 만 남도록 그 상부를 제거하여 질화막에 의한 기계적인 스트레스를 제거한다. (도 4a 참조).Thereafter, the upper portion of the first hard mask layer 36 is removed so that only a portion of the first hard mask layer 36 remains, for example, about 10 to 30% of the total thickness, thereby removing mechanical stress caused by the nitride layer. (See FIG. 4A).
그다음 상기 구조의 전표면에 BPSG, USG, 플라즈마 유도 CVD 산화막등으로된산화막 재질의 제2하드마스크층(41)을 도포한 후, (도 4b 참조), 상기 제2하드마스크층(41)의 상부를 식각하여 상기 랜딩플러그(40)를 노출시켜, 상기 제1하드마스크층(36)의 남아 있는 상부에 제2하드마스크층(41) 패턴이 남도록한다. 즉 질화막을 일부 제거하여 그로 인한 게이트산화막의 스트레스를 방지하고, 대신 산화막 재질로 그 자리를 대체하는 것이다. (도 4c 참조).Then, after applying the second hard mask layer 41 made of an oxide film made of BPSG, USG, plasma induced CVD oxide, etc. on the entire surface of the structure (see FIG. 4B), the second hard mask layer 41 The upper surface is etched to expose the landing plug 40 so that the second hard mask layer 41 pattern remains on the remaining upper portion of the first hard mask layer 36. In other words, the nitride film is partially removed to prevent stress of the gate oxide film, and the place is replaced with an oxide film instead. (See FIG. 4C).
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은 게이트전극과 중첩되는 하드마스크층을 일차로 질화막 재질로 형성하고, 랜딩플러그를 형성한 후에 질화막 재질의 하드마스크층 일부 두께를 제거하여 질화막에 의한 게이트산화막의 기계적 스트레스를 감소시킨 후, 제거된 자리를 산화막 재질로 체우고 후속 공정을 진행하였으므로, 소자의 누설전류가 감소되어 리플레쉬 특성이 향상되고, 스트레스로 인한 산화막의 열화를 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the hard mask layer overlapping the gate electrode is formed of a nitride film primarily, and after the landing plug is formed, the thickness of the hard mask layer of the nitride film is removed to remove the nitride film. After the mechanical stress of the gate oxide film was reduced, the removed site was filled with the oxide film material, and the subsequent process was performed. Therefore, the leakage current of the device is reduced, thereby improving the refresh characteristics and preventing the oxide film from deterioration due to stress. There is an advantage that can improve the process yield and the reliability of the device.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100829606B1 (en) * | 2006-09-07 | 2008-05-14 | 삼성전자주식회사 | Method of forming fine pattern in a semiconductor device fabricating |
| CN106409764A (en) * | 2015-08-03 | 2017-02-15 | 联华电子股份有限公司 | Method of making semiconductor component |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100829606B1 (en) * | 2006-09-07 | 2008-05-14 | 삼성전자주식회사 | Method of forming fine pattern in a semiconductor device fabricating |
| CN106409764A (en) * | 2015-08-03 | 2017-02-15 | 联华电子股份有限公司 | Method of making semiconductor component |
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