KR20040080574A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent damage and to increase process margin of gate patterning by using a dual hard mask layer. CONSTITUTION: A conductive layer and the first hard mask layer are sequentially formed on a substrate(30). A gate electrode(34) overlapped with the first hard mask pattern(36) is formed by patterning the first hard mask layer and the conductive layer. An insulating spacer(38) is formed at both sidewalls of the gate electrode and the first hard mask pattern. The first interlayer dielectric(40) and the second hard mask pattern(42) are sequentially formed on the resultant structure. The second interlayer dielectric(46) is formed on the resultant structure. A contact hole is formed to expose the substrate. Then, a contact plug(52) is formed in the contact hole.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a gate hard mask layer is formed in a double layer to increase the process margin of contact holes, and prevent a short circuit of the gate electrode to improve process yield and reliability of device operation. It relates to a method for manufacturing a device.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, ~ R = resolution, ~ λ = wavelength of light source, NA = opening number ~]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a self-aligned contact method, and the like.

In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.

In addition, the self-aligned contact method designed to overcome the limitations of the lithography process when forming contact holes can be divided into polysilicon layer, nitride film or oxynitride film, depending on the material used as the etch barrier layer. One method is to use nitride as an etch shield.

1A and 1B are a manufacturing process diagram of a semiconductor device according to the prior art, which is an example of a self-aligned contact.

First, a pattern of a hard mask layer 16 overlapping the gate oxide film 12, the gate electrode 14, and the gate electrode 14 is formed on the semiconductor substrate 10. An insulating spacer 18 is formed on the sidewall of the mask layer 16 pattern.

Next, an interlayer insulating film 20 is formed on the entire surface of the structure, and a photosensitive film pattern 22 for forming a contact is formed on the interlayer insulating film 20. (See FIG. 1A).

Thereafter, the interlayer insulating film 20, in which the photoresist pattern 22 is exposed as a mask, is etched to form a contact hole, and a contact plug 24 filling the contact hole is formed. (See FIG. 1B).

The method of manufacturing a semiconductor device according to the prior art as described above has an advantage in the process of forming a contact plug by using a self-aligned contact by using a gate hard mask layer. However, due to the hole type characteristics, the bar contact plug is reached due to the exposure limit. Although the bar contact plug has been developed to form a line / space pattern, exposure to the line width is possible, but the thickness of the hard mask layer serving as a mask is reduced, resulting in a smaller process margin when forming the upper layer plug in a subsequent process. There is a problem that causes a defect such as a short circuit, there is a limit in the process capability, which hinders the high integration of the device.

In addition, in order to solve the problem, increasing the thickness of the hard mask layer may result in an uneven line width during word line exposure, voids may be formed in the insulating film when the insulating film is deposited, and the etching process may be difficult.

The present invention is to solve the above problems, an object of the present invention by using a double hard mask layer to reduce the thickness of the hard mask layer to prevent the other deduction of clearance, and to prevent short circuits due to a pattern failure. By providing a method of manufacturing a semiconductor device that can improve the process yield and the reliability of device operation.

1A and 1B are manufacturing process diagrams of a semiconductor device according to the prior art.

2a to 2e is a manufacturing process diagram of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 30: semiconductor substrate 12, 32: gate oxide film

14, 34: gate electrodes 16, 36, 42: hard mask layer

18, 38: insulation spacer 20, 40, 46: interlayer insulating film

22, 44, 48: photoresist pattern 24, 52: contact plug

50: conductive layer

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a first interlayer insulating film on the semiconductor substrate;

Sequentially forming a conductive layer and a first hard mask layer on the first interlayer insulating film;

Photo-etching the first hard mask layer and the conductive layer using a conductive wiring patterning mask to form a conductive layer pattern overlapping the first hard mask layer pattern;

Forming an insulating spacer on sidewalls of the conductive layer pattern and the first hard mask layer pattern;

Sequentially forming a second interlayer insulating film and a second hard mask layer on the entire surface of the structure;

Photo-etching the second hard mask layer with the conductive layer patterning mask to form a second hard mask layer pattern on the conductive layer pattern;

Forming a third interlayer insulating film on the entire surface of the structure;

Selectively removing the photolithography process using a contact mask from the third interlayer insulating film to the first interlayer insulating film to form contact holes;

And forming a contact plug filling the contact.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are diagrams illustrating a process of manufacturing a semiconductor device according to the present invention, which is an example of a bar contact plug.

First, the gate oxide layer 32 is formed on the semiconductor substrate 30, and the gate electrode 34 overlapping the first hard mask layer 36 pattern is formed on the gate oxide layer 32. After forming insulating spacers 38 on the sidewalls of the gate electrode 34 and the first hard mask layer 36 pattern, and forming the first interlayer insulating film 40 on the entire surface of the structure, the first interlayer insulating film A second hard mask layer 42 is formed on the 40, and a first photoresist pattern 44, which is the gate patterning mask, is formed. (See FIG. 2A).

Next, the second hard mask layer 42 is etched using the first photoresist pattern 44 as a mask to form a second hard mask layer 42 pattern on the gate electrode 34, and the first photoresist layer After the pattern 44 is removed, a second interlayer insulating film 46 is formed on the entire surface of the structure. The first and second hard mask layers 36 and 42 may be formed of a material having an etching selectivity difference from the first and second interlayer insulating films 40 and 46, for example, a nitride film. (See FIG. 2B).

Thereafter, a second photoresist film pattern 48 that is a bar plug contact mask is formed on the second interlayer insulating film 46 (see FIG. 2C), and the second photoresist film pattern 48 is interposed between the second and first layers. The insulating films 46 and 40 are sequentially removed to form contact holes, and the plug conductive layer 50 is applied to the entire surface of the structure to fill the contact holes. (See FIG. 2D).

Then, the upper portion of the conductive layer 50 is etched by chemical mechanical polishing to form a contact plug 52 separated for each contact. In this case, a portion of the upper portion of the second interlayer insulating layer 46 and the second hard mask layer 42 is removed, but the second hard mask layer 42 serves as an etch stop layer. (See FIG. 2E).

Although the gate hard mask layer is taken as an example, the same may be applied to the hard mask of a bit line or other conductive wiring.

As described above, the method of manufacturing a semiconductor device according to the present invention includes a hard mask layer on the gate electrode, and the upper hard mask layer is patterned by a gate patterning mask, and the contact opening and the conductive layer are applied and etched. Since the contact plugs are separated for each cell, the upper hard mask layer becomes an etch barrier layer, and thus, damage to the lower hard mask layer can be prevented and can be formed thinly. Therefore, the process margin in gate patterning is increased, which is advantageous for pattern uniformity. In addition, in the subsequent contact process, since the upper hard mask layer serves as an etch barrier, defects such as a short circuit of the pattern can be prevented, thereby improving process yield and reliability of device operation.

Claims (1)

Forming a first interlayer insulating film on the semiconductor substrate; Sequentially forming a conductive layer and a first hard mask layer on the first interlayer insulating film; Photo-etching the first hard mask layer and the conductive layer using a conductive wiring patterning mask to form a conductive layer pattern overlapping the first hard mask layer pattern; Forming an insulating spacer on sidewalls of the conductive layer pattern and the first hard mask layer pattern; Sequentially forming a second interlayer insulating film and a second hard mask layer on the entire surface of the structure; Photo-etching the second hard mask layer with the conductive layer patterning mask to form a second hard mask layer pattern on the conductive layer pattern; Forming a third interlayer insulating film on the entire surface of the structure; Selectively removing the photolithography process using a contact mask from the third interlayer insulating film to the first interlayer insulating film to form contact holes; And forming a contact plug to fill the contact.