KR100702308B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and includes a contact plug, a word line, or a bottom portion of a guarding capacitor formed at an edge of a cell block in a cylindrical storage electrode forming process. In the chemical mechanical polishing process for providing a lower structure such as a bit line to separate the storage electrodes, the storage electrodes are collapsed due to the step between the cell region and the peripheral circuit region, or the residues generated therefrom. It is a technology that improves the characteristics and reliability of semiconductor devices by preventing the bridges between devices.

Description

Manufacturing method for semiconductor device

1 is a photograph showing a problem of a method of manufacturing a semiconductor device according to the prior art.

2A to 2C are plan views of each device formed in the cell block in the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

10 semiconductor substrate 12 device isolation insulating film

14 gate electrode 16 silicide film pattern

18: first mask insulating film pattern 20: first insulating film spacer

22 contact plug 24 first interlayer insulating film

26: second interlayer insulating film 28: bit line contact

29 bit line 30 second mask insulating film pattern

32: second insulating film spacer 34: third interlayer insulating film

36: fourth interlayer insulating film 38: storage electrode contact                 

40: first sacrificial insulating film 42: storage electrode

44: MPS film 46: second sacrificial insulating film

50: dummy storage electrode contact 110: cell block

120: guard ring gate electrode 130: dummy gate electrode

140: gate electrode 200: guard ring bit line

210: dummy bit line 220: redundancy bit line

230: bit line 300: storage electrode

310: dummy storage electrode 320: guard ring storage electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a dummy pattern is formed at the bottom of a guard ring storage electrode formed at an edge of a cell block to reduce the step between the cell region and the peripheral circuit region, thereby electrically separating the storage electrodes. It relates to a method for manufacturing a semiconductor device that facilitates a chemical mechanical polishing (hereinafter referred to as CMP) process.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a light source of deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 193 nm, to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes have misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.

In addition, in order to overcome the limitations of the lithography process in forming the contact hole, a technology for forming the contact hole by a self-aligning method has been developed.

Although not shown, a method of manufacturing a semiconductor device according to the related art is as follows.

First, a device isolation insulating film and a gate insulating film are formed on a semiconductor substrate, and a substructure such as a MOS field effect transistor, a bit line, and the like is formed of a gate electrode and a source / drain electrode.

Next, an interlayer insulating film having a storage electrode contact hole for exposing a portion of the source / drain electrode to be a storage electrode contact is formed.

Next, a storage electrode contact plug for filling the storage electrode contact hole is formed, and a first sacrificial insulating film is formed over the entire surface to expose a portion intended as the storage electrode.

A conductive electrode layer for the storage electrode is formed on the entire surface, and a metastable polysilicon (MPS) film is formed on the surface of the conductive layer for the storage electrode in order to increase capacitance. 2 A sacrificial insulating film is formed.

Next, the second sacrificial insulating film, the MPS film, and the conductive layer for the storage electrode are removed by the CMP process to electrically insulate the storage electrodes.                         

Next, the first sacrificial insulating film and the second sacrificial insulating film are removed, and a dielectric film and a plate electrode are formed.

In the method of manufacturing a semiconductor device according to the related art, a guard ring storage electrode is formed along the cell block in addition to the dummy storage electrode formed at the edge of the cell block due to the CMP process for electrically insulating the storage electrode. Although the dummy gate electrode and the dummy bit line may be formed at the bottom of the storage electrode, the uniformity between the cell region and the peripheral circuit area may be improved during the CMP process. Since there is no uniformity during the CMP process, as shown in FIG. 1, the storage electrodes formed in the cell block are collapsed or excessively removed, causing bridges between the storage electrodes, and deteriorating electrical characteristics of the device.

In order to solve the above-mentioned problems of the related art, a cell structure and a peripheral circuit are formed by forming a lower structure such as a dummy gate electrode, a dummy bit line, or a contact plug at the bottom of the guard ring storage electrode formed at the edge of the cell block. After alleviating the step difference between the regions, the CMP process that separates the upper portion of the storage electrode prevents the storage electrode from falling or being excessively removed, thereby preventing the bridge from occurring between the storage electrodes and improving the electrical characteristics of the semiconductor device. Its purpose is to provide a method for manufacturing a semiconductor device.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
In the method of manufacturing a semiconductor device to form a guard ring storage electrode on the cell block edge,

Forming a lower structure of the guard ring gate electrode and the guard ring bit line at the bottom of the guard ring storage electrode to alleviate the step between the cell region and the peripheral circuit region;
A guard ring gate electrode, a dummy gate electrode, a redundancy gate electrode, and a gate electrode are sequentially provided from the edge of the cell block toward the center portion, and a process of forming a contact plug between the guard ring gate electrode and the dummy gate electrode is further performed. To include, the width of the guard ring gate electrode is formed to the same size as the width of the gate electrode, the width of the guard ring gate electrode is formed to be different from the width of the gate electrode,
A guard ring gate electrode, a dummy gate electrode, and a gate electrode are sequentially provided from the edge of the cell block toward the center portion;
A guard ring bit line, a dummy bit line, a redundancy bit line, and a bit line are sequentially provided from the edge of the cell block toward the center, and the guard ring bit line, the dummy bit line, and the bit line are sequentially arranged from the edge of the cell block toward the center. The method further includes forming a storage electrode contact between the guard ring bit line and the dummy bit line, wherein the width of the guard ring bit line is equal to the width of the bit line. The width of the guard ring bit line is formed to be different from the width of the bit line,
The width of the guard ring bit line is formed to the same size as the width of the guard ring gate electrode,
The width of the guard ring bit line is formed to be different from the width of the guard ring gate electrode,
The width of the guard ring storage electrode is formed to be the same as the width of the guard ring gate electrode or guard ring bit line,
The width of the guard ring storage electrode is formed to be different from the width of the guard ring gate electrode or guard ring bit line;
In the lower structure, the storage electrode contact is formed on the guard ring gate electrode.

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Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are plan views illustrating elements formed in a cell block in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 3A to 3E are semiconductor devices according to the first embodiment of the present invention. 3A to 3D illustrate a cut section aa 'of FIG. 2A.

FIG. 2A is a plan view illustrating a gate electrode formed in a cell block. A guard ring gate electrode 120 is formed at an edge of the cell block 110 and a dummy gate electrode 130 is formed inside the guard ring gate electrode 120. ), Then a redundancy gate electrode (not shown) and a gate electrode 140 are formed in the dummy gate electrode 130.

2A and 3A, a device isolation insulating film 12 is formed on a semiconductor substrate 10, a gate insulating film (not shown) is formed, and a gate electrode 14 and a source / drain electrode (not shown) are formed. A MOS field effect transistor is formed. In this case, the gate electrode 14 has the silicide layer pattern 16 and the first mask insulating layer pattern 18 stacked thereon, and the first mask insulating layer pattern 18, the silicide layer pattern 16, and the gate electrode ( The first insulating layer spacer 20 is provided on the sidewall of the substrate 14.

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In the process, the guard ring gate electrode 120 and the dummy gate electrode 130 are formed at the same time, and the width of the guard ring gate electrode 120 is wider than the dummy gate electrode 130 and the gate electrode 140 or the same. It can be formed in size.

One or more guard ring gate electrodes 120 may be formed on both edges of the cell block 110.

Next, the first interlayer insulating film 24 is formed on the entire surface of the semiconductor substrate, and the first interlayer insulating film 24 is removed using an etching mask that exposes portions intended as bit line contacts and storage electrode contacts. 10). In this case, the etching mask does not expose the gap between the guard ring gate electrode 120 and the dummy gate electrode 130.

Then, a conductive layer is formed on the entire surface, and a contact plug 22 connected to the semiconductor substrate 10 is formed by performing a front surface etching or a CMP process.

2B, 3B, and 3D, the bit line is formed in a direction perpendicular to the gate electrode in the cell block, and a guard ring bit line 200 is formed at an edge of the cell block, and the dummy bit is moved inward. The line 210, the redundancy bit line 220, and the bit line 230 are formed in this order. In this case, at least one guard ring bit line 200 may be formed at an edge of the cell block, and the width of the guard ring bit line 200 may be different from that of the bit line 230 or the guard ring gate electrode 120, or may be formed to have the same size. . In addition, the formation of the dummy bit line 210 may be omitted.

Next, a second interlayer insulating layer 26 having a bit line contact hole for exposing a portion of the contact plug 22 to be a bit line contact is formed on the entire surface.

Next, a bit line contact 28 connected to the contact plug 22 is formed through the bit line contact hole. In this case, the contact plug 22 may or may not be formed at the portion where the guard ring bit line 200 is to be formed.

Next, a stack structure of the bit line 29 and the second mask insulating film pattern 30 connected to the bit line contact 28 is formed, and a second insulating film spacer 32 is formed on the sidewall of the stack structure.

Next, a third interlayer insulating film 34 and a fourth interlayer insulating film 36 having an etch selectivity difference with the third interlayer insulating film 34 are sequentially formed on the entire surface.

Next, the fourth interlayer dielectric layer 36, the third interlayer dielectric layer 34, and the second interlayer dielectric layer 26 are formed by using a contact mask that exposes a portion of the contact plug 22 to be a storage electrode contact as an etch mask. ) Is formed to form the storage electrode contact hole.

Next, a storage electrode contact 38 connected to the contact plug 22 is formed through the storage electrode contact hole. In this case, the storage electrode contact 38 is not formed at the portion where the guard ring storage electrode is to be formed.                     

Next, a first sacrificial insulating film 40 for forming a storage electrode is formed on the entire surface.

2C and 3E, the guard ring storage electrode 320 is formed at the edge of the cell block, the dummy storage electrode 310 is formed therein, and the storage electrode 300 is formed toward the center thereof. A redundancy storage electrode (not shown) may be formed between the guard ring storage electrode 320 and the dummy storage electrode 310, and instead of forming the redundancy storage electrode, the formation of the dummy storage electrode 310 may be omitted. It may be.

The width of the guard ring storage electrode 320 may be the same size as that of the guard ring gate electrode 120 or the guard ring bit line 200, or may be formed differently.

Next, the first sacrificial insulating layer 40 is etched using a storage electrode mask that exposes a predetermined portion of the storage electrode as an etching mask to form a trench that exposes the storage electrode contact 38.

Next, the conductive layer for the storage electrode is formed on the entire surface, and the MPS film 44 is formed on the surface of the conductive layer for the storage electrode.

Next, after the second sacrificial insulating film 46 is formed over the entire surface, the second sacrificial insulating film 46, the MPS film 44, and the storage electrode conductive layer are removed by a CMP process to form a cylindrical storage electrode. To form 42.

Thereafter, the second sacrificial insulating film 46 and the first sacrificial insulating film 40 remaining between the storage electrode 42 and the storage electrode 42 are removed.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. The provision of the electrode contact 50 is shown. In this case, the storage electrode contact 50 is formed on the guard ring gate electrode.

As described above, the method of manufacturing a semiconductor device according to the present invention includes a contact plug, a word line, or a bottom portion of a guarding capacitor formed at an edge of a cell block in a cylindrical storage electrode forming process. In the chemical mechanical polishing process for providing a substructure such as a bit line to separate the storage electrodes, the storage electrodes are collapsed due to the step between the cell region and the peripheral circuit region, or the bridges are caused by the residues generated therefrom. There is an advantage to improve the characteristics and reliability of the semiconductor device by preventing it.

Claims (16)

In the method of manufacturing a semiconductor device to form a guard ring storage electrode on the cell block edge, And forming a lower structure of a guard ring gate electrode and a guard ring bit line at a bottom of the guard ring storage electrode to mitigate a step between a cell region and a peripheral circuit region. The method of claim 1, And a guard ring gate electrode, a dummy gate electrode, a redundancy gate electrode, and a gate electrode are sequentially provided from the edge of the cell block toward the center portion. The method of claim 1, And a guard ring gate electrode, a dummy gate electrode, and a gate electrode are sequentially provided from the edge of the cell block toward the center portion. The method of claim 2, And forming a contact plug between the guard ring gate electrode and the dummy gate electrode. The method of claim 2, The width of the guard ring gate electrode is formed in the same size as the width of the gate electrode manufacturing method of a semiconductor device. The method of claim 2, The width of the guard ring gate electrode is a semiconductor device manufacturing method, characterized in that formed in a different size than the width of the gate electrode. The method of claim 1, And a guard ring bit line, a dummy bit line, a redundancy bit line, and a bit line are sequentially provided from the edge of the cell block toward the center portion. The method of claim 7, wherein And a guard ring bit line, a dummy bit line, and a bit line are sequentially provided from the edge of the cell block toward the center portion. The method of claim 7, wherein And forming a storage electrode contact between the guard ring bit line and the dummy bit line. The method of claim 7, wherein The width of the guard ring bit line is formed in the same size as the width of the bit line. The method of claim 7, wherein The width of the guard ring bit line is formed in a different size than the width of the bit line. The method according to claim 1 or 7, The width of the guard ring bit line is formed in the same size as the width of the guard ring gate electrode. The method according to claim 1 or 7, The width of the guard ring bit line is formed in a different size than the width of the guard ring gate electrode. The method of claim 1, The width of the guard ring storage electrode is a semiconductor device manufacturing method, characterized in that formed to the same size as the width of the guard ring gate electrode or guard ring bit line. The method of claim 1, The width of the guard ring storage electrode is formed to have a size different from the width of the guard ring gate electrode or guard ring bit line. The method of claim 1, And a storage electrode contact in the lower structure is formed on the guard ring gate electrode.

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