KR100307558B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100307558B1 KR100307558B1 KR1019980061933A KR19980061933A KR100307558B1 KR 100307558 B1 KR100307558 B1 KR 100307558B1 KR 1019980061933 A KR1019980061933 A KR 1019980061933A KR 19980061933 A KR19980061933 A KR 19980061933A KR 100307558 B1 KR100307558 B1 KR 100307558B1
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- storage electrode
- contact plug
- forming
- electrode contact
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 238000003860 storage Methods 0.000 claims abstract description 87
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 24
- 238000002955 isolation Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 abstract description 23
- 239000010410 layer Substances 0.000 description 93
- 239000010408 film Substances 0.000 description 56
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 239000011229 interlayer Substances 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000003475 lamination Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 모스전계효과 트랜지스터, 비트라인 콘택플러그 및 제1저장전극 콘택플러그가 형성되어 있는 반도체기판 상부에 상기 비트라인 콘택플러그와 접속되는 비트라인을 형성하되, 상기 비트라인 상부에 식각방지막으로 사용되는 질화막을 형성하고, 상기 구조 상부에 상기 질화막과 식각선택비 차이를 갖는 절연막을 형성한 후, 저장전극 콘택마스크를 이용하여 상기 제1저장전극 콘택플러그를 노출시키는 저장전극 콘택홀을 형성하고, 상기 제1저장전극 콘택플러그와 접속되는 제2저장전극 콘택플러그를 형성한 다음, 상기 제2저장전극 콘택플러그와 접속되는 저장전극을 형성함으로써 별도의 식각방지막을 형성하지 않고 상기 제1저장전극 콘택플러그와 접속되는 제2저장전극 콘택플러그를 형성할 수 있으므로 공정을 단순화시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, wherein a bit line connected to the bit line contact plug is formed on a semiconductor substrate on which a MOS field effect transistor, a bit line contact plug, and a first storage electrode contact plug are formed. After forming a nitride film to be used as an etch stop layer on the bit line, and forming an insulating film having an etch selectivity difference with the nitride film on the structure, the first storage electrode contact plug is exposed using a storage electrode contact mask. Forming a storage electrode contact hole, and forming a second storage electrode contact plug connected to the first storage electrode contact plug, and then forming a storage electrode connected to the second storage electrode contact plug. The second storage electrode contact plug may be formed to be connected to the first storage electrode contact plug without being formed. Therefore, it is a technology to simplify the process and thereby improve the characteristics and reliability of the semiconductor device.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 자기정렬콘택(self aligned contact, SAC) 형성방법으로 제1저장전극 콘택플러그를 형성하고, 그 상부에 다시 자기정렬콘택 형성방법으로 상기 제1저장전극 콘택플러그와 접속되는 제2저장전극 콘택플러그를 형성한 다음, 상기 제2저장전극 콘택플러그와 접속되는 저장전극을 형성하되, 추가되는 식각방지막 없이 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a first storage electrode contact plug is formed by a method of forming a self aligned contact (SAC), and the first storage is formed again by a method of forming a self-aligned contact thereon. The present invention relates to a method of forming a second storage electrode contact plug to be connected to an electrode contact plug, and then forming a storage electrode to be connected to the second storage electrode contact plug, without forming an etch stop layer.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture:NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.
[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선, 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 공정 상의 방법으로는 노광마스크를 위상 반전 마스크를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL이라 함) 방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass: SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resist: 이하 TLR 라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, the micrometer has a limit of about μm, and an exposure apparatus using an ultraviolet ray having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source, or a process As a method of imaging, a method of using a phase inversion mask as an exposure mask and a method of forming a separate thin film on the wafer which can improve image contrast can be used. A tri layer resist method (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers or silicon on a photoresist layer selectively. It has been developed, such as silico-migration method for injection may lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고, 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화, 마스크간의 정합 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have factors such as misalignment tolerance during mask alignment, lens distortion during exposure process, threshold size change during mask fabrication and photolithography process, and matching between masks to maintain gaps. Consider these to form a mask.
그리고, 콘택홀 형성시 리소그래피(lithography)공정의 한계를 극복하기 위하여 자기 정렬 방법으로 콘택홀을 형성하는 자기정렬콘택(self aligned contact, 이하 SAC 라 함)기술이 개발되었다.In order to overcome the limitations of the lithography process in forming the contact holes, a self aligned contact (SAC) technology for forming contact holes by a self alignment method has been developed.
상기 SAC 방법은 식각장벽층으로 사용하는 물질에 따라 다결정실리콘층이나 질화막 또는 산화질화막 등을 사용하는 것으로 나눌 수 있으며, 가장 유망한 것으로 질화막을 식각방어막으로 사용하는 방법이 있다.The SAC method may be divided into a polysilicon layer, a nitride film, or an oxynitride film according to the material used as the etch barrier layer, and the most promising method is to use a nitride film as an etch barrier.
도시되어 있지는 않으나, 종래 반도체소자의 SAC 제조방법에 관하여 살펴보면 다음과 같다.Although not shown, the SAC manufacturing method of the conventional semiconductor device will be described as follows.
먼저, 반도체기판 상에 소정의 하부구조물, 예를 들어 소자분리 절연막과 게이트 절연막, 마스크 산화막 패턴과 중첩되어 있는 게이트 전극 및 소오스/드레인영역 등의 모스 전계효과 트랜지스터(MOS field effect transistor : 이하 MOS FET 라 함) 등을 형성한 후, 상기 구조의 전표면에 식각방지막과 산화막 재질의 층간절연막을 순차적으로 형성한다.First, a MOS field effect transistor (MOS FET) such as a gate electrode and a source / drain region overlapping a predetermined substructure, for example, a device isolation insulating film, a gate insulating film, and a mask oxide film pattern on a semiconductor substrate. And the like, and then sequentially form an etch stop film and an interlayer insulating film made of an oxide film on the entire surface of the structure.
그 다음, 상기 반도체기판에서 저장전극이나 비트라인 등의 콘택으로 예정되어 있는 부분 상의 층간절연막을 노출시키는 감광막 패턴을 형성한 후, 상기 감광막 패턴에 의해 노출되어 있는 층간절연막을 건식식각하여 식각방지막을 노출시키고, 다시 식각방지막을 식각하여 콘택홀을 형성한다.Next, a photoresist pattern is formed on the semiconductor substrate to expose an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact such as a storage electrode or a bit line. Then, the interlayer insulating film exposed by the photosensitive film pattern is dry-etched to form an etch stop layer. It exposes and etches an etch stop layer again, and forms a contact hole.
상기에서 식각방지막을 다결정실리콘층으로 사용하는 경우, 이는 다시 식각방지막을 전면에 형성하는 방법과 콘택홀이 형성될 지역에만 다결정실리콘층 패드를 형성하는 방법으로 나누어지는데, 이러한 다결정실리콘층의 자기정렬콘택형성방법은 산화막과는 다른 식각기구를 가지는 다결정실리콘을 식각방지막으로 사용하므로 산화막과는 높은 식각선택비차를 얻을 수 있으나, 전면 증착 방법은 콘택홀간의 절연 신뢰성이 떨어지고, 패드를 형성하는 방법은 콘택 패드와 반도체기판간의 오정렬 발생시 반도체기판에 손상이 발생되는데, 이를 방지하기 위하여 스페이서 또는 폴리머를 사용하여 콘택 패드를 확장시키는 방법이 제시되고 있으나, 이 역시 0.18㎛ 이하의 디자인룰을 실현할 수 없는 문제점이 있다.When the etch barrier is used as a polysilicon layer, it is divided into a method of forming an etch barrier on the front surface and a method of forming a polysilicon layer pad only in a region where a contact hole is to be formed. Since the contact forming method uses polycrystalline silicon having an etching mechanism different from that of the oxide film as an etch stopper, a high etching selectivity difference can be obtained from the oxide film, but the surface deposition method has a poor insulation reliability between contact holes and a pad forming method. When misalignment occurs between the contact pad and the semiconductor substrate, damage occurs to the semiconductor substrate. To prevent this, a method of expanding the contact pad by using a spacer or a polymer has been proposed, but this also fails to realize a design rule of 0.18 μm or less. There is this.
이하, 도시되어 있지는 않지만 종래기술에 대하여 설명하기로 한다.Hereinafter, although not shown, the prior art will be described.
먼저, 반도체기판의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 산화막을 형성하고, 나머지 반도체기판에 게이트 산화막을 형성한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region. A device isolation oxide film is formed on the portion that is present and a gate oxide film is formed on the remaining semiconductor substrate.
그 다음, 상기 게이트 산화막 상부에 제1마스크 절연막이 적층되어 있는 게이트 전극을 형성하고, 상기 제1마스크 절연막과 게이트 전극의 측벽에 제1절연막 스페이서를 형성한다.Next, a gate electrode in which a first mask insulating layer is stacked is formed on the gate oxide layer, and a first insulating layer spacer is formed on sidewalls of the first mask insulating layer and the gate electrode.
다음, 상기 제1절연막 스페이서 양측 반도체기판에 불순물을 이온주입하여 소오스/드레인영역을 형성한다.Next, impurities are implanted into the semiconductor substrate on both sides of the first insulating layer spacer to form a source / drain region.
그 다음, 상기 구조의 상부에 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분과 접속되는 비트라인 콘택플러그 및 제1저장전극 콘택플러그를 구비하는 제1층간절연막을 형성한다. 다음, 상기 비트라인 콘택플러그와 접속되는 비트라인을 형성하되, 상기 비트라인의 상부에는 제2마스크 절연막이 적층되고, 상기 비트라인과 제2마스크 절연막의 측벽에는 제2절연막 스페이서가 형성된다.Next, a first interlayer insulating film having a bit line contact plug and a first storage electrode contact plug connected to a portion intended as a bit line contact and a storage electrode contact is formed on the structure. Next, a bit line connected to the bit line contact plug is formed, and a second mask insulating layer is stacked on the bit line, and a second insulating layer spacer is formed on sidewalls of the bit line and the second mask insulating layer.
그 다음, 전체표면 상부에 제2층간절연막을 형성하여 평탄화시킨다.Next, a second interlayer insulating film is formed over the entire surface to planarize.
다음, 상기 제2층간절연막 상부에 저장전극 콘택으로 예정되는 부분을 노출시키는 제1감광막 패턴을 형성하고, 상기 제1감광막 패턴을 식각마스크로 사용하여 상기 제2층간절연막을 식각함으로써 상기 제1저장전극 콘택플러그를 노출시키는 제1저장전극 콘택홀을 형성한다.Next, a first photoresist layer pattern is formed on the second interlayer dielectric layer to expose a predetermined portion as a storage electrode contact, and the first interlayer dielectric layer is etched by using the first photoresist layer pattern as an etch mask. A first storage electrode contact hole exposing the electrode contact plug is formed.
그 다음, 상기 제1감광막 패턴을 제거하고, 전체표면 상부에 상기 제1저장전극 콘택홀이 매립되도록 제1도전층을 형성한다.Next, the first photoresist layer pattern is removed, and a first conductive layer is formed to fill the first storage electrode contact hole on the entire surface.
다음, 상기 제1도전층을 전면식각 또는 CMP공정으로 제거하여 제2저장전극 콘택플러그를 형성한다.Next, the first conductive layer is removed by an entire surface etching or CMP process to form a second storage electrode contact plug.
그 다음, 전체표면 상부에 식각방지막을 형성한다.Next, an etch stop layer is formed on the entire surface.
다음, 상기 식각방지막 상부에 반도체기판의 셀영역을 보호하는 제2감광막 패턴을 형성하고, 상기 제2감광막 패턴을 식각마스크로 사용하여 상기 식각방지막을 제거하여 주변회로영역을 노출시킨다. 상기 식각방지막이 반도체기판의 주변회로영역에 남아 있으면 후속 열공정시 크랙(crack)을 유발시켜 금속배선 콘택의 형성공정시 식각정지막으로 작용하여 식각공정이 어려워진다.Next, a second photoresist layer pattern is formed on the etch stop layer to protect the cell region of the semiconductor substrate. The peripheral circuit region is exposed by removing the etch stop layer using the second photoresist pattern as an etch mask. If the etch stop layer remains in the peripheral circuit region of the semiconductor substrate, it causes a crack during the subsequent thermal process, which acts as an etch stop layer during the formation of the metallization contact, making the etch process difficult.
그 다음, 상기 제2감광막 패턴을 제거하고, 전체표면 상부에 제3층간절연막을 형성한다.Next, the second photoresist film pattern is removed, and a third interlayer insulating film is formed over the entire surface.
그리고, 상기 제3층간절연막 상부에 저장전극으로 예정되는 부분을 노출시키는 제3감광막 패턴을 형성한다.A third photoresist pattern is formed on the third interlayer insulating layer to expose a portion of the third interlayer insulating layer.
다음, 상기 제3감광막 패턴을 식각마스크로 사용하여 상기 제3층간절연막 및 식각방지막을 식각하여 상기 제2저장전극 콘택플러그를 노출시키는 제2저장전극 콘택홀을 형성한다.Next, the third interlayer insulating layer and the etch stop layer are etched using the third photoresist pattern as an etch mask to form a second storage electrode contact hole exposing the second storage electrode contact plug.
그 다음, 상기 제3감광막 패턴을 제거하고 상기 구조 전표면에 상기 제2저장전극 콘택플러그와 접속되는 제2도전층을 소정 두께 형성한다.Next, the third photoresist layer pattern is removed, and a second thickness of the second conductive layer connected to the second storage electrode contact plug is formed on the entire surface of the structure.
다음, 상기 제2도전층 상부에 제4층간절연막을 형성하여 평탄화시킨다.Next, a fourth interlayer insulating film is formed on the second conductive layer and planarized.
그 다음, 상기 제4층간절연막과 제2도전층을 전면식각 또는 CMP공정으로 제거하여 상기 제2도전층의 상부를 분리시킨다.Thereafter, the fourth interlayer insulating film and the second conductive layer are removed by an entire surface etching or CMP process to separate the upper portion of the second conductive layer.
그 후, 상기 제4층간절연막 및 제3층간절연막을 제거하여 상기 제2도전층을 노출시킴으로써 실린더형 저장전극을 형성한다.Thereafter, the fourth interlayer insulating film and the third interlayer insulating film are removed to expose the second conductive layer to form a cylindrical storage electrode.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 반도체소자가 고집적화되어 감에 따라서 셀영역이 점점 작아지고, 충분한 정전용량의 확보를 위해 콘택플러그를 형성한 다음, 상기 콘택플러그와 접속되는 저장전극을 형성하는 방법으로 저장전극의 표면적을 증가시키는 방법을 사용하였다. 그러나, 상기와 같은 방법은 저장전극간의 절연특성이 우수하지만, 하부의 비트라인과의 절연을 위하여 자기정렬방법의 선택적 식각을 하는데 어려움이 있고, 상기 비트라인 주위의 절연막층이 모두 드러나게 되어 전반적으로 구조가 불안정하여 상기 콘택플러그 상부에 또 다른 콘택플러그를 형성한 다음, 저장전극을 형성하는 방법을 사용하였다. 상기와 같이 또 다른 콘택플러그를 형성하기 위해서는 별도의 식각방지막을 사용되고, 상기 식각방지막에 의해서 공정의 수가 많이 증가하는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, as the semiconductor device becomes more integrated, the cell area becomes smaller and smaller, and the contact plug is formed to secure sufficient capacitance, and then the storage plug is connected to the contact plug. As a method of forming the electrode, a method of increasing the surface area of the storage electrode was used. However, the above method is excellent in insulating properties between storage electrodes, but it is difficult to selectively etch the self-aligning method to insulate the lower bit lines, and the insulating film layers around the bit lines are exposed. Since the structure was unstable, another contact plug was formed on the contact plug, and then a storage electrode was used. In order to form another contact plug as described above, a separate etch barrier layer is used, and the number of processes increases by the etch barrier layer.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 소정의 하부구조물이 형성되어 있는 반도체기판 상부에 비트라인 콘택플러그, 제1저장전극 콘택플러그가 구비되어 있는 제1절연막을 형성하고, 상기 비트라인콘택플러그와 접속되는 비트라인을 형성한 다음, 상기 비트라인 상부에 식각방지막으로 질화막을 형성한 후, 상기 질화막과 식각선택비차이를 갖는 절연막으로 평탄화시키고, 저장전극 콘택으로 예정되는 부분을 식각하여 상기 제1저장전극 콘택플러그를 노출시킨 다음, 상기 제1저장전극 콘택플러그와 접속되는 제2저장전극 콘택플러그를 형성한 다음, 상기 제2저장전극 콘택플러그와 접속되는 저장전극을 형성함으로써 상기 제2저장전극 콘택플러그를 형성하기 위한 별도의 식각방지막 없이 공정을 실시하여 공정을 단순화시키고 그에 따른 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.According to an aspect of the present invention, in order to solve the problems of the related art, a bit line contact plug and a first storage electrode contact plug are formed on a semiconductor substrate on which a predetermined substructure is formed. After forming a bit line connected to the line contact plug, a nitride film is formed as an etch stop layer on the bit line, and then planarized with an insulating film having an etching selectivity difference with the nitride film, and the portion intended to be a storage electrode contact is etched. Exposing the first storage electrode contact plug to form a second storage electrode contact plug connected to the first storage electrode contact plug, and then forming a storage electrode connected to the second storage electrode contact plug. Simplify the process by performing the process without a separate etch barrier to form the second storage electrode contact plug. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the process yield and the reliability of device operation.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체기판 13 : 제1절연막11: semiconductor substrate 13: first insulating film
15 : 저장전극 콘택플러그 17 : 제2절연막15: storage electrode contact plug 17: second insulating film
19 : 제1도전층 21 : 제3절연막19: first conductive layer 21: third insulating film
23a : 제4절연막 23b : 제4절연막 스페이서23a: fourth insulating film 23b: fourth insulating film spacer
25 : 제5절연막 27 : 제6절연막25: fifth insulating film 27: sixth insulating film
29 : 제2도전층 31 : 제7절연막29: second conductive layer 31: seventh insulating film
33 : 감광막 패턴 35 : 제3도전층33: photosensitive film pattern 35: third conductive layer
37 : 제8절연막37: eighth insulating film
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
소자분리절연막, 모스전계효과 트랜지스터가 형성되어 있는 반도체기판 상부에 비트라인 콘택플러그 및 제1저장전극 콘택플러그가 구비된 제1절연막을 형성하는 공정과,Forming a first insulating film including a bit line contact plug and a first storage electrode contact plug on the semiconductor substrate on which the device isolation insulating film and the MOS field effect transistor are formed;
상기 비트라인 콘택플러그와 접속되는 비트라인을 형성하되, 상기 비트라인 상부에 제2절연막을 형성하는 공정과,Forming a bit line connected to the bit line contact plug, and forming a second insulating layer on the bit line;
전체표면 상부에 식각방지막으로 사용되는 제3절연막을 형성한 다음, 상기 반도체기판의 셀부를 보호하는 셀마스크를 식각마스크로 사용하여 상기 제3절연막을 전면식각하는 공정과,Forming a third insulating layer to be used as an etch stop layer on the entire surface, and then etching the entire surface of the third insulating layer using a cell mask protecting the cell portion of the semiconductor substrate as an etch mask;
상기 제3절연막 상부에 상기 제3절연막과 식각선택비차이를 갖는 제4절연막과 제5절연막을 형성하는 공정과,Forming a fourth insulating film and a fifth insulating film on the third insulating film, the fourth insulating film having an etching selectivity difference with the third insulating film, and
저장전극 콘택마스크를 사용하여 상기 제5, 제4, 제3절연막을 식각하여 상기 제1저장전극 콘택플러그를 노출시키는 저장전극 콘택홀을 형성하는 공정과,Forming a storage electrode contact hole to expose the first storage electrode contact plug by etching the fifth, fourth, and third insulating layers using a storage electrode contact mask;
상기 제1저장전극 콘택플러그와 접속되는 제2저장전극 콘택플러그를 형성하는 공정과,Forming a second storage electrode contact plug connected to the first storage electrode contact plug;
전체표면 상부에 저장전극으로 예정되는 부분을 노출시키되, 상기 제2저장전극 콘택플러그를 노출시키는 제6절연막을 형성하는 공정과,Forming a sixth insulating layer exposing a portion intended as a storage electrode on the entire surface, and exposing the second storage electrode contact plug;
상기 제6절연막 상부에 저장전극용 도전층을 형성한 다음, 제7절연막을 형성하여 평탄화시키는 공정과,Forming a conductive layer for a storage electrode on the sixth insulating layer, and then forming a seventh insulating layer to planarize the insulating layer;
상기 제7절연막 및 저장전극용 도전층을 전면식각하여 상기 저장전극용 도전층의 상부를 분리시키는 공정과,Etching an entire surface of the seventh insulating layer and the storage electrode conductive layer to separate an upper portion of the conductive layer for the storage electrode;
상기 제7절연막의 소정 두께를 제거하는 공정을 포함하는 것을 특징으로 한다.And removing a predetermined thickness of the seventh insulating film.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(11)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판(11)에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 산화막(도시안됨)을 형성한 다음, 게이트 전극(도시안됨) 및 소오스/드레인영역(도시안됨)으로 구성되는 모스전계효과 트랜지스터를 형성한 다음, 상기 구조 전표면에 제1절연막(13)을 형성하여 평탄화시킨다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region. After forming a device isolation oxide film (not shown) on the portion intended as the device isolation region, forming a MOS field effect transistor consisting of a gate electrode (not shown) and a source / drain region (not shown), and then The first insulating film 13 is formed on the entire surface of the structure and planarized.
그 다음, 상기 소오스/드레인영역에서 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분 상의 제1절연막(13)을 식각하여 비트라인 콘택홀 및 제1저장전극 콘택홀을 형성한다.Next, the first insulating layer 13 on the portion of the source / drain region, which is supposed to be a bit line contact and a storage electrode contact, is etched to form a bit line contact hole and a first storage electrode contact hole.
다음, 상기 구조 전표면에 제1도전층을 형성한 후, 전면식각 또는 CMP공정을 실시하여 상기 비트라인 콘택홀 및 제1저장전극 콘택홀을 매립하는 비트라인 콘택플러그(도시안됨) 및 제1저장전극 콘택플러그(15)를 형성한다.Next, after the first conductive layer is formed on the entire surface of the structure, a bit line contact plug (not shown) and a first hole for filling the bit line contact hole and the first storage electrode contact hole are formed by performing an entire surface etching or CMP process. The storage electrode contact plug 15 is formed.
그 다음, 상기 구조 전표면에 제2절연막(17), 제2도전층(19) 및 제3절연막(21)의 적층구조를 순차적으로 형성하고, 비트라인 마스크를 이용하여 상기 적층구조를 식각하여 상기 비트라인 콘택플러그와 접속되는 비트라인을 형성한다. 이때, 상기 제3절연막(21)은 질화막으로 형성한다.Subsequently, a lamination structure of the second insulating layer 17, the second conductive layer 19, and the third insulating layer 21 is sequentially formed on the entire surface of the structure, and the lamination structure is etched using a bit line mask. A bit line connected to the bit line contact plug is formed. In this case, the third insulating film 21 is formed of a nitride film.
그 다음, 전체표면 상부에 식각방지막으로 사용되는 제4절연막(23a)을 질화막으로 형성하고, 상기 반도체기판(11)의 셀영역(Ⅰ)을 보호하는 셀마스크를 식각마스크로 사용하여 상기 제4절연막(23a)을 전면식각하여 상기 반도체기판(11)의 주변회로영역(Ⅱ) 상의 적층구조 측벽에 제4절연막 스페이서(23b)를 형성한다. (도 1참조)Next, a fourth insulating layer 23a, which is used as an etch stop layer, is formed on the entire surface of the nitride layer, and a cell mask protecting the cell region I of the semiconductor substrate 11 is used as an etch mask. A fourth insulating film spacer 23b is formed on the sidewalls of the stacked structure on the peripheral circuit region II of the semiconductor substrate 11 by etching the entire surface of the insulating film 23a. (See Fig. 1)
다음, 전체표면 상부에 상기 제4절연막(23a)과 식각선택비 차이를 갖는 제5절연막(25)을 형성한 후, 전면식각공정을 실시한다. 이때, 상기 제5절연막(25)은 상기 주변회로영역(Ⅱ) 상의 제4절연막 스페이서(23b)의 양측벽에 스페이서 형태로 형성된다.Next, after forming the fifth insulating layer 25 having the difference in etching selectivity from the fourth insulating layer 23a on the entire surface, the entire surface etching process is performed. In this case, the fifth insulating layer 25 is formed on both sidewalls of the fourth insulating layer spacer 23b on the peripheral circuit region II.
그 다음, 전체표면 상부에 제6절연막(27)을 형성하고 CMP공정을 실시하여 평탄화시킨다. (도 2참조)Next, a sixth insulating film 27 is formed over the entire surface and planarized by performing a CMP process. (See Fig. 2)
그 후, 상기 셀영역(Ⅰ)에서 저장전극 콘택으로 예정되는 부분을 노출시키는 저장전극 콘택마스크를 식각마스크로 사용하여 상기 제6절연막(27), 제5절연막(25) 및 제4절연막(23a)을 식각하여 상기 제1저장전극 콘택플러그(15)를 노출시키는 제2저장전극 콘택홀(도시안됨)을 형성한다.Subsequently, the sixth insulating layer 27, the fifth insulating layer 25, and the fourth insulating layer 23a are formed by using a storage electrode contact mask that exposes a portion of the cell region I as a storage electrode contact as an etch mask. ) Is formed to form a second storage electrode contact hole (not shown) that exposes the first storage electrode contact plug 15.
다음, 전체표면 상부에 상기 저장전극 콘택홀을 매립하는 제3도전층(29)을 형성한다. (도 3참조)Next, a third conductive layer 29 filling the storage electrode contact hole is formed on the entire surface. (See Fig. 3)
그 다음, 상기 제3도전층(29)을 전면식각공정으로 제거하여 상기 제1저장전극 콘택플러그(15)와 접속되는 제2저장전극 콘택플러그를 형성한다.Next, the third conductive layer 29 is removed by an entire surface etching process to form a second storage electrode contact plug connected to the first storage electrode contact plug 15.
다음, 전체표면 상부에 제7절연막(31)을 형성하여 평탄화시킨다.Next, a seventh insulating layer 31 is formed on the entire surface to be planarized.
그 다음, 상기 제7절연막(31) 상부에 상기 셀영역(Ⅰ)에서 저장전극으로 예정되는 부분을 노출시키는 감광막 패턴(33)을 형성한다. (도 4참조)Subsequently, a photoresist pattern 33 is formed on the seventh insulating layer 31 to expose a portion of the cell region I as a storage electrode. (See Fig. 4)
다음, 상기 감광막 패턴(33)을 식각마스크로 사용하여 상기 제7절연막(31)과 제6절연막(27)을 제거하되, 상기 제2저장전극 콘택플러그와 식각선택비차이를 이용하여 제거하여 상기 제2저장전극 콘택플러그를 노출시킨 후, 상기 감광막 패턴(33)을 제거한다.Next, the seventh insulating layer 31 and the sixth insulating layer 27 are removed using the photoresist pattern 33 as an etching mask, and the second storage electrode contact plug is removed using an etching selectivity difference. After exposing the second storage electrode contact plug, the photoresist pattern 33 is removed.
그 다음, 전체표면 상부에 상기 제2저장전극 콘택플러그와 접속되는 제4도전층(35)을 형성한다.Next, a fourth conductive layer 35 connected to the second storage electrode contact plug is formed on the entire surface.
그 후, 상기 제4도전층(35) 상부에 제8절연막(37)을 형성하여 평탄화시킨다. (도 5참조)Thereafter, an eighth insulating layer 37 is formed on the fourth conductive layer 35 to be planarized. (See Fig. 5)
다음, 상기 제8절연막(37)과 제4도전층(35)을 전면식각공정으로 제거하여 상기 셀영역(Ⅰ) 상의 제4도전층(35)의 상부를 분리시킨다.Next, the eighth insulating layer 37 and the fourth conductive layer 35 are removed by an entire surface etching process to separate the upper portion of the fourth conductive layer 35 on the cell region I.
그 다음, 상기 제4도전층(35)과의 식각선택비차이를 이용하여 상기 제7절연막(31)을 습식식각방법으로 소정 두께 제거하여 실린더형 저장전극을 형성한다. (도 6참조)Next, the seventh insulating layer 31 is removed by a wet etching method using a difference in etching selectivity from the fourth conductive layer 35 to form a cylindrical storage electrode. (See FIG. 6)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 모스전계효과 트랜지스터, 비트라인 콘택플러그 및 제1저장전극 콘택플러그가 형성되어 있는 반도체기판 상부에 상기 비트라인 콘택플러그와 접속되는 비트라인을 형성하되, 상기 비트라인 상부에 식각방지막으로 사용되는 질화막을 형성하고, 상기 구조 상부에 상기 질화막과 식각선택비차이를 갖는 절연막을 형성한 후, 저장전극 콘택마스크를 이용하여 상기 제1저장전극 콘택플러그를 노출시키는 저장전극 콘택홀을 형성하고, 상기 제1저장전극 콘택플러그와 접속되는 제2저장전극 콘택플러그를 형성한 다음, 상기 제2저장전극 콘택플러그와 접속되는 저장전극을 형성함으로써 별도의 식각방지막을 형성하지 않고 상기 제1저장전극 콘택플러그와 접속되는 제2저장전극 콘택플러그를 형성할 수 있으므로 공정을 단순화시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention includes a bit line connected to the bit line contact plug on an upper side of a semiconductor substrate on which a MOS field effect transistor, a bit line contact plug, and a first storage electrode contact plug are formed. A nitride film to be used as an etch stop layer on the bit line, an insulating film having an etching selectivity difference with the nitride film on the structure, and a first storage electrode using a storage electrode contact mask. Forming a storage electrode contact hole exposing the contact plug, forming a second storage electrode contact plug connected to the first storage electrode contact plug, and then forming a storage electrode connected to the second storage electrode contact plug. A second storage electrode contactle connected to the first storage electrode contact plug without forming an etch stop layer It can be formed him there is an advantage to simplify the process and improve the characteristics and reliability of the semiconductor device thereof.
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| KR101055211B1 (en) * | 2007-07-11 | 2011-08-08 | 엘지디스플레이 주식회사 | Manufacturing method of liquid crystal display device |
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| KR100669928B1 (en) * | 1999-10-27 | 2007-01-17 | 후지쯔 가부시끼가이샤 | Semiconductor device and manufacturing the same |
| KR101055211B1 (en) * | 2007-07-11 | 2011-08-08 | 엘지디스플레이 주식회사 | Manufacturing method of liquid crystal display device |
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