KR100465604B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100465604B1
KR100465604B1 KR1019970081321A KR19970081321A KR100465604B1 KR 100465604 B1 KR100465604 B1 KR 100465604B1 KR 1019970081321 A KR1019970081321 A KR 1019970081321A KR 19970081321 A KR19970081321 A KR 19970081321A KR 100465604 B1 KR100465604 B1 KR 100465604B1
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insulating layer
insulating film
film
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forming
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KR19990061067A (en
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이석주
김진배
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material

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Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판에 게이트 전극을 형성하고, 전면에 질화막을 형성한 다음, 하드 마스크(hard mask) 역할을 하는 산화막을 형성하고, 그를 이용하여 상기 질화막을 패터닝함으로써 게이트 전극과 비트라인 또는 전하저장전극 간에 서로 쇼트(short)되어 누설전류가 발생하는 것을 방지하고, 콘택의 공정 마진을 향상시켜 소자의 수율을 높이고, 제조 원가를 절감하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, wherein a gate electrode is formed on a semiconductor substrate, a nitride film is formed on the entire surface, an oxide film serving as a hard mask is formed, and the nitride film is patterned using the same. Accordingly, the present invention relates to a technology for preventing leakage current from being shorted between the gate electrode and the bit line or the charge storage electrode, increasing the process margin of the contact, increasing the yield of the device, and reducing the manufacturing cost.

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 게이트 전극과 콘택간의 단락을 방지하기 위하여 상기 게이트 전극의 상부 및 양측면에 질화막 패턴을 형성하고, 상기 질화막 패턴과 식각선택비를 갖는 산화막 스페이서를 상기 질화막 패턴의 양측벽에 형성함으로써 소자간의 공정 마진을 향상시키고, 그에 따른 소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly, in order to prevent a short circuit between a gate electrode and a contact, a nitride film pattern is formed on both sides of the gate electrode, and an oxide spacer having an etching selectivity with the nitride film pattern is formed. By forming on both side walls of the nitride film pattern relates to a technique for improving the process margin between devices, thereby improving the characteristics and reliability of the device.

최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광장치의 렌즈 구경(numerical aperture : NA, 개구수) 에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[ R = k * λ / NA , R = 해상도, λ = 광원의 파장, NA = 개구수 ][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]

여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365 ㎚ 인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5 ㎛ 정도가 한계이다. 그리고, 0.5 ㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet, DUV), 예를 들어 파장이 248 ㎚ 인 KrF 레이저나 193 ㎚ 인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL 이라 함)방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass : SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resister : 이하 TLR 이라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. About μm is the limit. In order to form a fine pattern of 0.5 µm or less, an exposure apparatus using a deep ultra violet (DUV), for example, a KrF laser having a wavelength of 248 nm or an ArF laser having 193 nm as a light source, is used. The method and the contrast enhancement layer (hereinafter referred to as CEL) method for forming a separate thin film on the wafer which can improve the image contrast or the S.O. Tri-layer resister (hereinafter referred to as TLR) method with an intermediate layer such as on glass (SOG) or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주요 배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고 엄격한 정렬이 요구되어 공정 여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size and spacing between the main wiring as the device is highly integrated, and the aspect ratio, which is a ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lensdistortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration) 등과 같은 요인들을 고려하여 마스크를 형성한다. These contact holes provide misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, and matching between masks to maintain spacing. The mask is formed by considering factors such as registration.

이하, 종래의 기술에 따른 반도체소자의 제조방법에 대해 설명하기로 한다. Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described.

먼저, 반도체기판에 소자분리막을 형성하고, 노출된 반도체기판의 상부에 게이트 산화막과 다결정실리콘층을 적층한 다음, 패턴닝 공정으로 상기 다결정실리콘층과 게이트 산화막을 식각하여 게이트 전극을 형성한다.First, a device isolation layer is formed on a semiconductor substrate, a gate oxide layer and a polysilicon layer are stacked on the exposed semiconductor substrate, and the polysilicon layer and the gate oxide layer are etched by a patterning process to form a gate electrode.

다음, 상기 게이트 전극의 양측의 반도체기판에 소오스/드레인을 형성한다. 여기서, 상기 소오스/드레인을 엘.디.디.(lightly doped drain, 이하 LDD 라함)구조로 형성할 수도 있으며, 이를 위해서는 게이트 전극 패터닝후 저농도 불순물을 주입하면 된다.Next, a source / drain is formed on the semiconductor substrates on both sides of the gate electrode. The source / drain may be formed of a lightly doped drain (LDD) structure. For this purpose, a low concentration of impurities may be injected after the gate electrode patterning.

그 다음, 상기 게이트 전극의 양측벽에 스페이서를 형성하고, 전표면 상부에 층간절연막을 형성하여 평탄화시킨다.Next, spacers are formed on both sidewalls of the gate electrode, and an interlayer insulating film is formed on the entire surface to be planarized.

그리고, 반도체기판에서 콘택으로 예정된 부분 상의 층간절연막을 제거하여 콘택홀을 형성하고, 상기 반도체기판과 접속되는 콘택을 형성한다.Then, a contact hole is formed by removing the interlayer insulating film on the portion of the semiconductor substrate, which is supposed to be a contact, to form a contact connected to the semiconductor substrate.

그러나, 상기와 같은 종래기술에 따른 반도체소자의 제조방법은, 반도체소자가 점차 고집적화되어 감에 따라 게이트 전극과 비트라인 또는 전하저장전극 간의 간격이 좁아져서, 콘택 형성공정시 오배열(misalign)으로 인해 누설전류가 흘러 소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.However, in the method of manufacturing a semiconductor device according to the related art as described above, as the semiconductor device becomes more and more highly integrated, the gap between the gate electrode and the bit line or the charge storage electrode becomes narrow, resulting in misalignment during the contact forming process. Due to the leakage current flows there is a problem to lower the characteristics and reliability of the device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 콘택 형성공정시 오배열로 인하여 게이트 전극과 비트라인 또는 전하저장전극 간에 단락이 되어 누설전류가 발생하는 것을 방지함으로써 소자의 리프레쉬 특성을 향상시키고, 그에 따른 소자의 수율 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention improves the refresh characteristics of the device by preventing a short circuit between the gate electrode and the bit line or the charge storage electrode due to the misalignment during the contact forming process to prevent the leakage current occurs. Another object of the present invention is to provide a method of manufacturing a semiconductor device, which improves the yield and reliability of the device.

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

반도체기판 상부에 게이트 전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate;

상기 게이트 전극 양측 반도체기판의 소오스/드레인 영역을 형성하는 공정과,Forming a source / drain region of the semiconductor substrate on both sides of the gate electrode;

상기 구조 상부에 제1절연막을 형성하는 공정과,Forming a first insulating film on the structure;

상기 제1절연막 상부에 상기 제1절연막과 식각선택비를 갖는 제2절연막을 형성하는 공정과,Forming a second insulating film having an etch selectivity with the first insulating film on the first insulating film;

상기 제2절연막을 게이트 전극용 마스크를 사용하여 패터닝하여 상기 게이트 전극 상부에 제2절연막 패턴을 형성하는 공정과,Forming a second insulating layer pattern on the gate electrode by patterning the second insulating layer using a mask for a gate electrode;

상기 구조 상부에 제3절연막을 형성하는 공정과,Forming a third insulating film on the structure;

상기 제3절연막을 전면식각하여 제2절연막 패턴 및 제1절연막의 측벽에 제3절연막 스페이서를 형성하는 공정과,Forming a third insulating film spacer on the sidewalls of the second insulating film pattern and the first insulating film by etching the third insulating film over the entire surface thereof;

상기 제2절연막 패턴 및 제3절연막 스페이서를 식각마스크로 반도체기판의 활성영역 상부의 제1절연막을 식각하여 제1절연막 패턴을 형성하는 공정과,Etching the first insulating layer over the active region of the semiconductor substrate using the second insulating pattern and the third insulating layer spacer as an etch mask to form a first insulating layer pattern;

상기 제2절연막 패턴 및 제3절연막 스페이서를 제거하는 공정과,Removing the second insulating pattern and the third insulating layer spacer;

상기 제1절연막 패턴의 양측벽에 제4절연막 스페이서를 형성하는 공정과,Forming fourth insulating film spacers on both side walls of the first insulating film pattern;

상기 구조 상부에 콘택홀을 구비하는 층간절연막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming an interlayer insulating film having a contact hole on the structure.

이하, 첨부된 도면을 참고로 하여 본 발명에 따른 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.

도 1 내지 도 8 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 8 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention.

먼저, 반도체기판(11)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판(11)에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 산화막(도시안됨)을 형성하고, 상기 구조 전표면에 게이트 절연막(12)을 형성한 다음, 전면에 게이트 전극용 도전층을 형성한다. 이때, 상기 게이트 전극용 도전층은 다결정실리콘층 또는 폴리사이드막을 사용한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region. A device isolation oxide film (not shown) is formed on the portion intended as the device isolation region, a gate insulating film 12 is formed on the entire surface of the structure, and then a conductive layer for the gate electrode is formed over the entire surface. In this case, a polysilicon layer or a polyside film is used as the gate electrode conductive layer.

다음, 게이트 전극용 마스크를 이용하여 상기 게이트 전극용 도전층을 식각하여 게이트 전극(13)을 형성한다. Next, the gate electrode conductive layer is etched using a gate electrode mask to form the gate electrode 13.

그 다음, 상기 게이트 전극(13) 양측의 반도체기판(11)에 소오스/드레인(도시안됨)을 형성한다. Next, a source / drain (not shown) is formed on the semiconductor substrate 11 on both sides of the gate electrode 13.

다음, 상기 구조 상부에 제1절연막(15)을 전면적으로 형성한다. 여기서 제1절연막은 질화막으로 형성한다. (도 1참조)Next, the first insulating layer 15 is formed over the entire structure. The first insulating film is formed of a nitride film. (See Fig. 1)

그 다음, 상기 제1절연막(15) 상부에 제2절연막(17)을 형성한 후 게이트 전극용 마스크를 사용하여 상기 제2절연막(17)을 패터닝한다.Next, after forming the second insulating layer 17 on the first insulating layer 15, the second insulating layer 17 is patterned by using a gate electrode mask.

다음, 상기 구조 상부에 제3절연막(19)을 전면적으로 형성한다. 여기서, 상기 제2절연막(17) 및 제3절연막(19)은 제1절연막(15)과 식각선택비를 갖는 중온산화막(middle temperature oxide, 이하 MTO 라 함), 고온산화막(high temperature oxide, 이하 HTO 라 함), 엘.피.-테오스(low pressure tetra ethyl ortho silicate glass, 이하 LP-TEOS 라 함) 또는 피.이.-테오스(plasma enhanced tetra ethyl ortho silicate glass, 이하 PE-TEOS 라 함)등을 사용하여 형성한다. (도 2참조)Next, a third insulating film 19 is formed over the entire structure. The second insulating layer 17 and the third insulating layer 19 may include a middle temperature oxide (hereinafter referred to as MTO) and an high temperature oxide layer having an etching selectivity with the first insulating layer 15. HTO), L.P.-Theos (low pressure tetra ethyl ortho silicate glass, hereinafter LP-TEOS) or P.-Theos (plasma enhanced tetra ethyl ortho silicate glass, hereinafter PE-TEOS To form). (See Fig. 2)

그 다음, 상기 제3절연막(19)을 전면식각하여 상기 제2절연막(17) 패턴 및 제1절연막(15)의 측벽에 제3절연막(19) 스페이서를 형성한다. (도 3참조)Next, the third insulating layer 19 is etched entirely to form a third insulating layer 19 spacer on sidewalls of the second insulating layer 17 pattern and the first insulating layer 15. (See Fig. 3)

다음, 상기 제2절연막(17) 패턴 및 제3절연막(19) 스페이서를 하드(hard) 마스크로 사용하여 상기 제1절연막(15)을 식각하여 제1절연막(15) 패턴을 형성한 후, 상기 제2절연막(17) 패턴 및 제3절연막(19) 스페이서를 제거한다.Next, the first insulating layer 15 is etched using the second insulating layer 17 pattern and the third insulating layer 19 spacer as a hard mask to form a first insulating layer 15 pattern. The second insulating layer 17 pattern and the third insulating layer 19 spacer are removed.

그 다음, 상기 구조 상부에 제4절연막(21)을 형성한다. (도 4참조)Next, a fourth insulating film 21 is formed on the structure. (See Fig. 4)

또한, 상기 제3절연막(19) 스페이서가 얇게 형성될 경우 상기 제1절연막(15)을 식각한 후, 노출되는 반도체기판(11)의 넓이가 커진다.In addition, when the spacer of the third insulating layer 19 is thin, the width of the exposed semiconductor substrate 11 is increased after etching the first insulating layer 15.

다음, 상기 제4절연막(21)을 전면식각하여 상기 제1절연막(15) 패턴의 양 측벽에 제4절연막(21) 스페이서를 형성한다. (도 5참조)Next, the fourth insulating layer 21 is etched entirely to form spacers of the fourth insulating layer 21 on both sidewalls of the pattern of the first insulating layer 15. (See Fig. 5)

그 다음, 상기 구조 상부에 층간절연막(23)을 형성하여 평탄화시키고, 콘택으로 예정된 부분을 노출시키는 감광막 패턴(25)을 형성한다. 이때, 상기 층간절연막(23)은 비.피.에스.지.(boro phospho silicate glass, 이하 BPSG 라함)과 같이 스텝커버리지가 우수한 절연막을 사용한다. (도 6참조)Next, an interlayer insulating film 23 is formed on the structure and planarized to form a photosensitive film pattern 25 exposing a predetermined portion as a contact. In this case, the interlayer insulating layer 23 uses an insulating film having excellent step coverage, such as boro phospho silicate glass (hereinafter referred to as BPSG). (See FIG. 6)

그리고, 상기 감광막 패턴(25)을 식각마스크로 사용하여 상기 층간절연막(23)을 식각하여 콘택홀을 형성한다. (도 7참조)The interlayer insulating layer 23 is etched using the photoresist pattern 25 as an etching mask to form a contact hole. (See Fig. 7)

그 후, 상기 구조 상부에 도전층(27)을 형성하여 상기 콘택홀을 통해 콘택으로 예정되어 있는 반도체기판(11)과 접속되는 콘택을 형성한다. (도 8참조)Thereafter, a conductive layer 27 is formed on the structure to form a contact that is connected to the semiconductor substrate 11, which is supposed to be a contact, through the contact hole. (See FIG. 8)

본 발명에 따른 반도체소자의 제조방법은, 반도체기판에 게이트 전극을 형성하고, 전면에 질화막을 형성한 다음, 하드 마스크(hard mask) 역할을 하는 산화막을 형성하고, 그를 이용하여 상기 질화막을 패터닝함으로써 게이트 전극과 비트라인 또는 전하저장전극 간에 서로 쇼트(short)되어 누설전류가 발생하는 것을 방지하고, 콘택의 공정 마진을 향상시켜 소자의 수율을 높이고, 제조 원가를 절감하는 이점이 있다. In the method of manufacturing a semiconductor device according to the present invention, a gate electrode is formed on a semiconductor substrate, a nitride film is formed on the entire surface, an oxide film serving as a hard mask is formed, and the nitride film is patterned using the same. The short between the gate electrode and the bit line or the charge storage electrode prevents leakage current, and improves the process margin of the contact to increase the yield of the device and reduce the manufacturing cost.

도 1 내지 도 8 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 8 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.

<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>

11 : 반도체기판 12 : 게이트 절연막11 semiconductor substrate 12 gate insulating film

13 : 게이트 전극 15 : 제1절연막13 gate electrode 15 first insulating film

17 : 제2절연막 19 : 제3절연막17: second insulating film 19: third insulating film

21 : 제4절연막 23 : 층간절연막21: fourth insulating film 23: interlayer insulating film

5 : 감광막 패턴 27 : 도전층5: photosensitive film pattern 27: conductive layer

Claims (6)

반도체기판 상부에 게이트 전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate; 상기 게이트 전극 양측 반도체기판의 소오스/드레인 영역을 형성하는 공정과,Forming a source / drain region of the semiconductor substrate on both sides of the gate electrode; 상기 구조 상부에 제1절연막을 형성하는 공정과,Forming a first insulating film on the structure; 상기 제1절연막 상부에 상기 제1절연막과 식각선택비를 갖는 제2절연막을 형성하는 공정과,Forming a second insulating film having an etch selectivity with the first insulating film on the first insulating film; 상기 제2절연막을 게이트 전극용 마스크를 사용하여 패터닝하여 상기 게이트 전극 상부에 제2절연막 패턴을 형성하는 공정과,Forming a second insulating layer pattern on the gate electrode by patterning the second insulating layer using a mask for a gate electrode; 상기 구조 상부에 제3절연막을 형성하는 공정과,Forming a third insulating film on the structure; 상기 제3절연막을 전면식각하여 제2절연막 패턴 및 제1절연막의 측벽에 제3절연막 스페이서를 형성하는 공정과,Forming a third insulating film spacer on the sidewalls of the second insulating film pattern and the first insulating film by etching the third insulating film over the entire surface thereof; 상기 제2절연막 패턴 및 제3절연막 스페이서를 식각마스크로 반도체기판의 활성영역 상부의 제1절연막을 식각하여 제1절연막 패턴을 형성하는 공정과,Etching the first insulating layer over the active region of the semiconductor substrate using the second insulating pattern and the third insulating layer spacer as an etch mask to form a first insulating layer pattern; 상기 제2절연막 패턴 및 제3절연막 스페이서를 제거하는 공정과,Removing the second insulating pattern and the third insulating layer spacer; 상기 제1절연막 패턴의 양측벽에 제4절연막 스페이서를 형성하는 공정과,Forming fourth insulating film spacers on both side walls of the first insulating film pattern; 상기 구조 상부에 콘택홀을 구비하는 층간절연막을 형성하는 공정을 포함하는 반도체소자의 제조방법.Forming an interlayer insulating film having a contact hole on the structure. 제 1 항에 있어서,The method of claim 1, 상기 게이트 전극은 다결정실리콘막 또는 폴리사이드막을 사용하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The gate electrode is a semiconductor device manufacturing method, characterized in that formed using a polysilicon film or a polyside film. 제 1 항에 있어서,The method of claim 1, 상기 제1절연막은 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.And the first insulating film is formed of a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 제2절연막과 제3절연막은 상기 제1절연막과 식각선택비를 갖는 MTO, HTO, LP-TEOS 또는 PE-TEOS와 같은 산화막으로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.And the second insulating layer and the third insulating layer are formed of an oxide film such as MTO, HTO, LP-TEOS, or PE-TEOS having an etching selectivity with the first insulating layer. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막은 스텝 커버리지가 우수한 BPSG 막을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.The interlayer insulating film is a manufacturing method of a semiconductor device, characterized in that for using a BPSG film excellent in step coverage. 제 1 항에 있어서,The method of claim 1, 상기 제2절연막 패턴 및 제3절연막 스페이서를 하드 마스크로 사용함으로써 상기 제1절연막을 건식식각하는 것을 특징으로 하는 반도체소자의 제조방법.And etching the first insulating layer by using the second insulating layer pattern and the third insulating layer spacer as a hard mask.
KR1019970081321A 1997-12-31 1997-12-31 Manufacturing method of semiconductor device KR100465604B1 (en)

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KR970008353B1 (en) * 1992-10-13 1997-05-23 Hyundai Electronics Ind Micro-contact formation of vlsi semiconductor elements
KR950010852A (en) * 1993-10-18 1995-05-15 이헌조 dish washer
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KR960026245A (en) * 1994-12-31 1996-07-22 김광호 Polyside Contact and Formation Method
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