KR19990061141A - Contact manufacturing method of semiconductor device - Google Patents
Contact manufacturing method of semiconductor device Download PDFInfo
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- KR19990061141A KR19990061141A KR1019970081395A KR19970081395A KR19990061141A KR 19990061141 A KR19990061141 A KR 19990061141A KR 1019970081395 A KR1019970081395 A KR 1019970081395A KR 19970081395 A KR19970081395 A KR 19970081395A KR 19990061141 A KR19990061141 A KR 19990061141A
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- forming
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- contact plug
- charge storage
- bit line
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000003860 storage Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 39
- 239000010410 layer Substances 0.000 description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 콘택 제조방법에 관한 것으로, 비트라인 콘택 및 전하저장전극 콘택으로 예정되는 부분에 반도체기판과 접촉되는 비트라인 콘택 플러그 및 전하저장전극 콘택 플러그를 형성하고, 상기 비트라인 콘택 플러그 및 전하저장전극 콘택 플러그의 양측벽에 절연막 스페이서를 형성하여 워드라인과의 단차를 형성함으로써 좁은 면적 내의 인접한 워드라인과 공정 마진을 확보하여 비트라인 콘택 및 전하저장전극 콘택 형성시 오배열이 발생해도 상기 워드라인과 단락되는 것을 방지하여 소자의 전기적 특성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device, wherein a bit line contact plug and a charge storage electrode contact plug in contact with a semiconductor substrate are formed at portions defined as bit line contacts and charge storage electrode contacts, and the bit line contact plugs are provided. And insulating film spacers on both side walls of the charge storage electrode contact plug to form a step with the word line, thereby securing process margins with adjacent word lines in a narrow area, even when misalignment occurs during bit line contact and charge storage electrode contact formation. It is a technology to prevent the short circuit with the word line to improve the electrical characteristics of the device and thereby high integration of the semiconductor device.
Description
본 발명은 반도체소자의 콘택 제조방법에 관한 것으로, 특히 고집적 소자의 제조 공정에서 전하저장전극 콘택과 비트라인 콘택 형성시 반도체기판에 접촉되는 전하저장전극 콘택 플러그 및 비트라인 콘택 플러그를 형성한 다음, 질화막으로 스페이서를 형성함으로써 상기 전하저장전극 콘택 및 비트라인 콘택을 형성할 때 오배열(misalign)으로 인하여 워드라인과 단락되는 것을 방지하는 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다.The present invention relates to a method for manufacturing a contact of a semiconductor device, and in particular, in the manufacturing process of a highly integrated device, after forming a charge storage electrode contact and a bit line contact, the charge storage electrode contact plug and the bit line contact plug are in contact with the semiconductor substrate. The present invention relates to a technology for enabling high integration of a semiconductor device, which prevents a short circuit from a word line due to misalignment when forming the charge storage electrode contact and the bit line contact by forming a spacer with a nitride film.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture:NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.
[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선, 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 공정 상의 방법으로는 노광마스크를 위상 반전 마스크를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL이라 함) 방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass: SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resist: 이하 TLR 라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, the micrometer has a limit of about μm, and an exposure apparatus using an ultraviolet ray having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source, or a process As a method of imaging, a method of using a phase inversion mask as an exposure mask and a method of forming a separate thin film on the wafer which can improve image contrast can be used. A tri layer resist method (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers or silicon on a photoresist layer selectively. It has been developed, such as silico-migration method for injection may lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고, 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화, 마스크간의 정합 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have factors such as misalignment tolerance during mask alignment, lens distortion during exposure process, threshold size change during mask fabrication and photolithography process, and matching between masks to maintain gaps. Consider these to form a mask.
종래 기술에 따른 반도체소자의 콘택 제조방법에 관하여 살펴보면 다음과 같다.Looking at the contact manufacturing method of the semiconductor device according to the prior art as follows.
먼저, 반도체기판의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 산화막을 형성하고, 나머지 반도체기판에 게이트 산화막과 제1다결정실리콘층, 실리사이드막 및 마스크 절연막을 순차적으로 형성한 후, 게이트전극 패턴닝 마스크를 사용하여 마스크 절연막과 실리사이드막 및 제1다결정실리콘층을 순차적으로 식각하여 제1다결정실리콘층 패턴과 실리사이드막 패턴으로된 게이트전극과 그 상부에 적층되어 있는 마스크 절연막 패턴을 형성한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region. A device isolation oxide film is formed on the portion of the semiconductor substrate, and the gate oxide film, the first polysilicon layer, the silicide film, and the mask insulating film are sequentially formed on the remaining semiconductor substrate, and then the mask insulating film and the silicide film and The first polysilicon layer is sequentially etched to form a gate electrode of the first polysilicon layer pattern and the silicide layer pattern and a mask insulating layer pattern stacked thereon.
그 다음, 상기 게이트전극 양측의 반도체기판에 엘.디.디.(lightly doped drain : LDD) 영역이 되는 저농도 불순물층을 형성한 후, 상기 제1다결정실리콘층 패턴과 실리사이드막 패턴 및 마스크 절연막 패턴의 측벽에 CVD 방법으로 산화막을 전면도포 및 전면 이방성 식각하여 절연 스페이서를 형성한다.Next, after forming a low concentration impurity layer serving as a lightly doped drain (LDD) region on the semiconductor substrates on both sides of the gate electrode, the first polysilicon layer pattern, the silicide layer pattern, and the mask insulation layer pattern The oxide film is front-coated and anisotropically etched on the sidewalls of the oxide film to form an insulating spacer.
그 후, 상기 스페이서 양측의 반도체기판에 고농도 불순물영역을 형성하고, 상기 구조의 전표면에 제2다결정실리콘층을 형성한다.Thereafter, a high concentration impurity region is formed in the semiconductor substrates on both sides of the spacer, and a second polycrystalline silicon layer is formed on the entire surface of the structure.
그 다음, 상기 소자분리 산화막이나 마스크 절연막 상의 제2다결정실리콘층을 사진식각하여 제거함으로써 반도체기판의 상부에만 남도록한 후에 상기 구조의 전표면에 층간절연막을 형성한다.Then, the second polysilicon layer on the device isolation oxide film or mask insulating film is removed by photolithography so as to remain only on the upper portion of the semiconductor substrate, and then an interlayer insulating film is formed on the entire surface of the structure.
이어서, 상기 반도체기판에서 콘택으로 예정되어 있는 부분상의 층간절연막을 제거하여 비트선 콘택홀과 전하저장전극 콘택홀을 형성하되, 상기 제2다결정실리콘층 패턴이 식각장벽층이 되고, 노출되는 제2다결정실리콘층을 제거하고, 상기 콘택홀의 측벽에 절연을 위한 절연 스페이서를 형성한후, 상기 콘택홀을 메우는 비트선과 전하저장전극을 형성한다.Subsequently, a bit line contact hole and a charge storage electrode contact hole are formed by removing an interlayer insulating layer on a portion of the semiconductor substrate, which is intended to be a contact, wherein the second polysilicon layer pattern becomes an etch barrier layer and is exposed. After removing the polysilicon layer, forming insulating spacers for insulation on the sidewalls of the contact holes, and forming bit lines and charge storage electrodes filling the contact holes.
상기와 같이 종래기술에 따른 반도체소자의 콘택 제조방법은, 워드라인과 워드라인 사이의 간격이 계속 좁아지는 고집적화에 따라 그 사이에 콘택을 형성하기 위한 공정마진이 감소되어, 비트라인 콘택 및 전하저장전극 콘택 형성 콘택 형성 공정시 오배열로 인하여 인접한 워드라인과 단락되어 후속 공정에 영향을 미치고, 공정수율 및 소자동작의 신뢰성을 떨어드리는 문제점이 있다.As described above, the contact manufacturing method of a semiconductor device according to the related art has a process margin for forming a contact therebetween as the integration between word lines and word lines continues to be narrowed, thereby reducing bit line contact and charge storage. Electrode contact formation There is a problem that short-circuit with adjacent word lines due to misalignment during the contact formation process affects subsequent processes and degrades process yield and device operation reliability.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 비트라인 콘택 플러그 및 전하저장전극 콘택 플러그를 형성한 다음, 워드라인에 절연막 스페이서를 형성하여 단차를 형성함으로써 비트라인 콘택 및 전하저장전극 콘택을 형성할 때, 상기 워드라인과의 단락을 방지하여 후속 공정을 용이하게 하고, 소자의 신뢰성 및 제조수율을 향상시키는 반도체소자의 콘택 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the bit line contact plug and the charge storage electrode contact plug are formed, and then the insulating film spacer is formed on the word line to form the step, thereby forming the bit line contact and the charge storage electrode contact. When forming, it is an object of the present invention to provide a method for manufacturing a contact of a semiconductor device which prevents a short circuit with the word line to facilitate a subsequent process and improves the reliability and manufacturing yield of the device.
도 1 내지 도 4 은 본 발명에 따른 반도체소자의 콘택 제조방법을 도시한 단면도.1 to 4 are cross-sectional views showing a contact manufacturing method of a semiconductor device according to the present invention.
◈ 도면의 주요부분에 대한 부호의 설명◈ Explanation of symbols for the main parts of the drawings
11 : 반도체기판 12 : 게이트 절연막11 semiconductor substrate 12 gate insulating film
13 : 게이트 전극 14 : 마스크 절연막 패턴13 gate electrode 14 mask insulating film pattern
15 : 제1절연막 17 : 제1평탄화막15: first insulating film 17: first flattening film
19a : 비트라인 콘택 플러그 19b : 전하저장전극 콘택 플러그19a: bit line contact plug 19b: charge storage electrode contact plug
21 : 제2절연막 23 : 제2평탄화막21: second insulating film 23: second planarization film
25 : 비트라인 27 : 제3평탄화막25 bit line 27 third planarization film
29 : 전하저장전극 콘택홀29: charge storage electrode contact hole
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 콘택 제조방법은,Contact manufacturing method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상에 마스크 절연막 패턴이 적층되어 있는 게이트 전극의 측벽에 제1절연막 스페이서가 형성되어 있는 모스 전계효과 트랜지스터를 형성하는 공정과,Forming a MOS field effect transistor having a first insulating film spacer formed on a sidewall of a gate electrode on which a mask insulating film pattern is stacked on a semiconductor substrate;
상기 구조를 평탄화하는 제1평탄화막을 형성하는 공정과,Forming a first planarization film to planarize the structure;
상기 게이트 전극의 양측에 콘택으로 예정되는 부분보다 넓은 부분을 노출시키는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on both sides of the gate electrode to expose a portion wider than a portion intended to be a contact;
상기 감광막 패턴을 식각마스크로 사용하여 상기 제1평탄화막을 제거하여 콘택홀을 형성하는 공정과,Forming a contact hole by removing the first planarization layer by using the photoresist pattern as an etching mask;
상기 콘택홀을 매립하는 동시에 상기 제1평탄화막보다 높은 단차를 갖는 콘택 플러그를 형성하는 공정과,Filling the contact hole and simultaneously forming a contact plug having a step height higher than that of the first planarization film;
상기 콘택 플러그의 단차부분에 제2절연막 스페이서를 형성하는 공정과,Forming a second insulating film spacer on a stepped portion of the contact plug;
상기 구조 상부에 제2평탄화막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a second planarization film on the structure.
이하, 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1 내지 도 4 은 본 발명에 따른 반도체소자의 콘택 제조방법을 도시한 단면도이다.1 to 4 are cross-sectional views illustrating a method for manufacturing a contact of a semiconductor device according to the present invention.
먼저, 반도체기판(11)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판(11)에 소자분리 절연막(도시안됨), 게이트 절연막(12)을 형성하고, 상부에 마스크 절연막 패턴(14)이 적층되어 있는 게이트 전극(13)이 형성되어 있는 모스 전계효과 트랜지스터를 형성한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the semiconductor substrate 11. A device isolation insulating film (not shown) and a gate insulating film 12 are formed, and a MOS field effect transistor having a gate electrode 13 having a mask insulating film pattern 14 stacked thereon is formed.
다음, 상기 마스크 절연막 패턴(14)과 게이트 전극(13)의 측벽에 제1절연막(15)을 형성하고, 전표면에 제1평탄화막(17)을 형성한다. 상기 제1절연막(15)과 제1평탄화막(17)은 산화막을 사용하여 형성한다.Next, a first insulating layer 15 is formed on sidewalls of the mask insulating layer pattern 14 and the gate electrode 13, and a first planarization layer 17 is formed on the entire surface. The first insulating film 15 and the first planarization film 17 are formed using an oxide film.
그 다음, 상기 반도체기판(11)의 비트라인 콘택 및 전하저장전극 콘택으로 예정된 부분보다 넓은 부분을 노출시키는 콘택홀을 형성하고, 그 상부에 제1도전층을 형성한다.Next, a contact hole exposing a wider portion than the predetermined portion is formed in the bit line contact and the charge storage electrode contact of the semiconductor substrate 11, and a first conductive layer is formed thereon.
그리고, 상기 제1도전층 상부에 비트라인 콘택 플러그 및 전하저장전극 콘택 플러그로 예정된 부분을 보호하는 감광막 패턴(도시안됨)을 형성하고, 그를 사용하여 상기 제1도전층을 식각하여 비트라인 콘택 플러그(19a) 및 전하저장전극 콘택 플러그(19b)를 형성한다. (도 1참조)Then, a photoresist pattern (not shown) is formed on the first conductive layer to protect a portion defined by the bit line contact plug and the charge storage electrode contact plug, and the first conductive layer is etched using the bit line contact plug. 19a and the charge storage electrode contact plug 19b are formed. (See Fig. 1)
다음, 상기 구조 상부에 제2절연막(21)을 형성한 다음, 상기 비트라인 콘택 플러그(19a) 및 전하저장전극 콘택 플러그(19b)가 노출될 때까지 전면식각을 실시하여 상기 비트라인 콘택 플러그(19a) 및 전하저장전극 콘택 플러그(19b)의 양측벽에 제2절연막(21) 스페이서를 형성한다. 여기서, 상기 제2절연막(21)은 질화막으로 형성한다. (도 2, 도 3참조)Next, a second insulating layer 21 is formed on the structure, and then the entire surface is etched until the bit line contact plug 19a and the charge storage electrode contact plug 19b are exposed, thereby performing the bit line contact plug ( 19a) and spacers of the second insulating layer 21 are formed on both sidewalls of the charge storage electrode contact plug 19b. The second insulating film 21 is formed of a nitride film. (See Figs. 2 and 3)
그 다음, 상기 구조를 평탄화하는 제2평탄화막(23)을 형성한 다음, 화학적 기계적 연막(chemical mechanical polishing, 이하 CMP 라 함)공정을 실시한다. 상기 제2평탄화막은 비.피.에스.지.(boro phospho silicate glass, 이하 BPSG 라함) 또는 피.에스.지.(phospho silicate glass, 이하 PSG 라 함)를 사용하여 형성한다.Next, a second planarization film 23 is formed to planarize the structure, and then a chemical mechanical polishing (hereinafter referred to as CMP) process is performed. The second planarization film is formed using B.P.G. (hereinafter referred to as BPSG) or P.G. (phospho silicate glass, referred to as PSG).
다음, 상기 비트라인 콘택 플러그(19a) 상의 제2평탄화막(23)을 제거하여 비트라인 콘택 플러그(19a)와 접촉되는 비트라인(25)을 형성한다.Next, the second planarization layer 23 on the bit line contact plug 19a is removed to form the bit line 25 in contact with the bit line contact plug 19a.
그후, 상기 구조의 전표면에 제3평탄화막(27)을 BPSG 또는 PSG 를 사용하여 형성하고, 전하저장전극 콘택 플러그(19b)상의 제2평탄화막(23) 및 제3평탄화막(27)을 순차적으로 제거하여 전하저장전극 콘택홀(29)을 형성한다. (도 4참조)Thereafter, the third planarization film 27 is formed on the entire surface of the structure using BPSG or PSG, and the second planarization film 23 and the third planarization film 27 on the charge storage electrode contact plug 19b are formed. By sequentially removing the charge storage electrode contact hole 29 is formed. (See Fig. 4)
그리고, 상기 전하저장전극 콘택홀(29)을 매립하고 상기 전하저장전극 콘택 플러그(19b)와 접촉되는 전하저장전극(도시안됨)을 형성한다.The charge storage electrode contact hole 29 is buried and a charge storage electrode (not shown) in contact with the charge storage electrode contact plug 19b is formed.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 콘택 제조방법은, 비트라인 콘택 및 전하저장전극 콘택으로 예정되는 부분에 반도체기판과 접촉되는 비트라인 콘택 플러그 및 전하저장전극 콘택 플러그를 형성하고, 상기 비트라인 콘택 플러그 및 전하저장전극 콘택 플러그의 양측벽에 절연막 스페이서를 형성하여 워드라인과의 단차를 형성함으로써 좁은 면적 내의 인접한 워드라인과 공정 마진을 확보하여 비트라인 콘택 및 전하저장전극 콘택 형성시 오배열이 발생해도 상기 워드라인과 단락되는 것을 방지하여 소자의 전기적 특성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, the method for manufacturing a semiconductor device contact according to the present invention includes forming a bit line contact plug and a charge storage electrode contact plug in contact with a semiconductor substrate at a portion designated as a bit line contact and a charge storage electrode contact. Bit line contact plugs and charge storage electrode contact insulating layer spacers are formed on both side walls of the plug to form a step with the word lines to secure bit margins and adjacent word lines in a narrow area to form bit line contacts and charge storage electrode contacts. Even if the arrangement occurs, short circuits with the word lines are prevented, thereby improving the electrical characteristics of the device and consequently enabling high integration of the semiconductor device.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970081395A KR19990061141A (en) | 1997-12-31 | 1997-12-31 | Contact manufacturing method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970081395A KR19990061141A (en) | 1997-12-31 | 1997-12-31 | Contact manufacturing method of semiconductor device |
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| KR19990061141A true KR19990061141A (en) | 1999-07-26 |
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- 1997-12-31 KR KR1019970081395A patent/KR19990061141A/en not_active Application Discontinuation
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