KR100345368B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising a bit line and a bit line formed on an upper surface of a semiconductor substrate including a cell region and a peripheral circuit region including a silicon on insulator (SOI) structure having a trench capacitor. Bar-bitline is formed, but each metal layer is formed to overlap the bit line and the bar-bit line in the layout of the cell area so that the layout area can be reduced, and the trench type capacitor is applied. The device isolation process can be performed at the same time, which simplifies the process and reduces the step difference between the cell region and the peripheral circuit region, and improves the refresh characteristics by reducing the leakage current in the cell region by applying a substrate of SOI structure. .

Description

Manufacturing method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a capacitor using a trench is formed on a silicon on insulator (SOI) substrate, and then bit lines and bar-bit lines are formed of different metal layers. A method for manufacturing a semiconductor device.

The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength? And the process variable k of the light source of the reduced exposure apparatus, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 435 nm and 365 nm have a process resolution of about 0.75 and 0.5 μm, respectively. In order to form a fine pattern of 0.5 μm or less, an exposure apparatus using a small-ultraviolet ray, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source, or As a method, a phase inversion mask is used as an exposure mask, a contrast enhancement layer method for forming a separate thin film on the wafer which can improve image contrast, or a two-layer photoresist film. .Tri layer resist method through intermediate layer such as spin on glass (SOG) or silylation method to selectively inject silicon into the upper side of photosensitive film. Has been developed to lower the resolution limit.

In the method of manufacturing a semiconductor device according to the prior art as described above, after forming a bit line using a tungsten silicide or a polycrystalline silicon layer, four bit lines are bundled and connected to each other using a second metal wiring with one Yi. In this case, the second metal wiring is patterned using an ultraviolet ray reticle as the exposure mask and an i-line as the light source. At this time, the bit line and the bar bit line were connected at the same step using the same metal wiring. In the above case, when the patterning is performed using the i line, the space margin between the bit lines is limited.

In order to solve the above-mentioned problems of the related art, a device isolation process using a trench is performed in a peripheral circuit portion of a semiconductor substrate, and a capacitor is formed in a cell portion and an SOI type substrate is formed to form a transistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device, by forming a bit line and a bar bit line using different metal wires, thereby securing a process margin and thereby enabling high integration of the semiconductor device.

1 to 9 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.

10 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

11: semiconductor substrate 13: n well

14: p well 15: pad oxide film

17 nitride film 19 first photosensitive film pattern

21: trench for storage electrode 22: trench for device isolation

23: device isolation insulating film 25: second photosensitive film pattern

27 dielectric film 29 first conductive layer

30: storage electrode 31: third photosensitive film pattern

32: first interlayer insulating film 33: fourth photosensitive film pattern

35: second conductive layer 36: fifth photosensitive film pattern

37 low concentration impurity region 38 gate electrode

39: mask insulating film pattern 41: high concentration impurity region

42 insulating film spacer 45 second interlayer insulating film

47: second metal wiring contact hole 49, 200: first metal wiring

100: word line 300: second metal wiring

400: bit line contact 500: active area

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

Forming a well by forming a well in each of the cell portion and the peripheral circuit portion of the semiconductor substrate, and etching a portion of the peripheral circuit portion, which is intended as an isolation region, and a portion of the cell portion, which is intended as a storage electrode;

Forming a device isolation insulating film filling the trench of the peripheral circuit portion, forming a dielectric film on the surface of the cell portion, and then forming a storage electrode filling the trench of the cell portion;

Forming a first interlayer insulating film having a contact hole exposing the storage electrode on an entire surface thereof;

Forming an undoped polysilicon layer over the entire surface and connected to the storage electrode through the contact hole;

Etching the undoped polysilicon layer and the first interlayer insulating film to form an SOI substrate in the cell portion;

Forming a MOS transistor on the SOI substrate of the cell portion and the peripheral circuit portion;

Forming a second interlayer insulating film having a contact hole exposing a portion of the peripheral circuit portion to be a first metal wiring and a portion of the cell portion to be a bit line on an entire surface thereof;

Forming a bit line and a first metal wiring to fill the contact hole;

Forming a third interlayer insulating film having a contact hole exposing a portion of the cell portion, which is intended for the second metal wiring, and a portion of the peripheral circuit portion, for the bar bit line, over the entire surface;

And forming a second metal wire and a bar bit line to fill the contact hole.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, wells are formed in desired portions on the cell portion I and the peripheral circuit portion II of the p-type semiconductor substrate 11. In this case, n well 13 is formed in the cell part I, and n well or p well 14 is formed in the peripheral circuit part II.

Next, the pad oxide film 15 and the nitride film 17 are sequentially formed on the entire surface, and the storage electrode in the cell portion I and the portion scheduled as the device isolation region in the peripheral circuit portion II on the nitride film 17. The first photosensitive film pattern 19 is formed to expose a predetermined portion. (See Figure 1)

Next, the nitride layer 17, the pad oxide layer 15, and the semiconductor substrate 11 are removed using the first photoresist layer pattern 19 as an etching mask to remove the storage electrode trenches 21 and the isolation trenches. 22).

Next, the first photoresist layer pattern 19, the nitride layer 17, and the pad oxide layer 15 may be removed, and the trench may be formed on the etching surface of the trench to remove defects in the etching surface of the trench during the process of forming the trench. A sacrificial oxide film (not shown) is formed and then removed. (See Figure 2)

Next, an isolation layer (not shown) is formed over the entire surface, and the isolation layer trench 21 and the isolation layer 22 are buried by removing the isolation layer through a front etching process. The insulating film for device isolation of a predetermined thickness remains on the trench.

Thereafter, a second photosensitive film pattern 25 exposing the cell portion I is formed over the entire surface.

Next, using the second photoresist layer pattern 25 as an etching mask, all the insulating film for device isolation is removed on the cell portion I. (See Figure 3)

Next, the second photoresist layer pattern 25 is removed, and a dielectric layer 27 is formed on the entire surface.

Next, the first conductive layer 29 is formed on the entire surface.

Next, a third photoresist pattern 31 is formed on the entire surface to protect a portion intended as the storage electrode, and the third photoresist pattern 31 is formed to protect the trench 21 for the storage electrode. (See Figure 4)

Next, the first conductive layer 29 is etched using the third photoresist pattern 31 as an etching mask to form the storage electrode 30, and then the third photoresist pattern 31 is removed. In this case, the storage electrode 30 is formed to protrude. Here, the n well 13 formed in the cell portion I is used as the plate electrode. (See Figure 5)

Next, a first interlayer insulating film 32 is formed over the entire surface.

Next, a fourth photoresist pattern 33 is formed on the first interlayer insulating layer 32 to expose the storage electrode 30. (See Figure 6)

Next, the first interlayer insulating layer 32 is etched using the fourth photoresist pattern 33 as an etching mask to expose the storage electrode 30, and then the fourth photoresist pattern 33 is removed. .

Thereafter, a second conductive layer 35 is formed on the entire surface, and the second conductive layer 35 is formed of an undoped polysilicon layer and connected to the exposed storage electrode 30.

Next, a fifth photoresist pattern 36 is formed on the second conductive layer 35 to expose a portion of the cell part I to be an active region. (See Figure 7)

Next, the second conductive layer 35 and the first interlayer insulating layer 32 are etched using the fifth photoresist pattern 36 as an etch mask to form a SOI semiconductor substrate. The semiconductor substrate of the SOI structure can be driven at a low voltage of 1.8V or less, and has a low leakage current and thus a strong refresh characteristic.

Next, a gate insulating film (not shown) is formed over the entire surface, the conductive layer for the gate electrode and the mask insulating film are sequentially formed, and then the gate in which the mask insulating film pattern 39 is stacked by an etching process using the gate electrode mask. Electrode 38 is formed.

Next, a low concentration of impurities are ion-implanted on both sides of the gate electrode 38 to form a source / drain region that becomes the low concentration impurity region 37.

Thereafter, an insulating film spacer 42 is formed on sidewalls of the stacked structure of the gate electrode 38 and the mask insulating film pattern 39, and the insulating film spacer 42 formed on the sidewalls of the gate electrode 38 on the peripheral circuit part II. A high concentration impurity region 41 is formed by ion implantation of high concentration impurities on both sides. (See Figure 8)

Next, a second interlayer insulating film 45 is formed over the entire surface. The second interlayer insulating film 45 is formed using B. P. G. (BPSG), and then planarized by performing a flow process. In this case, the second interlayer insulating layer 45 has a function of an isolation layer in the cell unit.

Next, a first predetermined portion of the n-well 13, which is a plate electrode of the capacitor of the cell region I, and a first portion of the peripheral circuit region II, which exposes the portion intended for the first metal wiring. The second interlayer insulating layer 45 is etched using a metal wiring contact mask as an etch mask to form a first metal wiring contact hole (not shown). In this case, the first metal wiring contact mask also exposes a portion of the cell region, which is intended as a bit line.

Next, a first metal layer is formed on the entire surface, and the first metal layer is etched using the first metal wiring mask as an etching mask to form the first metal wiring 49 and the bit line.

Next, the third interlayer dielectric layer and the second interlayer dielectric layer 45 are etched using a third interlayer dielectric layer (not shown) as an etch mask on the entire surface of the second metal interconnection contact hole. Form 47. In this case, the second metal wiring contact mask exposes a portion of the cell region I to be a bar bit line.

Next, a second metal layer is formed on the entire surface, and the second metal layer is etched using the second metal wiring mask as an etch mask to form a second metal wiring and a bar bit line.

10 is a plan view illustrating a method of manufacturing a semiconductor device in accordance with the present invention. The word line 100 is provided in a cell region, and the active region 500 is provided at both sides of the word line 100. The first metal wire 200 and the second metal wire 300 are provided in a direction perpendicular to the word line 100. At this time, both edges of the active region 500 are provided with trench capacitors, and a center portion is provided with a bit line contact 400.

The first metal wire 200 and the second metal wire 300 may overlap each other in layout.

As described above, the method of manufacturing a semiconductor device according to the present invention includes a bit line and a bar bit line on an upper portion of a semiconductor substrate including a cell region and a peripheral circuit region including a SOI structure semiconductor substrate including a trench capacitor. Form a different metal layer, and overlap the bit line and the bar bit line in the layout of the cell area to reduce the layout area, secure the space margin, and perform the process with the i-line; The device separation process can be carried out simultaneously by applying a type capacitor, which simplifies the process and reduces the step difference between the cell region and the peripheral circuit region, and also reduces the leakage current in the cell region by applying the SOI-structured substrate. There is an advantage to improve.

Claims (3)

Forming a well by forming a well in each of the cell portion and the peripheral circuit portion of the semiconductor substrate, and etching a portion of the peripheral circuit portion, which is intended as an isolation region, and a portion of the cell portion, which is intended as a storage electrode; Forming a device isolation insulating film filling the trench of the peripheral circuit portion, forming a dielectric film on the surface of the cell portion, and then forming a storage electrode filling the trench of the cell portion; Forming a first interlayer insulating film having a contact hole exposing the storage electrode on an entire surface thereof; Forming an undoped polysilicon layer over the entire surface and connected to the storage electrode through the contact hole; Etching the undoped polysilicon layer and the first interlayer insulating film to form an SOI substrate in the cell portion; Forming a MOS transistor on the SOI substrate of the cell portion and the peripheral circuit portion; Forming a second interlayer insulating film having a contact hole exposing a portion of the peripheral circuit portion to be a first metal wiring and a portion of the cell portion to be a bit line on an entire surface thereof; Forming a bit line and a first metal wiring to fill the contact hole; Forming a third interlayer insulating film having a contact hole exposing a portion of the cell portion, which is intended for the second metal wiring, and a portion of the peripheral circuit portion, for the bar bit line, over the entire surface; And forming a second metal wire and a bar bit line to fill the contact hole. The method of claim 1, The well formed in the cell portion is a semiconductor device manufacturing method, characterized in that used as a plate electrode. The method of claim 1, And the bit line and the bar bit line are designed to overlap each other when laid out.