KR20000043205A - Method for forming contact hole of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided which prevents an active region from being damaged during an etching process and thus improves the characteristics and the reliability of the device. CONSTITUTION: In case of forming a power line contact or a bit line contact in a peripheral circuit part, a mask insulation film or a barrier insulation film on top of a gate electrode or on top of a bit line is removed and then an etching process to form a contact hole is performed in order to prevent an active region from being damaged during the etching process. A contact hole(20) is formed by removing a barrier insulation film(16) and a mask insulation film on the active region and an anti-reflective film on top of a bit line and a gate electrode, after removing the barrier insulation film and a buffered oxide(15) on top of the gate electrode or bit line formed on the peripheral circuit part. The method includes the processes of: forming an inter level insulation film on top of the whole surface; forming a planarization film(18); forming a photoresist pattern revealing an active region on top of the planarization film and a part where a contact is to be formed; etching the planarization film on the active region and the planarization film and the mask insulation film on the gate electrode; and forming a contact hole by removing the inter level insulation film on the active region and the anti-reflective film on the gate insulation film, and then removing the photoresist pattern.

Description

Contact hole formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, when a power line contact or a bit line contact is formed in an active region, a gate electrode, or a bit line in a peripheral circuit portion, the contact hole is formed on the gate electrode and a bit line. The present invention relates to a method for forming a contact hole in a semiconductor device, by first removing the insulating layer to prevent damage to the active region during the contact hole forming process, thereby improving characteristics and yield of the semiconductor device.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure is limited using a deep ultra violet (DUV) light, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a multi-layered structure because the size of the contact hole and the distance between the peripheral wirings decrease as the device becomes highly integrated, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. In the highly integrated semiconductor device having the conductive wiring, there is a problem that the process margin is reduced because the accurate and strict alignment between the masks in the manufacturing process is required to form the contact, so that the conductive wiring is connected to each other and the process margin is increased. In order to form a contact plug.

In addition, an oxynitride film was used as an antireflection film and a mask insulating film on the gate electrode or the bit line to prevent short between the devices and to facilitate the mask operation. In particular, since the oxynitride film has different material characteristics from the oxide film, which is a general planarization film, in the peripheral circuit portion having a low level, the oxynitride film acts as a barrier during the contact etching process, causing a failing contact that does not open.

In order to prevent this, first, the planarization layer is removed and then the mask insulation layer and the anti-reflection layer are removed. In this case, the oxide layer on the active region having the high etch selectivity is removed first during the one-step etching process. Subsequent bit line and metallization contact characteristics have high resistance, large bit leakage occurs due to large junction leakage current, and final yield after package is reduced. There is this.

In order to solve the above-described problems of the related art, the barrier layer or mask insulating layer of the active region, the upper portion of the gate electrode, or the upper portion of the bit line is removed when the power line contact or the bit line contact is formed in the peripheral circuit portion having a low level difference. Next, the present invention provides a method for forming a contact hole in a semiconductor device which prevents damage to the active region during the etching process and improves characteristics and reliability of the semiconductor device by performing an etching process for forming a contact hole. There is this.

1A to 1G are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

2A to 2C are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to a third embodiment of the present invention.

<Description of Signs of Major Parts of Drawings>

11, 31, 51: semiconductor substrate 12,, 32, 52: gate electrode

13, 33, 53, 59: antireflection film 14, 34, 54, 60: mask insulating film

15, 35, 55: buffer oxide film 16, 36, 56: barrier insulating film

17: photosensitive film pattern 18, 37: planarization film

19, 38, 62: contact mask 20, 63: contact hole

57 first planarization film 58 conductive layer for bit line

61: second flattening film

In order to achieve the above object, the contact hole forming method of the semiconductor device according to the present invention,

Forming an interlayer insulating film over the entire surface to expose the peripheral circuit portion over the semiconductor substrate on which the anti-reflection film and the mask insulating film are stacked;

Forming a planarization film over the entire surface;

Forming a photoresist pattern on the planarization layer exposing an active region and a portion of the gate electrode to be contacted;

Etching the planarization film on the active region, the planarization film and the mask insulating film on the gate electrode using the photoresist pattern as an etching mask;

And forming a contact hole by removing the interlayer insulating film on the active region and the anti-reflection film on the gate insulating film using the photoresist pattern as an etching mask, and then removing the photoresist pattern.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the semiconductor substrate 11 An element isolation insulating film (not shown) is formed on the portion intended as the element isolation region.

Next, a gate insulating film (not shown) is formed over the entire surface, and a stacked structure of the conductive layer 12 for the gate electrode, the antireflection film 13, and the mask insulating film 14 is formed on the gate insulating film. In this case, the anti-reflection film 13 is formed of an oxy nitride layer, and the mask insulating film 14 is formed of an oxide film. (See FIG. 1A)

Next, a gate electrode conductive layer 12 pattern, an antireflection film 13 pattern, and a mask insulating film 14 pattern are formed by an etching process using a gate electrode mask (not shown). (See FIG. 1B)

Next, the buffer oxide film 15 and the barrier nitride film 16 are sequentially formed on the entire surface. The buffer oxide film 15 is formed to buffer stresses generated when the barrier insulating film 16 is directly formed on the semiconductor substrate 11, and the barrier insulating film 16 is used to perform a self-aligned contact process. Form. (See FIG. 1C)

Next, a photoresist pattern 17 is formed on the barrier insulating layer 16 to expose the peripheral circuit portion of the semiconductor substrate 11, and the barrier insulating layer 16 and the photoresist pattern 17 are used as an etching mask. The buffer oxide film 15 is removed. Here, the barrier insulating layer 16 and the buffer oxide layer 15 on the gate electrode formed in the peripheral circuit unit are removed by the etching process, thereby exposing the mask insulating layer 14 on the gate electrode. (See FIG. 1D)

Next, the photoresist layer pattern 17 is removed, a first planarization layer 18 is formed on the entire surface, and a portion of the first planarization layer 18 is formed as a bit line contact or a metal wiring contact. A contact mask 19 is formed to expose the gap. At this time, the barrier insulating film 16 and the buffer oxide film 15 of the portion where the bit line contact or the metal wiring contact are formed on the active region are left. (See Figure 1E)

Thereafter, using the contact mask 19 as an etch mask, the first planarization film 18 in the cell region is removed, and the first planarization film 18 on the peripheral circuit portion and the mask insulating film 14 on the gate electrode. Remove it. (See FIG. 1F)

Then, using the contact mask 19 as an etching mask, the barrier insulating film 16 and the buffer oxide film 15 of the cell portion of the semiconductor substrate 11 are removed, and the anti-reflection film 13 on the gate electrode on the peripheral circuit portion is removed. To form a contact hole 20. (See Figure 1g)

Looking at the second embodiment of the present invention.

2A to 2C are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to a second embodiment of the present invention. After the processes of FIGS. 1A to 1D have been performed, the photoresist pattern is removed, and the upper surface of the entire surface is removed. The planarization film 37 is formed.

Next, a contact mask 38 is formed on the planarization layer 37 to expose a portion of the bit line contact plug and the metal wiring contact plug.

Thereafter, the same method as in the first embodiment is performed to form a contact hole 39 exposing portions intended to be bit line contacts and metal wiring contacts.

In addition, the third embodiment of the present invention will be described.

3A to 3E are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to a third embodiment of the present invention.

First, the process of FIGS. 1A to 1D is performed, and then the photoresist pattern (not shown) is removed.

Next, a first planarization layer 57 having a bit line contact hole (not shown) is formed on the entire surface.

Next, a bit line conductive layer 58 filling the bit line contact hole is formed on the first planarization layer 57.

An antireflection film 59 and a mask insulating film 60 are sequentially formed on the bit line conductive layer 58. (See Figure 3a)

Next, the mask insulating film 60, the antireflection film 59, and the bit line conductive layer 58 are sequentially etched using a bit line mask (not shown) as an etching mask. (See Figure 3b)

Next, a contact mask 62 is formed on the entire surface to expose a second planarization layer 61 and exposes a portion of the peripheral circuit portion, which is intended as a power line contact and a metal wiring contact, on the second planarization layer 61. ). (See Figure 3c)

Next, the second planarization layer 61 and the first planarization layer 57 are etched using the contact mask 62 as an etch mask, and the mask insulating layer 54 on the bit line and the gate electrode is removed. . (See FIG. 3D)

Next, the barrier insulating film 56 and the buffer insulating film 55 are etched using the contact mask 62 as an etch mask, and the anti-reflection film 53 on the bit line and the gate electrode is removed to form the contact hole 63. ). (See Figure 3e)

As described above, in the method of forming a contact hole of a semiconductor device according to the present invention, when forming a power line contact or a bit line contact in a peripheral circuit portion having a low level, the barrier insulating film and the buffer oxide film on the upper part of the gate electrode or the upper part of the bit line are formed. After removal, the barrier insulating film and the mask insulating film over the active region and the anti-reflection film over the gate electrode and the bit line are removed to form a contact hole, thereby preventing damage to the active region during the contact etching process and thereby There is an advantage of improving characteristics and reliability.

Claims (5)

Forming an interlayer insulating film over the entire surface to expose the peripheral circuit portion over the semiconductor substrate on which the anti-reflection film and the mask insulating film are stacked; Forming a planarization film over the entire surface; Forming a photoresist pattern on the planarization layer exposing an active region and a portion of the gate electrode to be contacted; Etching the planarization film on the active region, the planarization film and the mask insulating film on the gate electrode using the photoresist pattern as an etching mask; And forming a contact hole by removing the interlayer insulating layer on the active region and the anti-reflective layer on the gate insulating layer using the photoresist pattern as an etching mask, and then removing the photoresist pattern. The method of claim 1, And the anti-reflection film is formed of an oxynitride film. The method of claim 1, And the mask insulating film is formed of an oxide film. The method of claim 1, And wherein the interlayer insulating film is formed in a stacked structure of a buffer oxide film and a nitride film. The method of claim 1, The method for forming a contact hole of the semiconductor device is used in a contact process for forming a bit line contact plug and a metal wiring contact plug.