KR100870299B1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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KR100870299B1
KR100870299B1 KR1020060106637A KR20060106637A KR100870299B1 KR 100870299 B1 KR100870299 B1 KR 100870299B1 KR 1020060106637 A KR1020060106637 A KR 1020060106637A KR 20060106637 A KR20060106637 A KR 20060106637A KR 100870299 B1 KR100870299 B1 KR 100870299B1
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insulating film
film
insulating layer
semiconductor device
etching process
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KR1020060106637A
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Korean (ko)
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KR20080039010A (en
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권우준
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 반도체 기판 상부에 제1 베리어 메탈막, 금속막, 제2 베리어 메탈막, 버퍼 절연막 및 제1 절연막이 적층된 구조의 패턴으로 형성되는 단계와, 상기 패턴을 포함한 반도체 기판 상부에 제2 절연막을 형성하는 단계와, 상기 제1 절연막 상부가 일부 노출되도록 상기 제2 절연막을 식각하는 단계와, 상기 제1 절연막을 제거하는 단계와, 상기 버퍼 절연막과 제2 절연막 측면의 일부를 제거하여 금속 배선 콘택 홀을 형성하는 단계로 이루어진다.The present invention relates to a method for manufacturing a semiconductor device, the method comprising: forming a pattern having a structure in which a first barrier metal film, a metal film, a second barrier metal film, a buffer insulating film, and a first insulating film are stacked on a semiconductor substrate; Forming a second insulating film over the semiconductor substrate including the pattern, etching the second insulating film so that the upper portion of the first insulating film is partially exposed, removing the first insulating film, 2 is a step of removing a portion of the insulating film side to form a metal wiring contact hole.

금속 배선 콘택 홀, 알루미늄, 질화막, 폴리머, 펀치, 버퍼 산화막, 건식 식각, 습식 식각 Metal wiring contact hole, aluminum, nitride, polymer, punch, buffer oxide, dry etching, wet etching

Description

반도체 소자의 제조방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

도 1a 내지 도 1e는 본 발명의 일 실시 예에 따른 반도체 소자의 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A through 1E are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 102 : 제1 베리어 메탈막100 semiconductor substrate 102 first barrier metal film

104 : 금속막 106 : 제2 베리어 메탈막104: metal film 106: second barrier metal film

108 : 버퍼 절연막 110 : 제1 절연막108: buffer insulating film 110: first insulating film

112 : 하드 마스크막 114 : 제2 절연막112: hard mask film 114: second insulating film

116 : 포토레지스트 패턴 118 : 금속 배선 콘택 홀116 photoresist pattern 118 metal wiring contact hole

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 금속 배선 콘택 홀을 형성하기 위한 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for forming a metal wiring contact hole.

일반적으로, 반도체 소자 제조 공정에서 원하는 패턴을 형성하기 위해 예정된 막을 증착하고, 그 상부에 포토레지스트 패턴을 형성하여 포토레지스트 패턴을 마스크로 식각 공정을 실시하여 원하는 패턴의 막을 형성한다.In general, a predetermined film is deposited to form a desired pattern in a semiconductor device manufacturing process, a photoresist pattern is formed thereon, and an etching process is performed using the photoresist pattern as a mask to form a film of a desired pattern.

그리고 반도체 기판의 셀 지역에 트랜지스터 등의 액티브 소자를 형성한 다음 그 상부에서 도전층의 저항을 최소화시키기 위해 금속 배선을 사용한다. An active device such as a transistor is formed in a cell region of the semiconductor substrate, and then metal wiring is used to minimize the resistance of the conductive layer thereon.

금속 배선은 금속 배선 콘택을 형성한 후 금속 배선 콘택을 포함한 반도체 기판 상부에 금속막을 증착한다. 금속막 상부에 포토레지스트 패턴을 형성한 후 포토레지스트 패턴을 마스크로 하부에 노출되는 금속막을 식각하여 금속 배선을 형성한다. The metal wiring forms a metal wiring contact and then deposits a metal film on the semiconductor substrate including the metal wiring contact. After forming the photoresist pattern on the upper portion of the metal layer, the metal layer exposed to the lower portion is etched using the photoresist pattern as a mask to form a metal wiring.

한편, 반도체 소자의 고집적화에 따라 반도체 소자의 내부에서 상하에 형성되어 금속 배선을 연결하는 금속 배선 콘택 홀은 자체의 크기와 주변 배선과의 간격이 감소하고, 금속 배선 콘택 홀의 지름과 깊이의 비인 에스팩트비(aspect ratio; AR)가 증가함으로써 후속 공정을 실시하는데 문제점이 있다. On the other hand, according to the high integration of semiconductor devices, metal wiring contact holes formed in the upper and lower sides of the semiconductor device to connect the metal wirings have their own size and the distance between peripheral wirings reduced, and the ratio of the diameter and depth of the metal wiring contact holes is S. There is a problem in carrying out subsequent processes due to an increase in the aspect ratio (AR).

본 발명은 금속 배선 상부에 버퍼 절연막과 절연막을 증착하여 식각 선택비를 인위적으로 만들어주고, 금속 배선 콘택 홀을 형성하기 위한 식각 공정시 건식(dry) 식각, 습식(wet) 식각 및 건식 식각 방법을 차례로 실시하여 콘택 저항(Rc)을 안정화시키기 위한 것이다. According to the present invention, a dry etching method, a dry etching method, a wet etching method, and a dry etching method are used to artificially create an etching selectivity by depositing a buffer insulating film and an insulating film on an upper part of a metal wiring, and to form a metal wiring contact hole. This is done in order to stabilize the contact resistance Rc.

본 발명의 일 실시 예에 따른 반도체 소자의 제조방법은, 반도체 기판 상부에 제1 베리어 메탈막, 금속막, 제2 베리어 메탈막, 버퍼 절연막 및 제1 절연막이 적층된 구조의 패턴으로 형성된다. 패턴을 포함한 반도체 기판 상부에 제2 절연막을 형성한다. 제1 절연막 상부가 일부 노출되도록 제2 절연막을 식각한다. 제1 절연막을 제거한다. 버퍼 절연막과 제2 절연막 측면의 일부를 제거하여 금속 배선 콘택 홀을 형성한다.In the method of manufacturing a semiconductor device according to an embodiment of the present invention, a first barrier metal film, a metal film, a second barrier metal film, a buffer insulating film, and a first insulating film are formed on a semiconductor substrate. A second insulating film is formed on the semiconductor substrate including the pattern. The second insulating layer is etched to partially expose the upper portion of the first insulating layer. The first insulating film is removed. A portion of side surfaces of the buffer insulating film and the second insulating film are removed to form a metal wiring contact hole.

상기에서, 금속막은 알루미늄(Al)으로 형성한다. 버퍼 절연막은 10Å 내지 50Å 두께의 산화막으로 형성한다. 제1 절연막은 100Å 내지 1000Å 두께의 질화막으로 형성한다. 제2 절연막은 HDP(High Density Plasm) 산화막으로 형성한다. 제2 절연막은 플라즈마를 이용한 건식(dry) 식각 공정을 이용하여 300Å 내지 6000Å의 두께로 식각한다. In the above, the metal film is formed of aluminum (Al). The buffer insulating film is formed of an oxide film having a thickness of 10 GPa to 50 GPa. The first insulating film is formed of a nitride film having a thickness of 100 GPa to 1000 GPa. The second insulating film is formed of a high density plasma (HDP) oxide film. The second insulating layer is etched to a thickness of 300 kV to 6000 kV using a dry etching process using plasma.

제2 절연막 식각 공정시 제2 절연막과 제1 절연막의 식각 선택비는 10:1 내지 30:1로 한다. 제2 절연막 식각 공정시 과도 식각으로 제1 절연막 상부가 일부 제거되거나, 제1 절연막 상부에서 식각이 멈춘다. 제1 절연막은 습식(wet) 식각 공정으로 제거한다. 제1 절연막을 제거하기 위한 습식 식각 공정은 뜨거운(hot) H3PO4 용액을 이용하여 10분 내지 90분 동안 실시한다. 버퍼 절연막 및 제2 절연막 측면의 일부는 플라즈마를 이용한 건식 식각 공정으로 제거한다.The etching selectivity of the second insulating film and the first insulating film in the second insulating film etching process may be 10: 1 to 30: 1. During the second insulating layer etching process, the upper portion of the first insulating layer is partially removed due to the excessive etching, or the etching is stopped on the upper portion of the first insulating layer. The first insulating layer is removed by a wet etching process. The wet etching process for removing the first insulating layer is performed for 10 to 90 minutes using a hot H 3 PO 4 solution. Portions of the side surfaces of the buffer insulating film and the second insulating film are removed by a dry etching process using plasma.

알루미늄(Al)으로 이루어진 금속 배선 상부를 노출하는 금속 배선 콘택 홀은 다음과 같이 형성된다.The metal wiring contact hole exposing the upper portion of the metal wiring made of aluminum (Al) is formed as follows.

소자분리막, 게이트, 소스 콘택 플러그, 드레인 콘택 플러그 등 소정의 구조가 형성된 반도체 기판 상부에 제1 베리어 메탈막, 금속막 및 제2 베리어 메탈막을 순차적으로 형성한다. 이때, 제1 베리어 메탈막 및 제2 베리어 메탈막은 티타늄(Ti) 및 티타늄 질화막(TiN)을 적층된 구조로 형성하고, 금속막은 알루미늄(Al)으로 형성한다. A first barrier metal film, a metal film, and a second barrier metal film are sequentially formed on the semiconductor substrate having a predetermined structure such as an isolation layer, a gate, a source contact plug, and a drain contact plug. In this case, the first barrier metal film and the second barrier metal film are formed of a stacked structure of titanium (Ti) and titanium nitride film (TiN), and the metal film is formed of aluminum (Al).

그런 다음, 금속 배선을 형성하기 위해 사진 및 식각 공정으로 제2 베리어 메탈막, 금속막, 제1 베리어 메탈막을 순차적으로 식각한 후 금속 배선을 포함한 반도체 기판 상부에 절연막을 형성한다. 이때, 절연막은 HDP(High Density Plasm) 산화막으로 형성한다. 화학적 기계적 연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 절연막을 평탄화시킨다. Then, the second barrier metal film, the metal film, and the first barrier metal film are sequentially etched by a photo and etching process to form a metal wiring, and then an insulating film is formed on the semiconductor substrate including the metal wiring. At this time, the insulating film is formed of a high density plasma (HDP) oxide film. A chemical mechanical polishing (CMP) process is performed to planarize the insulating film.

그런 다음, 금속 배선 상부가 노출되도록 절연막 및 제2 베리어 메탈막을 순차적으로 식각하여 금속 배선 콘택 홀을 형성한다.Then, the insulating film and the second barrier metal film are sequentially etched to expose the upper portion of the metal wiring to form a metal wiring contact hole.

그러나, 금속 배선 콘택 홀을 형성하기 위한 식각 공정시 제2 베리어 메탈막에 펀치(punch)가 발생하여 메탈릭 폴리머(metallic polymer)를 발생시킨다. 이는 후속 공정에 영향을 미쳐 콘택 저항(Rc) 변화(variation)를 유발시킨다. However, during the etching process for forming the metal wiring contact hole, a punch is generated in the second barrier metal layer to generate a metallic polymer. This affects subsequent processes resulting in contact resistance (Rc) variations.

또한, 제2 베리어 메탈막에 펀치가 발생하는 것은 절연막 증착시 두께가 고르지 못하여 절연막 표면을 평탄화시키기 위해 화학적 기계적 연마(CMP) 공정을 실시하게 되는데, 이로 인하여 절연막의 높이 변화가 발생하기 때문이다. In addition, the punch is generated in the second barrier metal film because the thickness of the insulating film is uneven, and the chemical mechanical polishing (CMP) process is performed to planarize the surface of the insulating film, which causes a change in the height of the insulating film.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1e는 본 발명의 일 실시 예에 따른 반도체 소자의 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A through 1E are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 소자분리막, 게이트, 소스 콘택 플러그, 드레인 콘택 플러그 등 소정의 구조가 형성된 반도체 기판(100) 상부에 제1 베리어 메탈막(102)을 형성한다. 이때, 제1 베리어 메탈막(102)은 티타늄(Ti) 및 티타늄 질화막(TiN)을 적층된 구조로 형성한다. 제1 베리어 메탈막(102) 상부에 금속막(104) 및 제2 베리어 메탈막(106)을 형성한다. 이때, 금속막(104)은 알루미늄(Al)으로 형성하고, 제2 베리어 메탈막(106)은 티타늄(Ti) 및 티타늄 질화막(TiN)을 적층된 구조로 형성한다. 제2 베리어 메탈막(106) 상부에 버퍼 절연막(108)을 형성한다. 이때, 버퍼 절연막(108)은 10Å 내지 50Å 두께의 산화막으로 형성한다. 버퍼 절연막(108) 상부에 제1 절연막(110) 및 하드 마스크막(112)을 순차적으로 형성한다. 이때, 제1 절연막(110)은 100Å 내지 1000Å 두께의 질화막으로 형성하고, 하드 마스크막(112)은 아몰포스 카본(amorphous carbon)으로 형성한다. Referring to FIG. 1A, a first barrier metal layer 102 is formed on a semiconductor substrate 100 on which a predetermined structure such as an isolation layer, a gate, a source contact plug, and a drain contact plug is formed. In this case, the first barrier metal film 102 is formed of a stacked structure of titanium (Ti) and titanium nitride film (TiN). The metal film 104 and the second barrier metal film 106 are formed on the first barrier metal film 102. In this case, the metal film 104 is formed of aluminum (Al), and the second barrier metal film 106 is formed of a stacked structure of titanium (Ti) and titanium nitride film (TiN). A buffer insulating layer 108 is formed on the second barrier metal layer 106. In this case, the buffer insulating film 108 is formed of an oxide film having a thickness of 10 kV to 50 kV. The first insulating layer 110 and the hard mask layer 112 are sequentially formed on the buffer insulating layer 108. In this case, the first insulating film 110 is formed of a nitride film having a thickness of 100 kHz to 1000 kHz, and the hard mask film 112 is formed of amorphous carbon.

도 1b를 참조하면, 금속 배선을 형성하기 위해 사진 및 식각 공정으로 하드 마스크막(112), 제1 절연막(110), 버퍼 절연막(108), 제2 베리어 메탈막(106), 금속막(104), 제1 베리어 메탈막(102)을 순차적으로 식각한다. Referring to FIG. 1B, a hard mask film 112, a first insulating film 110, a buffer insulating film 108, a second barrier metal film 106, and a metal film 104 are formed by a photolithography and etching process to form metal wirings. ), The first barrier metal layer 102 is sequentially etched.

그런 다음, 하드 마스크막(112)을 제거한 후 금속 배선을 포함한 반도체 기판(100) 상부에 제2 절연막(114)을 형성한 후 화학적 기계적 연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 제2 절연막(114)을 평탄화시킨다. 이때, 제2 절연막(114)은 HDP(High Density Plasm) 산화막으로 형성한다. 제1 절연막(110) 상부의 일부 영역이 노출되도록 제2 절연막(114) 상부에 포토레지스트 패턴(116)을 형성한다.After removing the hard mask layer 112, the second insulating layer 114 is formed on the semiconductor substrate 100 including the metal wires, and then subjected to a chemical mechanical polishing (CMP) process. Planarize 114. In this case, the second insulating layer 114 is formed of a high density plasma (HDP) oxide film. The photoresist pattern 116 is formed on the second insulating layer 114 to expose a portion of the upper portion of the first insulating layer 110.

도 1c를 참조하면, 포토레지스트 패턴(116)을 마스크로 제2 절연막(114)을 식각한다. 이때, 제2 절연막(114)은 플라즈마를 이용한 건식(dry) 식각 공정을 이용하여 300Å 내지 6000Å의 두께로 식각한다. 여기서, 제2 절연막(114)과 제1 절연막(110)의 식각 선택비는 10:1 내지 30:1로 한다. 제2 절연막(114) 식각 공정시 과도 식각으로 제1 절연막(110) 상부가 일부 제거되거나, 제1 절연막(110) 상부에서 식각이 멈춘다.Referring to FIG. 1C, the second insulating layer 114 is etched using the photoresist pattern 116 as a mask. In this case, the second insulating layer 114 is etched to a thickness of 300 kV to 6000 kV using a dry etching process using plasma. Here, the etching selectivity of the second insulating film 114 and the first insulating film 110 is 10: 1 to 30: 1. During the etching process of the second insulating layer 114, a portion of the upper portion of the first insulating layer 110 is removed by the excessive etching, or the etching is stopped on the upper portion of the first insulating layer 110.

도 1d를 참조하면, 제1 절연막(110)을 습식(wet) 식각 공정으로 제거한다. 이때, 제1 절연막(110)을 제거하기 위한 습식 식각 공정은 뜨거운(hot) H3PO4 용액을 이용하여 10분 내지 90분 동안 실시한다. 제1 절연막(110) 하부에 형성된 버퍼 절연막(108)은 습식 식각 공정시 사용되는 H3PO4 용액이 금속 배선인 금속막(104) 쪽으로 침투하여 손상을 주는 것을 막는 역할을 한다. Referring to FIG. 1D, the first insulating layer 110 is removed by a wet etching process. In this case, the wet etching process for removing the first insulating layer 110 is performed for 10 to 90 minutes using a hot H 3 PO 4 solution. The buffer insulating layer 108 formed under the first insulating layer 110 serves to prevent the H 3 PO 4 solution used in the wet etching process from penetrating into the metal layer 104, which is a metal wiring, to be damaged.

도 1e를 참조하면, 버퍼 절연막(108) 및 제2 절연막(114) 측면의 일부를 건식 식각 공정으로 제거하여 금속 배선 콘택 홀(118)을 형성한다. 이때, 버퍼 절연막(108) 및 제2 절연막(114) 측면의 일부를 제거하기 위한 건식 식각 공정은 플라즈마를 이용한다. Referring to FIG. 1E, portions of side surfaces of the buffer insulating layer 108 and the second insulating layer 114 are removed by a dry etching process to form the metal wiring contact hole 118. At this time, the dry etching process for removing portions of the sidewalls of the buffer insulating film 108 and the second insulating film 114 uses plasma.

상기와 같이, 금속 배선 콘택 홀(118)을 형성하기 위해 제2 절연막(114) 식각 공정시 제1 절연막(110) 중간 부분에서 식각을 멈춤으로써 제2 베리어 메탈막(106)의 손실을 최소화할 수 있다. As described above, the etching of the second barrier metal layer 106 may be minimized by stopping the etching in the middle portion of the first insulating layer 110 during the etching process of the second insulating layer 114 to form the metal wiring contact hole 118. Can be.

또한, 제1 절연막(110) 하부에 버퍼 절연막(108)을 형성함으로써 제1 절연막(110) 제거 공정시 사용하는 H3PO4 용액이 금속 배선인 금속막(104) 쪽으로 침투하여 손상되는 것을 방지할 수 있다. In addition, the buffer insulating film 108 is formed under the first insulating film 110 to prevent the H 3 PO 4 solution used in the removal process of the first insulating film 110 from penetrating toward the metal film 104, which is a metal wiring, to be damaged. can do.

본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었으나, 상기한 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명의 효과는 다음과 같다.As described above, the effects of the present invention are as follows.

첫째, 금속 배선 콘택 홀을 형성하기 위해 제2 절연막 식각 공정시 제1 절연막 중간 부분에서 식각을 멈춤으로써 제2 베리어 메탈막의 손실을 최소화할 수 있다. First, the loss of the second barrier metal layer may be minimized by stopping the etching in the middle portion of the first insulating layer during the second insulating layer etching process to form the metal wiring contact hole.

둘째, 제1 절연막 하부에 버퍼 절연막을 형성함으로써 제1 절연막 제거 공정시 사용하는 H3PO4 용액이 금속 배선인 금속막 쪽으로 침투하여 손상되는 것을 방지 할 수 있다. Second, by forming a buffer insulating film under the first insulating film it can be prevented that the H 3 PO 4 solution used in the first insulating film removal process penetrates into the metal film of the metal wiring to be damaged.

셋째, 금속 배선 콘택 홀을 형성하기 위해 건식 식각, 습식 식각 및 건식 식각 방법을 차례로 실시함으로써 콘택 저항(Rc)을 안정화시킬 수 있다. Third, the contact resistance Rc may be stabilized by performing dry etching, wet etching, and dry etching in order to form the metal wiring contact hole.

Claims (11)

반도체 기판 상부에 제1 베리어 메탈막, 금속막, 제2 베리어 메탈막, 버퍼 절연막 및 제1 절연막이 적층된 구조의 패턴이 형성되는 단계;Forming a pattern having a structure in which a first barrier metal film, a metal film, a second barrier metal film, a buffer insulating film, and a first insulating film are stacked on the semiconductor substrate; 상기 패턴을 포함한 상기 반도체 기판 상부에 제2 절연막을 형성하는 단계;Forming a second insulating film on the semiconductor substrate including the pattern; 상기 제1 절연막 상부가 일부 노출되도록 상기 제2 절연막을 식각하는 단계;Etching the second insulating film to partially expose an upper portion of the first insulating film; 상기 제1 절연막을 제거하는 단계; 및Removing the first insulating film; And 상기 제2 절연막 상부의 측면 및 상기 버퍼 절연막을 제거하여 금속 배선 콘택 홀을 형성하는 단계를 포함하는 반도체 소자의 제조방법.And removing a side surface of the second insulating layer and the buffer insulating layer to form a metal wiring contact hole. 제1항에 있어서, The method of claim 1, 상기 금속막은 알루미늄(Al)으로 형성하는 반도체 소자의 제조방법.The metal film is a method of manufacturing a semiconductor device formed of aluminum (Al). 제1항에 있어서, The method of claim 1, 상기 버퍼 절연막은 10Å 내지 50Å 두께의 산화막으로 형성하는 반도체 소자의 제조방법.The buffer insulating film is a semiconductor device manufacturing method of forming an oxide film having a thickness of 10 ~ 50Å. 제1항에 있어서, The method of claim 1, 상기 제1 절연막은 100Å 내지 1000Å 두께의 질화막으로 형성하는 반도체 소자의 제조방법.The first insulating film is a semiconductor device manufacturing method of forming a nitride film of 100 ~ 1000 Å thickness. 제1항에 있어서, The method of claim 1, 상기 제2 절연막은 HDP(High Density Plasm) 산화막으로 형성하는 반도체 소자의 제조방법.The second insulating film is a semiconductor device manufacturing method of forming a high density plasma (HDP) oxide film. 제1항에 있어서,The method of claim 1, 상기 제2 절연막은 플라즈마를 이용한 건식(dry) 식각 공정을 이용하여 300Å 내지 6000Å의 두께로 식각하는 반도체 소자의 제조방법.And the second insulating layer is etched to a thickness of 300 kV to 6000 kV using a dry etching process using plasma. 제1항에 있어서,The method of claim 1, 상기 제2 절연막 식각 공정시 상기 제2 절연막과 제1 절연막의 식각 선택비는 10:1 내지 30:1인 반도체 소자의 제조방법.The etching selectivity of the second insulating film and the first insulating film in the second insulating film etching process is a manufacturing method of a semiconductor device 10: 1 to 30: 1. 제1항에 있어서,The method of claim 1, 상기 제2 절연막 식각 공정시 과도 식각으로 상기 제1 절연막 상부가 일부 제거되거나, 상기 제1 절연막 상부에서 식각이 멈추는 반도체 소자의 제조방법.And partially removing the upper portion of the first insulating layer or removing the upper portion of the first insulating layer due to the excessive etching during the second insulating layer etching process. 제1항에 있어서,The method of claim 1, 상기 제1 절연막은 습식(wet) 식각 공정으로 제거하는 반도체 소자의 제조방법.The method of claim 1, wherein the first insulating layer is removed by a wet etching process. 제9항에 있어서,The method of claim 9, 상기 습식 식각 공정은 H3PO4 용액을 이용하여 10분 내지 90분 동안 실시하는 반도체 소자의 제조방법.The wet etching process is a method of manufacturing a semiconductor device performed for 10 minutes to 90 minutes using a H 3 PO 4 solution. 제1항에 있어서,The method of claim 1, 상기 버퍼 절연막 및 제2 절연막 측면의 일부는 플라즈마를 이용한 건식 식각 공정으로 제거하는 반도체 소자의 제조방법.A portion of the side surface of the buffer insulating film and the second insulating film is removed by a dry etching process using a plasma.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990001921A (en) 1997-06-18 1999-01-15 윤종용 Metal contact hole formation method of semiconductor device
KR20000043205A (en) 1998-12-28 2000-07-15 김영환 Method for forming contact hole of semiconductor device
KR20000056719A (en) 1999-02-25 2000-09-15 윤종용 Method for forming a contact of a semiconductor device
KR20050116482A (en) 2004-06-07 2005-12-13 주식회사 하이닉스반도체 Semiconductor device and method for fabrication thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990001921A (en) 1997-06-18 1999-01-15 윤종용 Metal contact hole formation method of semiconductor device
KR20000043205A (en) 1998-12-28 2000-07-15 김영환 Method for forming contact hole of semiconductor device
KR20000056719A (en) 1999-02-25 2000-09-15 윤종용 Method for forming a contact of a semiconductor device
KR20050116482A (en) 2004-06-07 2005-12-13 주식회사 하이닉스반도체 Semiconductor device and method for fabrication thereof

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