TW200910520A - Method for forming contact in semiconductor device - Google Patents

Method for forming contact in semiconductor device Download PDF

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Publication number
TW200910520A
TW200910520A TW096148552A TW96148552A TW200910520A TW 200910520 A TW200910520 A TW 200910520A TW 096148552 A TW096148552 A TW 096148552A TW 96148552 A TW96148552 A TW 96148552A TW 200910520 A TW200910520 A TW 200910520A
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TW
Taiwan
Prior art keywords
contact hole
layer
forming
insulating layer
contact
Prior art date
Application number
TW096148552A
Other languages
Chinese (zh)
Inventor
Sang-Hoon Cho
sang-on Lee
Original Assignee
Hynix Semiconductor Inc
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Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200910520A publication Critical patent/TW200910520A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

A method for fabricating a semiconductor device includes providing a substrate, forming an insulation layer over the substrate, forming a photoresist pattern for a contact hole over the insulation layer, wherein the photoresist pattern includes an opening having a critical dimension (CD) greater than a desired contact CD, forming a contact hole by selectively etching the insulation layer using the photoresist pattern, and forming a spacer on a sidewall of the contact hole until a CD of the contact hole whose sidewall is covered by the spacer is reduced to a desired contact CD.

Description

200910520 九、發明說明： 本發明係主張2007年8月31日申請之韓國專利申請 案第2007-0088146號優先權，在此將其全部倂入供參照。 【發明所屬之技術領域】 本發明係關於一種製造半導體元件之方法，並更特別 地，係關於一種於半導體元件中形成接觸部之方法。 【先前技術】 諸如動態隨機存取記億體（DRAM)元件之半導體元件 包含多層金屬線。因此，用來形成接觸部的製程要求連接 上金屬線與下金屬線。 近年來，隨著半導'體元件高度積體化，增加了接觸部 之縱橫比。因此，在形成該接觸部之製程期間會發生各種 問題。該等問題將參照第1 A到1 C圖作更詳細說明。 參照第1 A圖，包含位元線導電層1 1 A與位元線硬遮 罩層1 1 B之位元線1 1係形成於包含特定下部結構之基板 (沒有顯示）上方。 接著’於包含該位元線1 1之該合成結構上方形成第一 絕緣層1 2。蝕刻停止層1 3與第二絕緣層1 4係形成於該第 一絕緣層1 2上方。該第二絕緣層1 4係形成具有一足夠厚 度，以覆蓋在半導體記憶元件中之胞元區內所形成之電容 器（沒有顯示）。 在於該第二絕緣層1 4上方形成用於接觸孔製程硬遮 罩層15之後’具有開口以露出目標接觸孔區之光阻圖案 17係於該硬遮罩層15上方形成。抗反射層16可被插入該 200910520 光阻圖案1 7下方，以防止在曝光製程期間的反射。 參照第1 B圖，使用該光阻圖案1 7作爲蝕刻遮罩，蝕 刻該硬遮罩層15以形成硬遮罩圖案15A。在蝕刻製程期 間，該光阻圖案1 7會有某個程度之損失。 參照第1C圖，使用該硬遮罩圖案15A作爲蝕刻障壁， 蝕刻該第二絕緣層1 4、該蝕刻停止層1 3、該第一絕緣層 1 2及該位元線硬遮罩層1 1 B，以形成可露出該位元線導電 層11A之接觸孔18。接著，移除該硬遮罩圖案15A。其後， 藉由將導電層塡入該接觸孔18中形成接觸部（沒有顯示）， 並在該第二絕緣層1 4上方形成上金屬線（沒有顯示），用以 連接該接觸部。 然而，當降低設計規則時，光阻圖案1 7之顯影檢視臨 界尺寸（DICD)會明顯地減少，例如，在約40nm以下，其 在形成接觸孔之製程期間造成下述的問題。 首先，光阻圖案17之厚度也大體上隨著該DICD減少 而減少，並因而難以飽刻，即使用該光阻圖案1 7之硬遮罩 層1 5亦如此。 當該光阻圖案1 7之DICD減少時，會增加胞元區中之 電容器的高度以確保期望之電容値。因此，也增加該第二 絕緣層1 4之高度以覆蓋該電容器。此意指該接觸孔1 8具 有已減少臨界尺寸（CD)之頂部’同時具有增加的深度。亦 即，增加該接觸孔1 8之縱橫比。然而，在使用典型乾式蝕 刻設備的情況下，該接觸孔1 8之CD會隨著自頂部至底部 延伸而減少。因此，因爲該接觸孔1 8縱橫比的增加而可能 200910520 發生形成接觸孔1 8的接觸開口失敗（參照第1 c圖中虛線）。 爲克服上述問題，可考慮增加該光阻圖案1 7之D I C D， 藉以增加該光阻圖案1 7之厚度並確保接觸開口邊限。然 而’該光阻圖案17之DICD增加與隨後之該接觸孔18之 頂部的CD增加，會導致接觸部與相鄰金屬線之間的橋部 (bridge)問題。因爲字元線與金屬線具有相同節距，此問題 於字元線帶結構中會更頻繁的發生，其中該字元線帶結構 爲用以將字元線直接連接於金屬線，以減少周圍電路區中 之次字元線區域。 【發明內容】 本發明係提供一種於半導體元件中形成接觸部之方 法。 依據本發明之觀點，其提供一種製造半導體元件之方 法。該方法包含：配置基板；於該基板上方形成絕緣層； 於該絕緣層上方，形成接觸孔用光阻圖案，其中該光阻圖 案包含開口，其具有大於期望接觸CD之臨界尺寸（CD); 使用該光阻圖案，藉由選擇性蝕刻該絕緣層，形成接觸孔； 及於該接觸孔之側壁上形成間隔，直到該接觸孔之CD被 減少至期望的接觸CD，其中該接觸孔之側壁被該間隔覆 蓋。 【實施方式】 第2 A到2 D圖係剖面視圖，用以說明依據本發明之實 施例於半導體元件中形成接觸部之方法。 參照第2A圖，包含位元線導電層21A與位元硬遮罩 200910520 層2 1 B之位元線2 1係於包含特定下部結構之基板（沒有顯 示）上方形成。 接著，於包含該位元線2 1之合成結構上方形成第一絕 緣層2 2。蝕刻停止層2 3及第二絕緣層2 4係於該第一絕緣 層22上方形成。形成該第二絕緣層24具有足以覆蓋於半 導體元件之胞元區中所形成的電容器（沒有顯示）。 在於該第二絕緣層24上方’形成用於接觸孔製程的硬 遮罩層25之後，具有用以露出目標接觸孔區之開口的光阻 圖案27形成於硬遮罩層25上方。在此’該光阻圖案27之 開口露出目標接觸孔區以具有大於由設計規則所界定之臨 界尺寸（C D )。因此，即使降低設計規則，亦不需要引入新 的微影設備。此外，其可確保光阻圖案27之厚度，並因而 可輕易地蝕刻該硬遮罩層25。抗反射層26可於該光阻圖 案27下方形成，用以防止曝光製程期間的反射。 接著，使用該光阻圖案27作爲蝕刻遮罩，蝕刻該硬遮 罩層25，以形成硬遮罩圖案25A。 參照第2B圖，使用該硬遮罩圖案25A作爲蝕刻障壁， 依序蝕刻該第二絕緣層2 4、該蝕刻停止層2 3、該第一絕緣 層22與該位元線硬遮罩層2 1 B，以形成接觸孔28，直到露 出位元線導電層2 1 A。該接觸孔2 8之頂部之第一臨界尺寸 (CD)W1對應光阻圖案27之開口之尺寸。因此，該接觸孔 28之頂部之第一 CD W1係大於設計規則所界定之尺寸。當 然，該接觸孔2 8之頂部之第一C D W1應具有選擇値，使 得該接觸孔2 8不會侵入任何相鄰接觸孔。 200910520 因此，依據本發明，即使蝕刻目標（例如，該第 層24、該蝕刻停止層23、該第一絕緣層22、及該 硬遮罩層21B)是厚的，且該接觸孔28之CD隨著自 底部延伸而減少，因爲增加接觸邊限，故可防止接 的失敗。此意指不需要新發展之乾式蝕刻設備。 然而，若依照第2 B圖之製程結果，於頂部具 CD之接觸孔28上實施用於形成接觸部與上金屬線 製程，則會在該接觸部與其相鄰金屬線之間產生橋 此，爲防止此一橋部問題，應實施第2C與2D圖中 附加製程。 參照第2C圖，於第2B圖中之合成結構之表面 成間隔用絕緣層29，以減少該接觸孔28之頂部的、 W 1，直到其達到第二C D W 2。形成該絕緣層2 9直 觸孔2 8之頂部之第二CD W2達到設計規則所界定· 例如從約1 〇〇 A到約999A。在此實施例中’該絕緣只 爲氧化物層，例如03-未摻雜矽酸鹽玻璃（USG)層、 化四乙氧基矽酸鹽（PETEOS)層、硼磷矽酸鹽玻璃 層、磷矽酸鹽玻璃（PSG)層等。該接觸孔28之底部 絕緣層2 9覆蓋。 參照第2 D圖，移除在該接觸孔2 8之底部’間 緣層2 9，以露出位元線導電層2 1 A，藉以將該絕I 殘留在該接觸孔2 8之側壁上’以形成間隔2 9 A ’同 該接觸孔28之頂部的第二CD W2。在該接觸孔28 中的該絕緣層29係藉由覆蓋乾式蝕刻製程而移除。 二絕緣 位元線 頂部至 觸開口 有增加 之隨後 部。因 所示之 上方形 I 一 CD 到該接 之CD， I 29可 電漿強 (BPSG) 可被該 隔用絕 象層 29 時保持 之底部 在該覆 200910520 蓋乾式蝕刻製程期間，可選用地實施平坦化製程以改善表 面均勻性。該平坦化製程可藉由使用接觸式化學機械硏磨 (C Μ P )法較佳地實施，較佳地使用從約5 0 0 A到約1 5 0 0 A範 圍的硏磨目標。 雖然沒有顯示，但仍實施隨後之製程，藉由於具有該 第二CD W2之接觸孔28中塡入導電材料（例如，金屬）以形 成接觸部，並接著形成連接該第二絕緣層24上方之接觸部 的金屬線。 在此實施例中，已說明形成位元線與金屬線之間的接 觸部之方法的範例。然而，該方法可被應用至需要深接觸 部結構之所有種類的半導體元件。特別地，因爲大於設計 規則所界定之尺寸的該接觸孔頂部的C D會導致相鄰接觸 孔互相接觸，故本發明可較佳地應用至具有低接觸密度之 區域。 雖然本發明已針對特定實施例敘述，但本發明之上述 實施例並不限定於此。其對於熟悉該項技術者將顯而易見 的是，本發明可作成各種改變與修改而仍不脫離如下述申 請專利範圍中所界定之本發明之精神與範圍。 【圖式簡單說明】 第1 A到1 C圖係半導體元件中形成接觸部之傳統方法 之剖面視圖。 第2A到2D圖係依據本發明之實施例於半導體元件中 形成接觸部之方法之剖面視圖。 【主要元件符號說明】 -10- 200910520 11' 2 1 位 元 線 1 1 A 、2 1 A 位 元 線 導 電 層 12、 22 第 一 絕 緣 層 13、 23 蝕 刻 停 止 層 14、 24 第 二 絕 緣 層 15、 25 硬 遮 罩 層 1 5 A 、25 A 硬 遮 罩 圖 案 16 抗 反 射 層 17、 27 光 阻 圖 案 2 1 B 位 元 線 硬 遮 罩 28 接 觸 孔 29 絕 緣 層 29 A 間隔 W 1 第 一 臨 界 尺 寸 W2 第 二 臨 界 尺 寸 -11。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a method of forming a contact in a semiconductor device. [Prior Art] A semiconductor component such as a dynamic random access memory (DRAM) device includes a plurality of metal wires. Therefore, the process for forming the contacts requires the connection of the upper metal wire and the lower metal wire. In recent years, as the semi-conductive body elements are highly integrated, the aspect ratio of the contact portion is increased. Therefore, various problems occur during the process of forming the contact portion. These questions will be explained in more detail with reference to Figures 1A to 1C. Referring to Fig. 1A, a bit line 11 including a bit line conductive layer 1 1 A and a bit line hard mask layer 1 1 B is formed over a substrate (not shown) including a specific lower structure. Next, a first insulating layer 12 is formed over the composite structure including the bit line 1 1 . An etch stop layer 13 and a second insulating layer 14 are formed over the first insulating layer 12. The second insulating layer 14 is formed to have a sufficient thickness to cover a capacitor (not shown) formed in the cell region of the semiconductor memory device. A photoresist pattern 17 having an opening to expose the target contact hole region is formed over the second insulating layer 14 to form a photoresist pattern 17 over the hard mask layer 15. An anti-reflective layer 16 can be inserted under the 200910520 photoresist pattern 17 to prevent reflection during the exposure process. Referring to Fig. 1B, the photoresist pattern 17 is used as an etch mask to etch the hard mask layer 15 to form a hard mask pattern 15A. The photoresist pattern 17 has a certain degree of loss during the etching process. Referring to FIG. 1C, the second insulating layer 14 , the etch stop layer 13 , the first insulating layer 12 , and the bit line hard mask layer 1 1 are etched using the hard mask pattern 15A as an etch barrier. B, to form a contact hole 18 that exposes the bit line conductive layer 11A. Next, the hard mask pattern 15A is removed. Thereafter, a contact portion (not shown) is formed by dipping the conductive layer into the contact hole 18, and an upper metal line (not shown) is formed over the second insulating layer 14 for connecting the contact portion. However, when the design rule is lowered, the development viewing critical dimension (DICD) of the photoresist pattern 17 is remarkably reduced, for example, below about 40 nm, which causes the following problems during the process of forming the contact holes. First, the thickness of the photoresist pattern 17 is also substantially reduced as the DICD is reduced, and thus it is difficult to saturate, i.e., the hard mask layer 15 using the photoresist pattern 17 is also the same. When the DICD of the photoresist pattern 17 is reduced, the height of the capacitor in the cell region is increased to ensure the desired capacitance 値. Therefore, the height of the second insulating layer 14 is also increased to cover the capacitor. This means that the contact hole 18 has a top portion that has a reduced critical dimension (CD) while having an increased depth. That is, the aspect ratio of the contact hole 18 is increased. However, in the case of a typical dry etching apparatus, the CD of the contact hole 18 will decrease as it extends from the top to the bottom. Therefore, because of the increase in the aspect ratio of the contact hole 18, it is possible that the contact opening forming the contact hole 18 fails in 200910520 (refer to the broken line in Fig. 1c). In order to overcome the above problem, it is conceivable to increase the D I C D of the photoresist pattern 17 to increase the thickness of the photoresist pattern 17 and to ensure contact opening margins. However, the increase in the DICD of the photoresist pattern 17 and the subsequent increase in the CD at the top of the contact hole 18 may cause a bridge problem between the contact portion and the adjacent metal line. Since the word line has the same pitch as the metal line, this problem occurs more frequently in the word line structure, where the word line structure is used to connect the word line directly to the metal line to reduce the circumference. The sub-word line area in the circuit area. SUMMARY OF THE INVENTION The present invention provides a method of forming a contact portion in a semiconductor element. According to the viewpoint of the present invention, there is provided a method of manufacturing a semiconductor element. The method includes: disposing a substrate; forming an insulating layer over the substrate; forming a contact hole photoresist pattern over the insulating layer, wherein the photoresist pattern includes an opening having a critical dimension (CD) greater than a desired contact CD; a photoresist pattern, wherein a contact hole is formed by selectively etching the insulating layer; and a space is formed on a sidewall of the contact hole until a CD of the contact hole is reduced to a desired contact CD, wherein a sidewall of the contact hole is Interval coverage. [Embodiment] Figs. 2A to 2D are cross-sectional views for explaining a method of forming a contact portion in a semiconductor element in accordance with an embodiment of the present invention. Referring to Fig. 2A, a bit line 2A including a bit line conductive layer 21A and a bit hard mask 200910520 layer 2 1 B is formed over a substrate (not shown) including a specific lower structure. Next, a first insulating layer 2 2 is formed over the composite structure including the bit line 2 1 . The etch stop layer 23 and the second insulating layer 24 are formed over the first insulating layer 22. The second insulating layer 24 is formed to have a capacitor (not shown) formed sufficient to cover the cell region of the semiconductor element. After the hard mask layer 25 for the contact hole process is formed over the second insulating layer 24, a photoresist pattern 27 having an opening for exposing the target contact hole region is formed over the hard mask layer 25. Here, the opening of the photoresist pattern 27 exposes the target contact hole region to have a critical dimension (C D ) greater than that defined by the design rule. Therefore, even if the design rules are lowered, there is no need to introduce new lithography equipment. Further, it ensures the thickness of the photoresist pattern 27, and thus the hard mask layer 25 can be easily etched. An anti-reflective layer 26 can be formed under the photoresist pattern 27 to prevent reflection during the exposure process. Next, the photoresist pattern 27 is used as an etch mask, and the hard mask layer 25 is etched to form a hard mask pattern 25A. Referring to FIG. 2B, the second insulating layer 24, the etch stop layer 23, the first insulating layer 22, and the bit line hard mask layer 2 are sequentially etched using the hard mask pattern 25A as an etch barrier. 1 B to form contact holes 28 until the bit line conductive layer 2 1 A is exposed. The first critical dimension (CD) W1 at the top of the contact hole 28 corresponds to the size of the opening of the photoresist pattern 27. Therefore, the first CD W1 at the top of the contact hole 28 is larger than the size defined by the design rules. Of course, the first C D W1 at the top of the contact hole 28 should have a selection 値 such that the contact hole 28 does not intrude into any adjacent contact hole. 200910520 Therefore, according to the present invention, even if the etching target (for example, the first layer 24, the etch stop layer 23, the first insulating layer 22, and the hard mask layer 21B) is thick, and the CD of the contact hole 28 As it extends from the bottom, the contact failure is prevented because the contact margin is increased. This means a dry etching apparatus that does not require new development. However, if the process for forming the contact portion and the upper metal line is performed on the contact hole 28 of the top portion of the CD according to the result of the process of FIG. 2B, a bridge is formed between the contact portion and the adjacent metal line. In order to prevent this bridge problem, additional processes in Figures 2C and 2D should be implemented. Referring to Fig. 2C, the surface of the resultant structure in Fig. 2B is spaced apart by an insulating layer 29 to reduce W1 at the top of the contact hole 28 until it reaches the second C D W 2 . The second CD W2 forming the top of the insulating layer 209 of the contact holes 28 is as defined by the design rules, for example from about 1 〇〇 A to about 999 Å. In this embodiment, the insulation is only an oxide layer, such as a 03-undoped tantalate glass (USG) layer, a tetraethoxyphthalate (PETEOS) layer, a borophosphonite glass layer, Phosphonate glass (PSG) layer, etc. The bottom of the contact hole 28 is covered by an insulating layer 29. Referring to FIG. 2D, the interlayer edge layer 9 9 at the bottom of the contact hole 28 is removed to expose the bit line conductive layer 2 1 A, thereby leaving the anode I on the sidewall of the contact hole 28. To form a second CD W2 with a spacing of 2 9 A ' at the top of the contact hole 28. The insulating layer 29 in the contact hole 28 is removed by a dry etching process. The second insulation of the bit line has an increased portion from the top to the touch opening. As shown above, the square I-CD to the connected CD, I 29 plasma strong (BPSG) can be maintained by the bottom of the insulating layer 29 during the cover of the 200910520 cover dry etching process, optionally A planarization process is implemented to improve surface uniformity. The planarization process can preferably be carried out by using a contact chemical mechanical honing (C Μ P) process, preferably using a honing target from about 50,000 A to about 1,500 A. Although not shown, the subsequent process is performed by forming a contact portion by forming a contact portion with a conductive material (for example, metal) in the contact hole 28 having the second CD W2, and then forming a connection above the second insulating layer 24. The metal wire of the contact. In this embodiment, an example of a method of forming a contact portion between a bit line and a metal line has been described. However, this method can be applied to all kinds of semiconductor elements requiring a deep contact structure. In particular, the present invention can be preferably applied to a region having a low contact density because the C D at the top of the contact hole larger than the size defined by the design rule causes the adjacent contact holes to contact each other. Although the present invention has been described with respect to specific embodiments, the above embodiments of the present invention are not limited thereto. It will be apparent to those skilled in the art that the present invention may be practiced with various modifications and changes without departing from the spirit and scope of the invention as defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to 1C are cross-sectional views showing a conventional method of forming a contact portion in a semiconductor element. 2A to 2D are cross-sectional views showing a method of forming a contact portion in a semiconductor element in accordance with an embodiment of the present invention. [Description of main component symbols] -10- 200910520 11' 2 1 bit line 1 1 A , 2 1 A bit line conductive layer 12, 22 First insulating layer 13, 23 Etch stop layer 14, 24 Second insulating layer 15 25 hard mask layer 1 5 A , 25 A hard mask pattern 16 anti-reflection layer 17, 27 photoresist pattern 2 1 B bit line hard mask 28 contact hole 29 insulating layer 29 A interval W 1 first critical dimension W2 second critical dimension -11

Claims (1)

200910520 十、申請專利範圍： 1 · 一種製造半導體元件之方法，該方法包含： 配置基板； 於該基板上方形成絕緣層； 於該絕緣層上方形成接觸孔用光阻圖案，其中該光阻 圖案包含開口，具有大於期望接觸臨界尺寸（CD)之臨界 尺寸（CD); 使用該光阻圖案，藉由選擇性蝕刻該絕緣層，形成接 觸孔；及 於該接觸孔之側壁上形成間隔，直到該接觸孔之CD 被減少至期望的接觸CD，其中該接觸孔之側壁被該間隔 覆蓋。 2 .如申請專利範圍第1項之方法，其中該所期望的接觸C D 由半導體元件用之設計法則所界定之C D。 3.如申請專利範圍第1項之方法，其中該基板包含位元 線，其具有在該絕緣層下方依序形成之位元線導電層與 位元線硬遮罩層，並實施形成接觸孔，藉由蝕刻該絕緣 層與該位元線硬遮罩層露出該位元線導電層。 4 .如申請專利範圍第1項之方法，其中更包含在形成該等 光阻圖案前，於該絕緣層上方形成硬遮罩層。 5 ·如申請專利範圍第4項之方法，其中使用由該光阻圖案 予以圖案化之該硬遮罩層以實施形成該接觸孔。 6.如申請專利範圍第1項之方法，其中形成該間隔包含： 於包含該接觸孔之合成結構之表面上方形成間隔用之絕 -12- 200910520 緣層；及 移除在該接觸孔之底部，該間隔用之絕緣層。 7 .如申請專利範圍第6項之方法，其中該間隔用之絕緣層 係由氧化物系層製成。 8 .如申請專利範圍第7項之方法，其中該間隔用之絕緣層 包含03 -未摻雜矽酸鹽玻璃（USG)層、電漿強化四乙氧基 矽酸鹽（PETEOS)層、硼磷矽酸鹽玻璃（BPSG)層' 磷矽酸 鹽玻璃（PSG)層、或其組合。 9 .如申請專利範圍第7項之方法，其中間隔用之該絕緣層 的厚度從約1 〇 〇 A到約9 9 9 A的範圍。 1 〇.如申請專利範圍第6項之方法，其中藉由覆蓋（blanket) 乾式飩刻製程，實施移除在該接觸孔之底部，該間隔用 之絕緣層。 i i .如申請專利範圍第7項之方法，其中形成該間隔更包含 在移除在該接觸孔之底部，該間隔用之絕緣層後，實施 平坦化製程。 1 2 .如申請專利範圍第6項之方法，其中使用接觸式化學機 械硏磨（CMP)法來實施該平坦化製程。 i 3 .如申請專利範圍第1 2項之方法，其中實施該接觸式CMP 法，具有約500A到約1 500A範圍之硏磨區。 1 4 .如申請專利範圍第1項之方法，其中該接觸孔具有臨界 尺寸（CD)，其被選擇以致使該接觸孔不侵入任何鄰近的 接觸孔上。 1 5 .如申請專利範圍第1項之方法，其中在形成該間隔後， 更包含以導電材料塡充該接觸孔而形成接觸部。200910520 X. Patent application scope: 1 . A method for manufacturing a semiconductor device, the method comprising: disposing a substrate; forming an insulating layer over the substrate; forming a photoresist pattern for the contact hole over the insulating layer, wherein the photoresist pattern comprises an opening, Having a critical dimension (CD) greater than a desired contact critical dimension (CD); forming a contact hole by selectively etching the insulating layer using the photoresist pattern; and forming a space on a sidewall of the contact hole until the contact hole The CD is reduced to the desired contact CD where the sidewalls of the contact hole are covered by the spacing. 2. The method of claim 1, wherein the desired contact C D is a C D defined by a design rule for the semiconductor component. 3. The method of claim 1, wherein the substrate comprises a bit line having a bit line conductive layer and a bit line hard mask layer sequentially formed under the insulating layer, and forming a contact hole The bit line conductive layer is exposed by etching the insulating layer and the bit line hard mask layer. 4. The method of claim 1, further comprising forming a hard mask layer over the insulating layer prior to forming the photoresist pattern. 5. The method of claim 4, wherein the hard mask layer patterned by the photoresist pattern is used to effect formation of the contact hole. 6. The method of claim 1, wherein forming the spacer comprises: forming a spacer layer -12-200910520 over the surface of the composite structure including the contact hole; and removing the bottom layer of the contact hole , the insulation layer used for the interval. 7. The method of claim 6, wherein the insulating layer for the spacer is made of an oxide layer. 8. The method of claim 7, wherein the insulating layer of the spacer comprises a layer of 03-undoped tantalate glass (USG), a layer of plasma-reinforced tetraethoxyphthalate (PETEOS), boron Phosphonite glass (BPSG) layer 'phosphorite glass (PSG) layer, or a combination thereof. 9. The method of claim 7, wherein the insulating layer has a thickness ranging from about 1 〇 〇 A to about 9 9 A. The method of claim 6, wherein the insulating layer is removed at the bottom of the contact hole by a blanket engraving process. The method of claim 7, wherein the forming the interval further comprises performing a planarization process after removing the insulating layer at the bottom of the contact hole. The method of claim 6, wherein the planarization process is carried out using a contact chemical mechanical honing (CMP) method. The method of claim 12, wherein the contact CMP method is carried out, and the honing zone has a range of about 500 A to about 1 500 Å. The method of claim 1, wherein the contact hole has a critical dimension (CD) selected such that the contact hole does not intrude into any adjacent contact hole. The method of claim 1, wherein after forming the interval, further comprising filling the contact hole with a conductive material to form a contact portion.
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