KR100571652B1 - Method for fabrication of semiconductor device capable of forming fine pattern - Google Patents

Abstract

An object of the present invention is to provide a method for manufacturing a semiconductor device to which an ArF photolithography process can be applied, which can prevent a lifting phenomenon of a hard mask by wet cleaning. To this end, the present invention, by placing an insulating nitride film between the photoresist pattern (anti-reflective film) and the interlayer insulating film as an etched layer when forming a contact hole pattern to use as a hard mask, an ultrafine pattern for applying an ArF exposure source to a photolithography process Prevents pattern deformation in the forming process, improves productivity by shortening process time by allowing insulating hard mask etching process and interlayer insulating film etching process in the same chamber, and insulating hard mask in SAC etching and plug forming process This increases the choice with the substrate, enabling the SEG process to be applied during the deposition of plug material.

In addition, the present invention is to planarize the interlayer insulating film to the gate hard mask after the deposition of the interlayer insulating film, and to form a hard mask on the planarized upper surface to make the gate hard mask and the hard mask of the same material contact with the nitride film-based material film, interlayer insulating film By reducing the etching target due to the SAC etching process margin, and also to prevent the lifting phenomenon of the hard mask due to the separation of the interface between the interlayer insulating film and the hard mask, which is different from each other in the wet cleaning before the plug material deposition. .

Argon fluoride (ArF), nitride film, hard mask, lifting, planarization, line pattern, hole pattern.

Description

TECHNICAL FOR FABRICATION OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING FINE PATTERN}             

1A-1D are cross-sectional views illustrating a landing plug contact forming process according to the prior art.

2 is a SEM photograph showing the deformation of the ArF photoresist pattern generated in the LPC formation process.

Figure 3 is a SEM photograph showing the loss of the gate hard mask in the LPC formation process applying the ArF process technology.

4 is a SEM photograph showing a phenomenon in which a pattern collapses in an LPC forming process to which an ArF process technology is applied.

5A to 5F are sectional views showing a pattern forming process of a semiconductor device using an ArF exposure source according to the improved prior art.

6 is a SEM photograph for explaining the lifting phenomenon of the hard mask generated after the wet cleaning process.

7A to 7G are cross-sectional views illustrating a pattern forming process of a semiconductor device using an ArF exposure source according to an embodiment of the present invention.

8A and 8B illustrate changes in thicknesses and TEM photographs of respective material films during the SAC process when the thickness of the hard mask is set to 670 kPa.

9A and 9B illustrate changes in thicknesses and TEM photographs of respective material layers during the SAC process when the thickness of the hard mask is 900 mW;

10A and 10B are diagrams illustrating changes in the thickness of each material film and a TEM photograph during the SAC process when the thickness of the hard mask is 1000 mW.

FIG. 11 is a graph showing changes in the thickness of each material film during the SAC process when the thickness of the hard mask is set to 1150 GPa; FIG.

Explanation of symbols on the main parts of the drawings

70 substrate 71 gate insulating film

72: gate conductive film 73: gate hard mask

74: impurity diffusion region 75, 75a: etch stop film

76: interlayer insulating film 83: plug

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern of 80 nm or less using an ArF photolithography process using a nitride film as a hard mask. .

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices, for example, transistors and capacitors. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties have arisen in the manufacturing process of the semiconductor devices forming the cell.

In the case of applying a photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the etching process is performed in accordance with the conventional etching process concept (exact pattern formation and vertical etching profile, etc.). There is a need for additional requirements of suppression of deformation of the resulting photoresist. Accordingly, when manufacturing a semiconductor device of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the high integration of semiconductor devices is accelerated, various elements of the semiconductor devices have a stacked structure, and thus, a contact plug (or pad) concept has been introduced.

In forming such a contact plug, a landing plug contact is known as having a larger area at the upper part than the lower part contacted to increase the contact area with a minimum area at the lower part and to increase the process margin for subsequent processes at the upper part. ) Technology has been introduced and commonly used.

<Private Technology>

1A to 1D are cross-sectional views illustrating a landing plug contact forming process according to the prior art.

First, as shown in FIG. 1A, a gate hard mask 13 / gate conductive film 12 / gate insulating film 11 is formed on a semiconductor substrate 10 on which various elements for forming a semiconductor device, for example, a field insulating film and a well, are formed. ) Are stacked to form the gate electrode patterns G1 and G2.

The gate insulating film 11 uses a conventional oxide-based material film such as a silicon oxide film, and the gate conductive film 12 usually uses polysilicon, W, WN, WSi _x, or a combination thereof.

The gate hard mask 13 is used to protect the gate conductive layer 12 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation, and the etching speed is significantly different from that of the interlayer insulating layer. Use For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

An impurity diffusion region 14 such as a source / drain junction is formed in the substrate 10 between the gate electrode patterns G1 and G2.

In general, when the source / drain junction region is formed between the gate electrode patterns G1 and G2 through ion implantation, impurities are implanted into the substrate 10 through ion implantation so as to be aligned with the gate electrode patterns G1 and G2. Next, spacers are formed on sidewalls of the gate electrode patterns G1 and G2 and ion implantation is performed again to form a lightly doped drain (LDD) structure. Here, the LDD structure and the spacer forming process are omitted.

An etch stop layer acts as an etch stop to prevent attack of the substrate 10 in an etching process using a subsequent self-aligned contact (SAC) method on the entire surface where the gate electrode patterns G1 and G2 are formed. (15) is formed. In this case, the etch stop film 15 may be formed along the profiles of the gate electrode patterns G1 and G2, and a nitride film-based material film is used.

Next, as shown in FIG. 1B, an oxide-based interlayer insulating film 16 is formed on the entire structure where the etch stop film 15 is formed.

When the interlayer insulating film 16 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, BPSG (Boro-Phopho-Silicate-Glass) film, PSG (Phospho-Silicate-Glass) film, TEOS (Tetra) -Ethyl-Ortho-Silicate (HDP) film, HDP (High Density Plasma) film, or SOG (Spin On Glass) film, etc. may be used. In addition to the oxide film, an inorganic or organic low dielectric constant film may be used.

Subsequently, a photoresist pattern 17 for forming an LPC is formed on the interlayer insulating film 16. An anti-reflection film is usually used between the photoresist pattern 17 and the interlayer insulating film 16, but is omitted here for the sake of simplicity.

Subsequently, as shown in FIG. 1C, the interlayer insulating layer 16 and the etch stop layer 15 are etched using the photoresist pattern 17 as an etch mask to diffuse impurities between two adjacent gate electrode patterns G1 and G2. The contact hole 18 exposing the region 14 is formed.

The above-mentioned contact hole 18 forming process is generally a SAC etching process using an etching selectivity of the interlayer insulating film 16 and the gate hard mask 13. The photoresist pattern 16 is commonly used as an etch mask. ) And the process of exposing the substrate 10 (specifically, the impurity diffusion region 14) by removing the etch stop layer 15 by etching the etch stop layer 15 by etching. It is divided into the cleaning process to remove the etching residues by expanding the opening of the). In such an etching process, CxFy (x, y is 1 to 10) gas, such as CF ₄ , and CaHbFc (a, b, c is 1 to 10) gas, such as CH ₂ F ₂ , are mixed and used.

Meanwhile, as the high integration increases, the vertical heights of the gate electrode patterns G1 and G2 increase, and thus, an excessive use of the etching gas and an increase in the etching time are inevitable when the SAC etching corresponds to the increased etching target. This results in loss of the gate hard mask 13 as shown by reference numeral 19 in FIG. 1C.

The photoresist pattern 17 is removed through an ashing process. When an organic material is used as the antireflection film, the photoresist pattern 17 is removed like the photoresist pattern 17 in the ashing process.

Subsequently, as shown in FIG. 1D, a conductive material for forming a plug is deposited on the entire surface where the contact hole 18 is formed to sufficiently fill the contact hole 18, and then to a target to which the gate hard mask 13 is exposed. The planarization process is performed to form a plug 20 electrically connected to the impurity diffusion region 14 through the contact hole 18 and having the gate hard mask 13 and the upper portion flattened.

The most commonly used material for forming the plug 20 is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and may also use tungsten.

Meanwhile, since the gate hard mask 13 is lost during the SAC process in FIG. 1C described above, not only the insulation property between the plug 20 and the gate conductive layer 12 is degraded, but also the loss of the gate hard mask 13 is reduced. When the gate conductive layer 12 is severely exposed, an electrical short circuit occurs between the plug 20 and the gate conductive layer 12 as shown by reference numeral 21 of FIG. 1D.

As described above, the loss of the gate hard mask 13 is inevitable in the LPC forming process due to the high integration of semiconductor devices. In addition, since the thickness of the photoresist pattern must also be reduced in order to achieve high resolution, this significantly reduces the function of the photoresist pattern as a mask in the etching process. Therefore, in order to overcome this problem, a technology using a hard mask is introduced between the photoresist pattern (antireflection film when using an antireflection film) and the etching layer, and a photo using a laser such as KrF (chromium fluoride) or ArF as an exposure source. Tungsten and polysilicon are widely used in the lithography process and are being studied and used as materials for such hard masks.

The photoresist for ArF is still commercially available and includes a polymer form of COMA (CycloOlefin-Maleic Anhydride) or Acrylate system, or a mixture thereof.

However, as is well known, the photolithography process using the ArF exposure source has an advantage of being suitable for miniaturization, but there are various disadvantages compared to the KrF photolithography process technology.

2 is a SEM (Scanning Electron Microscopy) photograph showing the deformation of the ArF photoresist pattern generated in the LPC formation process, Figure 3 is a SEM photograph showing the loss of the gate hard mask in the LPC formation process using the ArF process technology, FIG. 4 is a SEM photograph illustrating a phenomenon in which a pattern collapses in an LPC forming process to which an ArF process technology is applied.

Referring to FIG. 2, it can be seen that in the LPC forming process to which the ArF photolithography process is applied, striation occurs as shown in 'A' when the etching process is performed to form a pattern. This is due to the above-mentioned characteristics of the photoresist for ArF, which is generated due to the weak etching resistance to the fluorine-based gas mainly used in the etching process for forming LPC.

Referring to FIG. 3, it can be seen that after the SAC etching process for forming the LPC, a loss of a gate hard mask of 800 Å or more occurred as shown in 'B'.

Referring to (a) of FIG. 4, it can be seen that the bar-shaped ArF photoresist pattern for forming LPC collapses as shown in 'C', causing device defects. Referring to FIG. 3, it can be seen that a pattern defect occurs at a weak point of the ArF photoresist pattern as illustrated in 'D'.

The existing requirements in the LPC formation process, such as minimizing gate hardmask loss and ensuring sufficient contact area during SAC etching of interlayer dielectrics, are based on the ArF photolithography process and trade-off process to avoid pattern deformation. As it is a trade-off relationship, as the process parameters such as electrode temperature and power are changed, the pattern deformation and the existing requirements are reversed to each other, reducing the process margin. This results in difficulty in setting up process conditions.

For example, when the photolithography process using the KrF exposure source is applied, it is preferable to maintain the electrode temperature at about 60 ° C. during the SAC etching process for forming the LPC. However, when applying the photolithography process using the ArF exposure source, the SAC is applied. If the temperature of the electrode is maintained at about 60 ° C. during the etching process, the photoresist pattern is deformed during etching, so the temperature of the electrode should be maintained at about 0 ° C. When the temperature of the electrode is kept low, the deformation of the photoresist pattern is suppressed, but this causes a decrease in the etching selectivity between heterogeneous layers, for example, oxide and nitride layers, which are relatively the core of the SAC etching process.

When the SAC etching process is performed under the same conditions, it can be seen that the gate hard mask loss of about 200 GPa or more occurs when the ArF process is applied, compared with the KrF process. On the other hand, if the thickness of the gate hard mask is increased to compensate for the loss of a relatively large gate hard mask, the vertical height of the gate electrode pattern is increased to increase the aspect ratio corresponding to the gap between the height of the gate electrode pattern and the gate electrode pattern ( Increasing the aspect ratio will adversely affect the gap-fill characteristics and the contact area of the interlayer dielectric.

In addition, to compensate for the loss of the gate hard mask, a capping of the upper part of the gate hard mask is performed by using an undoped Silicate glass (USG) film having poor step coverage. The method was devised. As described above, securing the gate hard mask using the capping method is difficult to control the thickness of the oxide layer (interlayer insulating layer) inside the contact, which is a main culprit for contact not open for some contacts even in the existing KrF process. However, it is necessary to omit this capping method in order to form a competitive LPC structure for actual production.

The LPC formation process using the ArF photolithography process itself has problems such as weakness in pattern formation due to relatively thin photoresist thickness and poor etching resistance, and collapse of pattern due to increased aspect ratio. .

In order to overcome these problems, as described above, a hard mask using tungsten or polysilicon is used between the photoresist pattern and the etched layer.

When the process of using tungsten as a hard mask is briefly described, an etch stop film and an interlayer insulating film are formed on the entire surface where the gate electrode pattern is formed, a tungsten film is deposited on the interlayer insulating film, and a photoresist pattern is formed. After etching the tungsten film using the resist pattern as an etch mask to form a tungsten hard mask, the photoresist pattern is removed, and the tungsten hard mask is etched with an etch mask to etch the interlayer insulating layer and the etch stop layer, and then the tungsten hard mask is removed. After performing the cleaning process, the LPC process is completed by depositing a plug forming material and forming a plug through a planarization process.

By using a hard mask such as tungsten or polysilicon, the thickness of the photoresist can be lowered, thereby improving light sensitivity during exposure, loss of contact and loss of gate hard mask, which is a problem in the LPC process, as well as pattern deformation, which is a problem in the ArF process. Problems such as reduction of the area could be solved.

However, since both tungsten and polysilicon are conductive materials, a process of removing them is necessary. In addition, the process of etching such a conductive material and the process of etching an insulating interlayer insulating film must be performed in different chambers during the SAC etching process. The process takes a lot of time and causes a secondary problem such as contamination due to particles due to movement. These problems are not only a cathode pattern forming process such as an SAC etching process, but also a gate electrode pattern, a bit line, or a metal wiring. The same problem occurs in the anode pattern forming process.

In addition, in the case of the LPC process, the selectivity of the exposed silicon substrate and the insulating film (ie, interlayer insulating film), such as selective epitaxial growth (SEG), which is frequently used after contact hole formation, is used. It is not suitable for application in the technology of growing plug material. This is because tungsten and polysilicon have no selectivity with the substrate.

<Improved Prior Art>

Therefore, in order to overcome the problems caused by the use of tungsten or polysilicon, a nitride film is applied as a hard mask, and FIGS. 5A to 5F illustrate a process of forming a pattern of a semiconductor device using an ArF exposure source according to the improved prior art. As sectional drawing, it demonstrates in detail with reference to this.

First, as shown in FIG. 5A, a gate hard mask 53 / gate conductive film 52 / gate insulating film 51 is formed on a semiconductor substrate 50 on which various elements for forming a semiconductor device, for example, a field insulating film and a well, are formed. ) Are stacked to form the gate electrode patterns G1 and G2.

The gate insulating film 51 uses a conventional oxide film material film such as a silicon oxide film, and the gate conductive film 52 is made of polysilicon, tungsten (W), tungsten nitride film (WN _x ), tungsten silicide (WSi _x ), or the like. Use alone or in combination thereof.

The gate hard mask 53 is to prevent the gate conductive layer 52 from being attacked in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for the subsequent contact formation, and the interlayer insulating layer and the etching speed are remarkably increased. Different materials are used. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

An impurity diffusion region 54 such as a source / drain junction is formed in the substrate 50 between the gate electrode patterns G1 and G2.

When source / drain junction regions are formed between the gate electrode patterns G1 and G2 through ion implantation, impurities are implanted into the substrate 50 through ion implantation so as to be aligned with the gate electrode patterns G1 and G2. Next, spacers are formed on the sidewalls of the gate electrode patterns G1 and G2 and ion implantation is performed again to form an LDD structure. Here, the LDD structure and the spacer forming process are omitted.

An etch stop layer 55 may be formed on the entire surface where the gate electrode patterns G1 and G2 are formed to serve as an etch stop to prevent attack of the substrate 50 in a subsequent SAC etching process. In this case, the etch stop film 55 may be formed along the profiles of the gate electrode patterns G1 and G2. The etch stop film 55 may be formed of a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film. I use it.

Next, as shown in FIG. 5B, an oxide-based interlayer insulating film 56 is formed on the entire structure where the etch stop film 55 is formed.

When the interlayer insulating film 56 is used as an oxide-based material film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, or an SOG film may be used. In addition to the oxide film, an inorganic or organic low dielectric constant film may be used. have.

Subsequently, a nitride layer 57 for a hard mask, which is an insulating material and has an etching selectivity with the interlayer insulating layer 56, is used as a hard mask material. The nitride film 57 for hard mask includes a nitride film using plasma enhanced chemical vapor deposition method, a nitride film using PE-nitride film or low pressure chemical vapor deposition method, or an LP-nitride film. The deposition thickness is preferably used in consideration of both the amount of loss generated during subsequent SAC etching of the interlayer dielectric layer 56 and the amount lost when the impurity diffusion region 54 is exposed by etching the etch stop layer 55. It is preferable to make the etching stop film 55 (together two lost amounts) or more so that it can be naturally removed in-situ during etching.

When the exposure for forming the pattern on the hard mask nitride film 57 is increased, that is, the light reflectivity of the lower mask nitride film 57 is increased to prevent diffuse reflection and prevent unwanted patterns from being formed, and the nitride film 57 for hard mask is formed. ) And the antireflection film 58 is formed for the purpose of improving the adhesion between the photoresist and the subsequent photoresist.

Here, the anti-reflection film 58 is preferably made of an organic material similar to the photoresist and the etching characteristics thereof. On the other hand, the use of the antireflection film 58 may be omitted depending on the process.

Subsequently, a photoresist for an ArF exposure source is applied on the antireflection film 58 to an appropriate thickness by a method such as spin coating, and then a predetermined reticle (not shown) for defining the width of the ArF exposure source and the contact hole is applied. Photoresist for LPC formation by selectively exposing a predetermined portion of the photoresist, leaving the exposed or unexposed portions through the developing process, and then removing the etch residues through a post-cleaning process. The resist pattern 59 is formed.

In FIG. 5B, a process cross section in which a photoresist pattern 59 defining a region C / T in which contact holes are formed for forming an LPC is formed.

On the other hand, in the method of using tungsten or polysilicon as the material for the hard mask, since the reflectivity of the material itself is high, a big problem in reading the overlay is revealed, and a separate alignment key opening process is required for mask alignment. In the case of nitride film, since reflectivity is very low compared to tungsten and polysilicon, there is no great difficulty in mask alignment.

Since the thickness of the photoresist for pattern formation is only about the thickness of etching the thin mask 57 for hard mask, the thickness of the photoresist is thinner than the case of using no hard mask or using polysilicon or tungsten hard mask. It is also possible to use a resist, which improves the fine ability at the time of pattern formation, thereby enabling the formation of a fine pattern without the collapse of the pattern.

Subsequently, as shown in FIG. 5C, the antireflection film 58 and the hard mask nitride film 57 are etched using the photoresist pattern 59 as an etch mask to form a hard mask 57a.

The photoresist pattern 59 is removed through an ashing process. When an organic material is used as the antireflection film 58, the photoresist pattern 59 is removed like the photoresist pattern 59 in the ashing process. The ashing process includes a photoresist strip process or O ₂ plasma treatment carried out in a conventional photoresist strip apparatus.

On the other hand, if the photoresist pattern 59 remains, it may cause a pattern defect in a subsequent SAC etching process, so it should be removed.

Subsequently, as shown in FIG. 5D, the etch stop layer 55 between two neighboring gate electrode patterns G1 and G2 is etched by etching the interlayer insulating layer 56 as an etched layer using the hard mask 57a as an etch mask. The contact hole 61 is formed by performing an SAC etching process 60 that exposes it.

At this time, since the etching of the interlayer insulating film 56 does not have to consider the deformation of the photoresist pattern, it has the characteristic of SAC that maximizes the selectivity with the hard mask 57a and sufficiently secures the bottom CD of the contact hole 61. Apply the recipe.

SAC process using a conventional photoresist pattern as an etch mask is performed even if the loss of the gate hard mask 53 of about 300 GPa generated in the subsequent etching stop layer 55 is added due to the drastic reduction of the loss of the gate hard mask 53. It is improved compared with the case of carrying out. This further eliminates the need to protect the gate hard mask 53 by forming a capping layer on the gate electrode patterns G1 and G2 using a USG film or the like. That is, the formation process of the capping layer can be omitted.

Although the omission of the capping layer forming process is a side of the process simplification, due to the irregular thickness deposited inside the contact hole when the capping layer is formed, the etch stop layer 55 for the contact opening may prevent the contact sick opening phenomenon mainly generated during the etching process. To be able. In the case of a device having a minimum line width of about 100 nm in which a capping layer is actually applied, control failure of the capping layer process frequently occurs. To solve this problem, the thickness of the capping layer and wet cleaning Careful control is required.

In addition, in a device having a design rule of 80 nm or less, a capping layer forming process may cause problems such as over-hang, and thus it may not be applied to an actual process. Therefore, the omission of the capping layer may be essential in devices of 80 nm or less.

Subsequently, as shown in FIG. 5E, the etch stop layer 55 is removed to expose the substrate 50, specifically, the impurity diffusion region 54.

The etching of the etch stop film 55 uses a blanket etch as shown by the reference numeral '62', and at this time, the etching stop film 55 is about 300 kV, which is almost equal to the amount of the etch stop film 55 at the bottom of the contact hole 61. The gate hard mask 53 is lost, resulting in the loss of the gate hard mask 53 of about 600 kV to 700 kPa.

By using an insulating nitride film as the hard mask 57a, it is possible to proceed a series of LPC formation processes in-situ on the same equipment. For example, in the case of a two chamber body equipped with a photoresist stripper, a hard mask is formed by etching a nitride film for a hard mask by an ArF photolithography process, followed by a photoresist strip process, and then in another chamber. It is possible to perform a SAC etching process and an etch stop film etching process.

This can solve the disadvantage of having to etch between different equipment to etch the conductive hard mask when using a conductive material such as polysilicon or tungsten as a hard mask, and greatly help in reducing TAT (Turn Around Time) when mass production is applied. This can be

Subsequently, as shown in FIG. 5F, a plug forming conductive material is deposited on the entire surface of the substrate 50 on which the contact hole 61 is formed to sufficiently fill the contact hole 61, and then the gate hard mask 33 is formed. A planarization process is performed on the exposed target to form a gate 63 electrically connected to the impurity diffusion region 54 through the contact hole 61 and a planarized plug 63 with the gate hard mask 53.

In the planarization process, an etching back process is performed on the plug material to reduce the step difference between the cell region and the peripheral circuit region of the memory for chemical mechanical polishing (hereinafter referred to as CMP). On the other hand, the hard mask (57a) can be left in the upper portion of the peripheral circuit region, which controls the deposition thickness of the nitride film for the hard mask to be deposited thicker in the peripheral circuit region, or when removing the etch stop layer (55) The hard mask 57a may be left in the peripheral circuit region by removing the etch stop layer by using a mask (cell open mask) that opens only the cell region without performing blanket etching.

The reason why the hard mask 57a remains in the peripheral circuit region is that a pattern isolated from the peripheral circuit region, for example, a gate electrode pattern or the like, may be caused by a pattern density difference between the cell region and the peripheral circuit region during the subsequent CMP process. This is to prevent attack. In fact, as a result of performing the CMP process by remaining the hard mask 57a in the peripheral circuit region, it is possible to prevent attack on the gate electrode pattern in the peripheral circuit region, thereby increasing the margin of the CMP process.

Subsequently, a part of the interlayer insulating film 56 may be left according to the type of mask pattern used without necessarily having to align the polishing target with the gate hard mask 53 during planarization through the CMP process.

The most commonly used material for forming the plug 63 is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and may also use tungsten.

In recent years, when forming the plug 63, in addition to the above-described deposition process, many SEG processes are also applied.

Due to the use of an insulating nitride film as the hard mask 57a, a growth method such as SEG may be applied as well as a method of depositing polysilicon deposition in the plug 63 forming process of the SEG method. When tungsten or polysilicon is used as the hard mask 57a, when the SEG method is applied, the selectivity between the impurity diffusion region 54 and the hard mask 57a of the exposed substrate 50 is lost and the hard mask 57a is lost. Since the problem of growing silicon also occurs in the prior art, since the hard mask 57a must be removed before the SEG process is applied, there is a process inconvenience. However, since the nitride film is used as the hard mask 57a, it is not necessary to remove the hard mask 57a even when the SEG process is applied. Therefore, there is an advantage that can be applied regardless of the plug forming process to the process of 80nm or less.

Incidentally, in the conventional case using the deposition method of the plug material, the plug seam is generated depending on the profile of the interlayer insulating film 56. However, in the improved conventional technology, the interlayer insulating film (using the hard mask 57a) is used. By improving the profile of 56), it is possible to prevent the occurrence of plug shims. This is due to the deposition of the capping layer and wet cleaning, whereas the profile of the interlayer insulating film 56 caused seams in the deposition assumption of the plug material, whereas the profile of the interlayer insulating film 56 is slightly positive in the improved art. This is because it suppresses seam generation.

On the other hand, as described above, it is preferable to calculate the thickness of the hard mask to the thickness lost during the SAC etching and the thickness lost during the removal of the etch stop layer, but in practice, it is generally difficult to accurately control the thickness of the hard mask. The mask is made thicker and the remaining hard mask after removing the etch stop film is removed in the planarization process for plug isolation.

As such, the hard mask remaining after removing the etch stop layer causes a problem in the wet cleaning process performed to secure the CD on the bottom of the contact.

6 is a SEM photograph for explaining a lifting phenomenon of the hard mask generated after the wet cleaning process.

Referring to FIG. 6, a plurality of gate electrode patterns G1 to G4 are arranged at regular intervals, and mask patterns P1 to P4 for forming line-shaped LPCs in a direction crossing the gate electrode patterns G1 to G4. ) Is arranged. The mask patterns P1 to P4 have a structure in which an interlayer insulating film and a hard mask are stacked, and a plurality of contact holes are formed between the gate electrode patterns G1 to G4 after etching the SAC and the etch stop layer using the mask patterns P1 to P4. As formed, the relatively small size represents the contact hole SNC for the subsequent storage node contact, and the relatively large size compared to the contact hole SNC represents the contact hole BLC for the subsequent bit line contact.

However, the relatively weak interface between the hard mask and the interlayer insulating film remaining in the cleaning process using a wet solution such as BOE (Buffered Oxide Etchant), which forms contact holes such as SNC and BLC, and deposits a plug forming material film prior to deposition or growth. Separation phenomenon occurs at.

The phenomenon that the hard mask is lifted due to the separation between the two membranes occurs, and 'HM1' and 'HM2' in the lower left portion of FIG. 6 indicate a lifted hard mask. The lifting phenomenon of the hard mask occurs more frequently, especially in the case of memory devices, when the hard mask remains in the peripheral circuit area.

This lifting problem is also closely related to the size of the pattern, so that the smaller the contact area, the more easily occurs. Therefore, there may be a greater problem in the implementation of the technology of 80nm or less.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device using an ArF photolithography process capable of preventing a lifting phenomenon of a hard mask by wet cleaning.

In order to achieve the above object, the present invention includes the steps of forming a plurality of conductive patterns adjacent to each other having a first hard mask nitride film / conductive film structure on a substrate having a cell region and a peripheral circuit region; Forming an etch stop layer along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on an entire surface of the substrate on which the etch stop film is formed; Removing and planarizing the interlayer insulating layer and the etch stop layer until an upper portion of the first hard mask nitride layer is exposed; Forming a second hard mask nitride film on the exposed first hard mask nitride film and the interlayer insulating film; Forming an anti-reflection film on the second hard mask nitride film; Forming a photoresist pattern on the anti-reflection film through a photolithography process using an ArF exposure source; Selectively etching the anti-reflection film and the second hard mask nitride layer using the photoresist pattern as an etching mask to form a hard mask; Removing the photoresist pattern and the anti-reflection film; Forming a contact hole exposing the etch stop layer by etching the interlayer insulating layer between the adjacent conductive patterns using the hard mask as an etch mask; Removing the etch stop layer on the bottom of the contact hole to expose the substrate; And cleaning the inside of the contact hole.

According to the present invention, an ultra-fine pattern forming process for applying an ArF exposure source to a photolithography process is performed by placing an insulating nitride film between a photoresist pattern (anti-reflective film) and an interlayer insulating film as an etched layer when forming a contact hole pattern and using it as a hard mask. Prevents pattern deformation, improves productivity by shortening process time by allowing insulating hard mask etching process and interlayer insulating film etching process in the same chamber, and insulated hard mask in SAC etching and plug forming process The selection with the substrate is increased to enable application of the SEG process in the deposition of plug material.

In addition, the present invention is to planarize the interlayer insulating film to the gate hard mask after the deposition of the interlayer insulating film, and to form a hard mask on the planarized upper surface to make the gate hard mask and the hard mask of the same material contact with the nitride film-based material film, interlayer insulating film By reducing the etching target due to the SAC etching process margin, and also to prevent the lifting phenomenon of the hard mask due to the separation of the interface between the interlayer insulating film and the hard mask, which is different from each other in the wet cleaning before the plug material deposition. .

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

7A to 7G are cross-sectional views illustrating a pattern forming process of a semiconductor device using an ArF exposure source according to an embodiment of the present invention, which will be described in detail with reference to the drawings.

In an embodiment of the present invention described below, a process of forming a space pattern, for example, a contact hole pattern, of a semiconductor device is described as an example. The contact hole pattern to which the present invention is applied is a metal wiring contact and a bit. The present invention can be applied to a process for forming a contact pad and contact with an impurity bonding layer in a substrate such as a source / drain junction for a storage node contact of a line or a capacitor.

First, as shown in FIG. 7A, a gate hard mask 73 / gate conductive film 72 / gate insulating film 71 is formed on a semiconductor substrate 70 on which various elements for forming a semiconductor device, for example, a field insulating film and a well, are formed. ) Are stacked to form the gate electrode patterns G1 and G2.

The gate insulating film 71 uses a conventional oxide film material film such as a silicon oxide film, and the gate conductive film 72 is made of polysilicon, tungsten (W), tungsten nitride film (WN _x ), tungsten silicide (WSi _x ), or the like. Use alone or in combination thereof.

The gate hard mask 73 is to prevent the gate conductive layer 72 from being attacked in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation, and the interlayer insulating layer and the etching speed are remarkably increased. Different materials are used. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

An impurity diffusion region 74 such as a source / drain junction is formed in the substrate 70 between the gate electrode patterns G1 and G2.

When source / drain junction regions are formed between the gate electrode patterns G1 and G2 through ion implantation, impurities are implanted into the substrate 70 through ion implantation so as to be aligned with the gate electrode patterns G1 and G2. Next, spacers are formed on the sidewalls of the gate electrode patterns G1 and G2 and ion implantation is performed again to form an LDD structure. Here, the LDD structure and the spacer forming process are omitted.

An etch stop layer 75 is formed on the entire surface where the gate electrode patterns G1 and G2 are formed to serve as an etch stop to prevent attack of the substrate 70 in a subsequent SAC etching process. In this case, the etch stop film 75 may be formed along the profiles of the gate electrode patterns G1 and G2. The etch stop film 75 may be formed of a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film. I use it.

Next, an oxide-based interlayer insulating film 76 is formed on the entire structure where the etch stop film 75 is formed.

When the interlayer insulating film 76 is used as an oxide-based material film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, or an SOG film may be used. In addition to the oxide film, an inorganic or organic low dielectric constant film may be used. have.

Subsequently, the interlayer insulating film 76 and the etch stop film 75 are removed until the gate hard mask 73 is exposed to substantially planarize the gate hard mask 73 and the interlayer insulating film 76.

In this case, the CMP process is applied, and the amount of loss of the gate hard mask 73 is minimized to 100 μm or less, and the gate hard mask 73 and the interlayer insulating film remaining by the use of an appropriate polishing slurry are used. It is important that the bending of 76) does not occur.

FIG. 7B shows a process cross section in which the gate hard mask 73 and the interlayer insulating film 76 are planarized through a CMP process.

Subsequently, a nitride layer 77 for a hard mask, which is an insulating material and has an etching selectivity with the interlayer insulating film 76, is used as a hard mask material. For the hard mask nitride film 77, a PE-nitride film or an LP-nitride film is preferably used, and the deposition thickness thereof is an impurity by etching the etch stop film 75 and the amount of loss generated during the subsequent SAC etching of the interlayer insulating film 76. Considering all the amounts lost when exposing the diffusion region 74 (together, the amounts lost), the etch stop layer 75 may be at least enough to be naturally removed in-situ during etching. .

For example, in the preferred embodiment of the present invention, considering the 300 Å at the time of SAC etching and the 300 Å at the time of etching stop film 75, the thickness of 500 Å to 800 ((for devices of 100 nm or less) is applied. (Reticle) or may vary depending on the device.

When the exposure for pattern formation on the hard mask nitride film 77 is performed, the light reflectivity of the lower portion, that is, the hard mask nitride film 77 is increased, thereby preventing unwanted reflections from being formed and forming a hard mask nitride film 77 ) And the antireflection film 78 is formed for the purpose of improving the adhesion between the photoresist and the subsequent photoresist.

Here, the anti-reflection film 78 preferably uses an organic material similar to the photoresist and the etching characteristics thereof.

In addition, in this embodiment, but using the anti-reflection film 78 as an example, it may be omitted depending on the process.

Subsequently, a photoresist for an ArF exposure source is applied on the antireflection film 78 to an appropriate thickness by a method such as spin coating, and then a predetermined reticle (not shown) for defining the width of the ArF exposure source and the contact hole is applied. Photoresist for LPC formation by selectively exposing a predetermined portion of the photoresist, leaving the exposed or unexposed portions through the developing process, and then removing the etch residues through a post-cleaning process. The resist pattern 79 is formed.

In FIG. 7C, a process cross section in which a photoresist pattern 79 defining a region C / T in which contact holes are formed for forming an LPC is formed.

On the other hand, in the method of using tungsten or polysilicon as a material for hard mask, since the reflectivity of the material itself is high, it shows a big problem in reading the overlay, requiring a separate alignment key opening process for mask alignment. Reflectivity is very low compared to polysilicon, so there is no great difficulty in mask alignment.

Since the thickness of the photoresist for pattern formation is only about the thickness of etching the thin film of the hard mask nitride film 77, the thickness of the photoresist is thinner than the case of using no hard mask or using polysilicon or tungsten hard mask. It is also possible to use a resist, which improves the fine ability at the time of pattern formation, thereby enabling the formation of a fine pattern without the collapse of the pattern.

Therefore, the present invention can be applied to a manufacturing technique having a minimum line width of 80 nm or less. For example, since the expected thickness of the photoresist in the 80nm technology is 1500Å, the minimum thickness of the photoresist required for etching the nitride film 57 for the hard mask of about 700 예상 is expected to be about 1000 수, and thus it can be sufficiently applied in a process of 80 nm or less.

Subsequently, as shown in FIG. 7D, the anti-reflection film 78 and the hard mask nitride film 77 are etched using the photoresist pattern 79 as an etch mask to form the hard mask 77a.

In the case of applying the ArF photolithography process, in particular, forming a pattern by etching the nitride film in the form of a line is one of the extremely difficult to set up the process recipe. Therefore, it is very important to secure the process conditions for the nitride film of 1000 Å or less. Do.

To this end, in order to etch the nitride film 77 for the hard mask, a recipe that is advantageous for straining and pattern deformation should be applied. The characteristics of the electrode are low temperature, the structure in the equipment is controlled independently of the plasma source and bias, The extremely low bias power is advantageous.

The experimental recipe was obtained by using TEL's SCCM equipment: 'The pressure in the chamber of 50 mTorr, the source power of 1000 W, the bias power of 200 W, the electrode temperature of O ₂ of ₂₀ SCCM and CF ₄ and 0 ° C of 100 SCCM'. Desirability could be obtained through experiments.

The above-described recipe allows the etching of the hard mask nitride film 77 simultaneously with the etching of the organic antireflection film 78 and is important for realizing the hard mask 77a structure of FIG. 7D. In this case, the CD of the hard mask 77a having a bar pattern may be controlled by controlling the etching gas and the etching time, thereby increasing the margin for securing the CD of the bottom of the contact hole through the subsequent SAC etching process.

The photoresist pattern 79 is removed through the ashing process. When the organic material is used as the anti-reflection film 78, the photoresist pattern 79 is removed like the photoresist pattern 79 in the ashing process. The ashing process includes a photoresist strip process or O ₂ plasma treatment performed in a conventional photoresist strip apparatus.

On the other hand, if the photoresist pattern 79 remains, it may cause a pattern defect in a subsequent SAC etching process, so it should be removed.

Subsequently, as shown in FIG. 7E, the etch stop layer 75 between the two adjacent gate electrode patterns G1 and G2 is etched by etching the interlayer insulating layer 76 as an etched layer using the hard mask 77a as an etch mask. The contact hole 81 is formed by performing an SAC etching process 80 that exposes it.

At this time, since the etching of the interlayer insulating film 76 does not have to take into consideration the deformation of the photoresist pattern, the characteristic of SAC that maximizes the selectivity with the hard mask 77a and sufficiently secures the bottom CD of the contact hole 81 is obtained. Apply the recipe you have.

Due to the limited supply of carbon (C) sources by photoresist, the use of a gas with a higher selectivity compared to conventional SAC recipes is essential, and C ₄ F ₆ or C ₅ F rather than conventional C ₄ F ₈ It is preferable to use a gas which generates a large amount of CF ₂ radicals such as ₈ .

In addition, it is required to set the appropriate recipe to secure the CD of the bottom of the contact, which becomes relatively weak due to the use of high selectivity. The set recipe uses a high electrode temperature of about 40 ° C. to improve the selectivity and add O ₂ to secure the CD on the bottom of the contact hole 81.

The experimental SAC recipe was obtained using TEL's SCCM equipment with a pressure of 40 mTorr, source power of 500 W, source power of 1200 W, bias power of 1200 W, C ₅ F ₈ of 7 SCCM, Ar ₂ of 800 SCCM, and O ₂ and 40 ° C. of 5 SCCM. It was obtained through experiments that the recipe 'electrode temperature of' is preferred.

Meanwhile, as shown in FIG. 7B, the interlayer insulating layer 76 is removed to directly contact the hard mask 77a and the gate hard mask 73, so that the etching target is reduced by the thickness of the removed interlayer insulating layer 76. This may increase the margin of the SAC etching process. For example, in the case of the SAC process, the loss of the gate hard mask 73 is 300 mW to 400 mW. However, the gate hard mask 73 can be reduced to about 100 mW to 200 mW due to the reduction of the etching target, and the etching time is reduced.

In addition, for example, the thickness of the interlayer insulating film is reduced by about 1500 mW from 5000 mW to 3500 mW, so that the CD of the bottom surface of the contact hole 81 can be expanded by about 10%.

The SAC process is performed using the photoresist pattern as an etch mask even if the loss of the gate hard mask 73 is increased by about 300 [mu] s resulting from the subsequent etching stop layer 75 etching due to the drastic reduction of the loss of the gate hard mask 73. It can be seen that the improvement compared to the case. This further eliminates the need to protect the gate hard mask 73 by forming a capping layer on the gate electrode patterns G1 and G2 using a USG film or the like. That is, the formation process of the capping layer can be omitted.

Although the omission of the capping layer forming process is a side of the process simplification, due to the irregular thickness deposited inside the contact hole when the capping layer is formed, the etch stop layer 75 for the contact opening may be prevented from occurring mainly during the etching process. To be able. In the case of a device having a minimum line width of about 100 nm in which a capping layer is actually applied, failure of the capping layer process control frequently occurs. To solve this problem, careful control of the capping layer thickness and wet cleaning process is required.

In addition, in a device of 80 nm or less, in which the design rule becomes smaller, the capping layer forming process may have problems such as over-hanging, and thus it may not be applicable to an actual process. Therefore, the omission of the capping layer may be essential in devices of 80 nm or less.

Subsequently, as shown in FIG. 7F, the etch stop layer 75 is removed to expose the substrate 70, specifically, the impurity diffusion region 74.

The etching of the etch stop layer 75 uses a blanket etch as shown by reference numeral '82', and at this time, a gate hard mask having a gate hard mask of about 300 μs which is almost equal to the amount of the etch stop layer 75 at the bottom of the contact hole 81. 73 is lost, and the total loss of the gate hard mask 73 of about 400 GPa to 500 GPa occurs.

As described above, when the etch stop layer 75 is etched, the hard mask 77a remaining on the interlayer insulating layer 76 is preferably removed in-situ. After removing the film 75, the hard mask 77a remains on the gate hard mask 73.

By using an insulating nitride film as the hard mask 77a, it is possible to proceed a series of LPC formation processes in-situ in the same equipment. For example, in the case of a two chamber body equipped with a photoresist stripper, a hard mask is formed by etching a nitride film for a hard mask by an ArF photolithography process, followed by a photoresist strip process, and then in another chamber. It is possible to perform a SAC etching process and an etch stop film etching process. In this case, the substrate 70 having the photoresist pattern 79 formed in FIG. 7D is preferably used in this etching apparatus.

This can solve the disadvantage of having to etch between different equipment in order to etch the conductive hard mask when using a conductive material such as polysilicon or tungsten as a hard mask, and can be a great help in shortening the TAT when mass production is applied.

Subsequently, as shown in FIG. 7G, a conductive material for forming a plug is deposited on the entire surface of the substrate 70 on which the contact hole 81 is formed to sufficiently fill the contact hole 81, and then the gate hard mask 73. The planarization process is performed on the target exposed to form a plug 73 electrically connected to the impurity diffusion region 74 through the contact hole 81 and planarized on the gate hard mask 73.

In the planarization process, an etch back process is performed on the plug material to reduce the step difference between the cell region and the peripheral circuit region of the memory for CMP. On the other hand, the hard mask (77a) can be left on the upper peripheral circuit region, which is to control the deposition thickness of the nitride film for the hard mask to be deposited thicker in the peripheral circuit region, or when removing the etch stop film (75) The hard mask 77a may be left in the peripheral circuit region by removing the etch stop layer by using a mask (cell open mask) that opens only the cell region without performing blanket etching.

The reason why the hard mask 77a remains in the peripheral circuit region is to prevent an attack that may occur in a pattern isolated from the peripheral circuit region, for example, a gate electrode pattern, by a pattern density difference between the cell region and the peripheral circuit region during a subsequent CMP process. To do this. In fact, as a result of performing the CMP process by remaining the hard mask 77a in the peripheral circuit region, the attack on the gate electrode pattern in the peripheral circuit region can be prevented, thereby increasing the margin of the CMP process.

Subsequently, a part of the interlayer insulating film 76 may be left according to the type of mask pattern used without necessarily having to align the polishing target with the gate hard mask 73 during planarization through the CMP process.

The most widely used material for forming the plug 83 is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and may also use tungsten or the like.

Recently, when forming the plug 83, in addition to the above-described deposition process, many SEG processes are also applied.

Due to the use of an insulating nitride film as the hard mask 77a, a growth method such as SEG may be applied as well as a method of depositing polysilicon deposition in the plug 83 forming process of the SEG method. When tungsten or polysilicon is used as the hard mask 77a, when the SEG method is applied, the selectivity between the impurity diffusion region 74 and the hard mask 77a of the exposed substrate 70 is lost and the hard mask 77a is lost. The problem of silicon growing in the

When tungsten or polysilicon is used as the hard mask 77a, the hard mask 77a must be removed before the SEG process is applied. However, since the nitride film is used as the hard mask 77a, it is not necessary to remove the hard mask 77a even if the SEG process is applied. Therefore, there is an advantage that can be applied regardless of the plug forming process to the process of 80nm or less. Incidentally, when a plug material deposition method is used, a plug seam is generated depending on the profile of the interlayer insulating film 76. However, the plug seam is generated by improving the profile of the interlayer insulating film 76 using the hard mask 77a. It can prevent. This is because when the conductive hard mask is used, the profile of the interlayer insulating film 76 is slightly inclined by the deposition of the capping layer and the wet cleaning, whereas the profile of the interlayer insulating film 76 causes seam during the deposition of the plug material. This is because it suppresses the occurrence of seams.

8A and 8B illustrate changes in the thickness of each material film and a TEM photograph when the hard mask thickness is 670 kPa. FIGS. 9A and 9B show the SAC when the hard mask thickness is 900 kPa. FIG. 10A and FIG. 10B illustrate changes in the thickness of each material film and a TEM picture during the SAC process when the thickness of the hard mask is 1000 mW. 11 shows the change of the thickness of each material film during the SAC process when the thickness of the hard mask is 1150 GPa.

Hereinafter, with reference to FIGS. 8A to 11, the characteristics according to the change in the thickness of the hard mask described above will be described.

Hard mask thickness Cell area Peripheral Circuit Area (A) Thickness of the first hard mask 670 670 (B) Hard mask thickness remaining after SAC etching 300 500 (C) Hard mask thickness remaining after contact opening 0 200 (D) Thickness of hard mask remaining after plug isolation 0 0

Table 1 is a graph of the graph shown in Figure 8a, and shows the change in the thickness of the hard mask in the cell and peripheral circuit area during each process for forming the LPC.

Referring to this, in the step (A), that is, the hard mask forming step, the first hard mask was formed to a thickness of 670 Å, and in step (B), that is, etching the interlayer insulating film. In the SAC etching process, 170 Å hard masks are lost in the 370 Å peripheral circuit region in the cell region, and 300 Å and 500 하드 hard masks remain in the two regions, respectively.

In the step (C), that is, the step of removing the etch stop layer, the hard mask of 300 mV is lost in the peripheral circuit area of 300 mV in the cell region, and thus, the hard masks of 0 mV and 200 mV remain in the two regions. On the other hand, it can be seen that in the step (D) after the etch back and / or CMP process for plug isolation, there is no hard mask remaining in both regions.

FIG. 8B is a TEM photograph corresponding to a cross section taken along the line X-X ′ of FIG. 6 corresponding to the cell region. Referring to FIG. 8B, the interlayer insulating layer 76 is etched, and in step (C) of removing the etch stop layer through blanket etching, all hard masks are removed from the cell region in-situ so that the interlayer insulating layer 76 is formed on the interlayer insulating layer 76. It can be seen that there is no remaining hard mask.

In this case, since the hard mask is removed in-situ when the etch stop layer is removed, the lifting phenomenon of the hard mask generated in the subsequent wet cleaning process can be prevented.

Hard mask thickness Cell area Peripheral Circuit Area (A) Thickness of the first hard mask 900 900 (B) Hard mask thickness remaining after SAC etching 500 740 (C) Hard mask thickness remaining after contact opening 140 380 (D) Thickness of hard mask remaining after plug isolation 0 0

Table 2 is a graph of the graph shown in Figure 9a, and shows the change in the thickness of the hard mask in the cell and peripheral circuit area during each process for forming the LPC.

Referring to this, in the step (A), that is, the hard mask forming step, the first hard mask was formed to a thickness of 900 Å, and in step (B), that is, etching the interlayer insulating film. In the SAC etching process, the hard mask of 160 각각 is lost in the 400 Å peripheral circuit region in the cell region, and thus, the hard masks of 500 Å and 740 잔류 remain in the two regions, respectively.

In the step (C), that is, removing the etch stop layer and opening the contact region, the hard mask of 360 에서 is lost in the peripheral circuit region of 360 에서는 in the cell region, and 140 Å and 380 하드 hard masks remain in the two regions. Able to know.

On the other hand, it can be seen that in the step (D) after the etch back and / or CMP process for plug isolation, there is no hard mask remaining in both regions.

FIG. 9B is a TEM photograph corresponding to a cross section taken along the line X-X ′ of FIG. 6 corresponding to the cell region. Referring to FIG. 9B, the interlayer insulating film 76 is etched and a hard mask 77a of 140 Å remains on the interlayer insulating film 76 in the cell region after the step (C) of removing the etch stop film through the blanket etching. It can be seen.

In this case, the lifting of the hard mask 77a in the wet cleaning process using the BOE performed after the contact opening process increases.

Therefore, as shown in the present invention, the interlayer insulating film is polished and planarized with the gate hard mask, and then a hard mask is formed thereon, thereby preventing the occurrence of lifting of the hard mask 77a by cleaning.

Hard mask thickness Cell area Peripheral Circuit Area (A) Thickness of the first hard mask 1000 1000 (B) Hard mask thickness remaining after SAC etching 600 830 (C) Hard mask thickness remaining after contact opening 250 500 (D) Thickness of hard mask remaining after plug isolation 0 100

Table 3 is a graph of the graph shown in Figure 10a, and shows the thickness change of the hard mask in the cell and the peripheral circuit area during each process for forming the LPC.

Referring to this, in the step (A), that is, the hard mask forming step, the first hard mask was formed to a thickness of 1000 Å, and in step (B), that is, etching the interlayer insulating film. In the SAC etching process, the 170kW hard mask is lost in the 400kV peripheral circuit area in the cell area, and thus, the 600kW and 830kW hard masks remain in the two areas.

In the step of (C), that is, removing the etch stop layer and opening the contact region, the hard mask of 330 Å is lost in the 350 Å peripheral circuit region in the cell region, and 250 Å and 500 하드 hard mask remain in the two regions. Able to know.

On the other hand, in the step (D) after the etch back and / or CMP process is performed for plug isolation, a hard mask of 100 Å remains in the 0 Å peripheral circuit region in the cell region.

FIG. 10B is a TEM photograph corresponding to a cross section taken along the line Y-Y 'corresponding to the cell region. Referring to FIG. 10B, as shown in FIG. 7F, the etch stop layer is removed and the contact region is opened through the contact hole 81. In this case, similarly to FIG. 9, etch stop is performed through blanket etching. After removing the film (C), the hard mask of 250 Å remains in the interlayer insulating film 76 in the cell region, so that the lifting of the hard mask may occur in the wet cleaning process using the BOE performed after the contact opening process. Increases. Therefore, as shown in the present invention, the interlayer insulating film is polished and planarized with the gate hard mask, and then a hard mask is formed thereon, thereby preventing the occurrence of lifting of the hard mask by cleaning.

Hard mask thickness Cell area Peripheral Circuit Area (A) Thickness of the first hard mask 1150 1150 (B) Hard mask thickness remaining after SAC etching 750 980 (C) Hard mask thickness remaining after contact opening 400 630 (D) Thickness of hard mask remaining after plug isolation 0-50 230

Table 4 above shows the graph of FIG. 11 as a table, and shows the change of the thickness of the hard mask in the cell and the peripheral circuit area during each process for forming the LPC.

Referring to this, in the step (A), that is, the hard mask forming step, the first hard mask was formed to a thickness of 1150 Å, and in step (B), that is, etching the interlayer insulating film. In the SAC etching process, the hard mask of 170 마 is lost in the 400 Å peripheral circuit region in the cell region, and thus, the 750 Å and 980 하드 hard masks remain in the two regions, respectively.

In the step (C), that is, removing the etch stop layer and opening the contact region, 350 하드 hard masks are lost in the 350 Å peripheral circuit region in the cell region, and 400 Å and 630 하드 hard masks remain in the two regions. Able to know.

On the other hand, in the step (D) after the etch back and / or CMP process for plug isolation, 230 Å hard mask remains in the 0 Å to 50 Å peripheral circuit region in the cell region.

In this case, similarly to FIG. 10A, after removing the etch stop layer through blanket etching (C), a hard mask of 400 잔류 remains in the interlayer insulating layer in the cell region, and accordingly, a BOE performed after the contact opening process is performed. In the wet cleaning process, the lifting of the hard mask is more likely to occur. Therefore, as shown in the present invention, the interlayer insulating film is polished and planarized with the gate hard mask, and then a hard mask is formed thereon, thereby preventing the occurrence of lifting of the hard mask by cleaning.

On the other hand, when the thickness of the hard mask is formed too thick, as shown in FIGS. 10A, 10B and 11 described above, a selectivity ratio for the photoresist may occur.

Therefore, it is desirable to appropriately adjust the thickness of the hard mask according to the design rule of the semiconductor device and the process applied.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, only the line-type SAC process is used as an example, but it is also applicable to the hole-type SAC process, and the process of opening not only between the gate electrode patterns but also between the bit lines (ie, , Storage node contact hole forming process), or via contact forming process.

The present invention as described above, while having all the advantages of using the nitride film as a hard mask, it is possible to prevent the hard mask remaining in the wet cleaning performed after the contact is opened to cause the defect of the device, The implementation of a fine pattern such as a design rule of 80nm or less has the effect of improving the yield by minimizing the occurrence of defects in manufacturing semiconductor devices.

Claims (13)

Forming a plurality of conductive patterns adjacent to each other having a first hard mask nitride film / conductive film structure on a substrate having a cell region and a peripheral circuit region; Forming an etch stop layer along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on an entire surface of the substrate on which the etch stop film is formed; Removing and planarizing the interlayer insulating layer and the etch stop layer until an upper portion of the first hard mask nitride layer is exposed; Forming a second hard mask nitride film on the exposed first hard mask nitride film and the interlayer insulating film; Forming an anti-reflection film on the second hard mask nitride film; Forming a photoresist pattern on the anti-reflection film through a photolithography process using an ArF exposure source; Selectively etching the anti-reflection film and the second hard mask nitride layer using the photoresist pattern as an etching mask to form a hard mask; Removing the photoresist pattern and the anti-reflection film; Forming a contact hole exposing the etch stop layer by etching the interlayer insulating layer between the adjacent conductive patterns using the hard mask as an etch mask; Removing the etch stop layer on the bottom of the contact hole to expose the substrate; And Cleaning the inside of the contact hole A semiconductor device manufacturing method comprising a. The method of claim 1, Removing the interlayer insulating layer and the etch stop layer to planarize And applying a chemical mechanical polishing process so that the upper part of the conductive pattern is lost within 100 mW. The method of claim 1, The interlayer insulating film is an oxide film-based material film, And forming a contact hole using a self-aligned contact etching process. The method of claim 3, wherein The conductive pattern is a semiconductor device manufacturing method, characterized in that to form a nitride film for the first hard mask having a thickness larger than the sum of the amount lost during the etching of the self-aligned contact and the amount removed in the step of removing the etch stop layer. . The method of claim 3, wherein And C ₄ F ₆ or C ₅ F ₈ gas for etching the self-aligned contact. The method of claim 1, And removing the etch stop layer, using a blanket etch. The method of claim 6, And forming the nitride film for the second hard mask to have a thickness equal to or greater than the sum of the amount lost in the forming of the contact hole and the amount lost in the removing of the etch stop layer. The method of claim 1, And removing the etch stop layer in the cell region using a cell open mask. The method of claim 1, After the cleaning step, Forming an electrically conductive plug in the exposed substrate, Forming the plug, Forming a plug forming material to be conductive with the exposed substrate; Etching back and removing a portion of the plug forming material deposited to reduce the step difference between the cell region and the peripheral circuit region; And Polishing the plug forming material with a target to which the conductive pattern is exposed to form an isolated plug A semiconductor device manufacturing method comprising a. The method of claim 9, Forming the plug forming material, And depositing the plug-forming material on the entire surface of the substrate or growing from the exposed substrate through selective epitaxial growth. The method of claim 1, The photoresist pattern includes a line type or a hole type. The method of claim 1, The conductive pattern includes any one of a gate electrode pattern, a bit line or a metal wiring. The method of claim 1, After forming the photoresist pattern, Charging the substrate on which the photoresist pattern is formed in an etching apparatus including first and second chambers, Forming the hard mask and removing the photoresist pattern and the anti-reflection film in a first chamber, Forming the contact hole and removing the etch stop layer in a second chamber.

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