KR101073130B1 - Method for forming self align contact of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a SAC of a semiconductor device that can prevent the SAC fail, for this purpose, the present invention, a plurality of conductive patterns having a laminated structure of a conductive sacrificial hard mask / insulating hard mask / conductive film on a substrate Forming a; Forming an interlayer insulating film on an entire surface of the substrate including the plurality of conductive patterns; Performing a chemical mechanical polishing process on the polishing target to which the insulating hard mask is exposed to remove the interlayer dielectric layer and the sacrificial hard mask; Forming a photoresist pattern on the insulating hard mask and the interlayer insulating film; And forming a contact hole exposing the substrate between the conductive patterns by etching the interlayer insulating layer using the photoresist pattern as an etch mask.

Contact Pads, Self Align Contact (SAC), Sacrificial Hardmask, SAC Fail, Gate Hardmask, Chemical Mechanical Polishing (CMP).

Description

Method for forming self-aligned contact of semiconductor device {METHOD FOR FORMING SELF ALIGN CONTACT OF SEMICONDUCTOR DEVICE}             

1 is a plan view showing a map of a wafer analyzed for defects after contact pad formation;

Figure 2a is a cross-sectional SEM photograph showing a portion where the SAC fail of Figure 1 occurred.

FIG. 2B is a cross-sectional SEM photograph showing a portion where the SAC fail of FIG. 1 does not occur.

3 is a view showing the polishing rate according to each part of the wafer in the chemical mechanical polishing process.

4A through 4C are cross-sectional views illustrating a SAC forming process of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

400: substrate 401: field oxide film

402 active region 403 gate insulating film

404: gate conductive film 405: gate hard mask

406: sacrificial hard mask 407: etch stop

408: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device, and more particularly, to forming a contact hole in a semiconductor device by a self alignment contact (hereinafter referred to as SAC) etching process. It is about a method.

As the degree of integration of semiconductor devices increases, a vertical arrangement of unit devices is used, and a pad (or plug) forming technology is employed for electrical connection between these unit devices. Currently, such a contact pad forming technology is a semiconductor device process technology. Generalized.

In addition, as the pitch decreases and the vertical thickness thereof increases, the etching margin is insufficient in an etching process, for example, an etching process for forming contact holes between gate electrode patterns, thereby improving an etching selectivity and obtaining an etching profile. The SAC etching process has been introduced, and is currently used as a conventional semiconductor device process.

In the case of SAC etching, when the etched layer mainly etches the interlayer insulating layer, an insulating hard mask based on a nitride layer is mainly used on the upper portion of the conductive pattern to prevent attack of the conductive pattern such as the gate electrode pattern or the bit line.

As the thickness of the hard mask is increased, the conductive pattern is effective in preventing attack, but the vertical thickness of the conductive pattern is increased to cause a gap-fill defect during deposition of the interlayer insulating film, so that the thickness is formed to an appropriate thickness.

1 is a plan view illustrating a map of a wafer in which defects are analyzed after contact pad formation.

Referring to FIG. 1, it can be seen that a plurality of net dies are partitioned on the wafer, and black dots indicate bits in which a failure occurs.

Here, reference numeral 'A' denotes a portion in which a SAC fail is generated, and reference numeral 'B' denotes a portion in which a normal SAC process is performed without generating a SAC fail.

FIG. 2A is a cross-sectional SEM photograph showing a portion where the SAC fail of FIG. 1 occurs.

Referring to FIG. 2A, it can be seen that a SAC fail occurred as indicated by the 'X' due to a lack of a hard mask margin during the SAC process.

On the other hand, Figure 2b is a cross-sectional SEM picture showing a portion of the SAC fail does not occur in Figure 1, it can be seen that the attack of the hard mask does not occur, such as 'Y' that a good SAC process was achieved.

As can be seen from the above-described Figures 2a and 2b, in the SAC etching process, the defect occurrence site occurs in the die located at the edge of the wafer rather than the middle of the wafer.

3 is a view showing the polishing rate according to each part of the wafer during the chemical mechanical polishing (CMP) process.

Referring to FIG. 3, it can be seen that the polishing rate at the center 30 of the wafer is significantly lower than the polishing rate at the edge 31 of the wafer, resulting in excessive polishing at the edge of the wafer during the CMP process.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for forming an SAC of a semiconductor device capable of preventing SAC failing.

In order to achieve the above object, the present invention comprises the steps of forming a plurality of conductive patterns having a laminated structure of a conductive sacrificial hard mask / insulating hard mask / conductive film on the substrate; Forming an interlayer insulating film on an entire surface of the substrate including the plurality of conductive patterns; Performing a chemical mechanical polishing process on the polishing target to which the insulating hard mask is exposed to remove the interlayer dielectric layer and the sacrificial hard mask; Forming a photoresist pattern on the insulating hard mask and the interlayer insulating film; And forming a contact hole exposing the substrate between the conductive patterns by etching the interlayer insulating layer using the photoresist pattern as an etch mask.

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It is very important to secure the bottom area of the contact opening because the bottom area of the contact opening affects the cell contact resistance as the degree of integration of the semiconductor device increases. Therefore, when the SAC etching process is performed while the interlayer insulating layer is thickly deposited on the gate electrode pattern when forming the cell contact, the slope of the side of the etched contact hole is 85 ° or less, so the bottom of the contact hole after the SAC etching process is formed. It is difficult to secure a bottom. In addition, over-etching must be performed, which may cause a gate hard mask to be damaged.

Accordingly, in the present invention, by removing the interlayer insulating layer on the conductive pattern such as the gate electrode pattern and placing the hard mask or photoresist pattern, which is the SAC etching mask, on the gate electrode pattern, the etching target is reduced, thereby reducing the gate hardness of the gate electrode pattern. Prevents attack of the mask and ensures sufficient contact area.

For this purpose, CMP process should be performed until the upper part of the gate electrode pattern is exposed after the deposition of the interlayer insulating film.In this case, in order to prevent attack of the gate hard mask, hard water such as metal on the existing hard mask is formed in advance. The gate electrode pattern is formed by stacking hard masks having sexual characteristics. Ensure that all conductive hardmasks are removed during the CMP process. Therefore, during the SAC etching process, the etching target may be reduced to prevent attack of the gate hard mask and sufficient contact openings may be secured.

Hereinafter, with reference to FIGS. 3A to 3D, which are attached to the most preferred embodiments of the present invention, in order to explain in detail enough to enable those skilled in the art to easily implement the technical idea of the present invention. It demonstrates in detail.

4A to 4C are cross-sectional views illustrating a SAC forming process of a semiconductor device according to an embodiment of the present invention.

In the embodiment of the present invention described below, the process of forming the contact hole pattern and the plug of the semiconductor device will be described as an example, and the contact hole pattern to which the present invention is applied is a metal node and a storage node of a bit line or a capacitor. The present invention can be applied to a process for forming a contact pad and contact with an impurity bonding layer in a substrate such as a source / drain junction for contact.

First, as shown in FIG. 4A, a field oxide film 401 is formed on a substrate 400 on which various elements for forming a semiconductor device are formed to define an active region 402. The field oxide layer 401 may use a LOCOS (LOCal Oxidation Of Silicon) or STI (Shallow Trench Isolation) scheme.

Subsequently, gate electrode patterns G1 to G4 having a structure in which a conductive sacrificial hard mask 406, an insulating gate hard mask 405, a gate conductive film 404, and a gate insulating film 403 are stacked on the substrate 400. ).                     

The gate insulating film 403 uses a conventional oxide film material film such as a silicon oxide film, and the gate conductive film 404 is made of polysilicon, tungsten (W), tungsten nitride film (WN _x ), tungsten silicide (WSi _x ), or the like. Use alone or in combination thereof.

The gate hard mask 405 is to prevent the gate conductive layer 404 from being attacked in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation, and the interlayer insulating layer and the etching speed are remarkably increased. Different materials are used. For example, when an oxide-based layer is used as an interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and an oxide-based material is used when a polymer-based low dielectric film is used as the interlayer insulating film. do.

The gate hard mask 405 is preferably formed to a thickness of 1000 kPa to 5000 kPa.

The sacrificial hard mask 406 is made of polysilicon film, Al film, W film, WSix (x is 1-2) film, WN film, Ti film, TiN film, TiSix (x is 1-2) film, TiAlN film, TiSiN Film, Pt film, Ir film, IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x is 1 to 2) ), An Al ₂ O ₃ film, an AlN film, a PtSix (x is 1 to 2) film, and at least one thin film selected from the group consisting of CrSix (x is 1 to 2) film.

The sacrificial hard mask 406 is preferably formed to a thickness of 300 kPa to 3000 kPa.                     

An impurity diffusion region (not shown) such as a source / drain junction is formed in the substrate 400 between the gate electrode patterns G1 to G4.

When source / drain junction regions are formed between the gate electrode patterns G1 to G4 through ion implantation, impurities are implanted into the substrate 400 through ion implantation so as to be aligned with the gate electrode patterns G1 to G4. Next, spacers are formed on the sidewalls of the gate electrode patterns G1 to G4 and ion implantation is performed again to form an LDD structure. Here, the LDD structure, the impurity diffusion region, and the spacer forming process are omitted.

An etch stop layer 407 is formed on the entire surface where the gate electrode patterns G1 to G4 are formed in order to prevent attack of the substrate 400 in the SAC etching process. In this case, the etch stop film 407 may be formed along the profile of the gate electrode patterns G1 to G4. The etch stop film 407 may be formed of a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film. I use it.

Nitride-based materials are mainly used as the etch stop layer 407. The reason for this is that the etching selectivity with the oxide layer used as the interlayer insulating layer in the SAC etching process for the subsequent plug formation can be obtained, and the gate electrode pattern It is to prevent the loss of etching.

On the other hand, the etch stop film 407 may be used as a single layer or may be used as a plurality of layers. In addition, since the nitride film series causes stress upon contact with the substrate 400, a structure in which a buffer oxide film is formed in a portion in contact with the substrate may be used.

Subsequently, an interlayer insulating film 408 is formed to sufficiently cover the gate electrode patterns G1 to G4 and the substrate. As the interlayer insulating film 408, a BOSG (Boro Phospho Silicate Glass) film, BSG (Boro Silicate Glass) film, PSG (Phospho Silicate Glass) film, TEOS (Tetra Ethyl Ortho Silicate) film, HDP (High Density Plasma) oxide film, low A dielectric constant film, a spin on glass (SOG) film, an advanced planarization layer (APL) film, or the like may be used alone or in combination.

Subsequently, the sacrificial hard mask 406, the interlayer cutting film 408, and the etch stop film 407 are polished and removed by performing a CMP process on the polishing target to which the gate hard mask 405 is exposed. At this time, the CMP process is performed so that the polishing rate of the oxide film series and the nitride film series is almost the same, that is, the polishing ratio of the oxide film series and the nitride film series is about 0.8: 1 to 1.2: 1.

Therefore, the attack of the gate hard mask 405 is prevented by the sacrificial hard mask 406 during the CMP process.

Meanwhile, some of the sacrificial hard mask 406 may be left, so that the sacrificial hard mask 406 may be thin enough to be removed in a subsequent SAC process, thereby obtaining a higher etching selectivity in the SAC process.

In FIG. 4B, the sacrificial hardmask 406 is removed to show a planarized process cross section.

Subsequently, the photoresist is applied to an appropriate thickness on the flattened front surface by spin coating or the like, and then a predetermined reticle (not shown) for defining an exposure source such as KrF, ArF or F ₂ and the width of the contact hole is used. SAC formation by selectively exposing a predetermined portion of the photoresist, and remaining or unexposed portions of the photoresist through a developing process, and then removing etch residues through a post-cleaning process, etc. A photoresist pattern 409, which is a cell contact open mask for forming, is formed.

Here, the cell contact open mask may use various types such as hole type, bar type, or tee type.

When the exposure to form a pattern, that is, the lower reflectance of the interlayer insulating film 408 and the gate hard mask 405 is increased to prevent diffuse reflection to form unwanted patterns, and improve the adhesion between the underlying structure and the photoresist. An antireflection film (not shown) is formed between the photoresist pattern 409 and the underlying structure for the purpose. The anti-reflection film mainly uses an organic-based material having similar etching characteristics to that of the photoresist, and may be omitted depending on the process.

In addition, a hard mask may be formed between the lower structure and the photoresist or between the lower structure and the anti-reflection film. In this case, as the hard mask material, a nitride-based insulating material or a conductive material such as tungsten or polysilicon may be used.

Subsequently, as shown in FIG. 4C, the etch stop layer 407 between the adjacent gate electrode patterns G1 to G4 is etched by etching the interlayer insulating film 408 as an etched layer using the photoresist pattern 409 as an etch mask. The contact hole 410 is formed by performing a SAC etching process that exposes the exposed portions.

Meanwhile, as described above, when the hard mask material film is formed before the photoresist pattern is formed, the hard mask material film is etched using the photoresist pattern 409 as a mask to transfer the pattern, and then the patterned hard mask material film is used. The interlayer insulating film 408 is etched.

At this time, the etching of the interlayer insulating film 408 is applied to the recipe of the conventional SAC etching process, fluorine-based plasma, for example, C ₃ F ₃ , C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F CxFy (x, y is 1 to 10) such as ₆ , C ₅ F _8, or C ₅ F _{10 is used} as a stock angle gas, and is a gas for generating a polymer in the SAC process, that is, CH ₂ F ₂ , C ₃ A gas such as HF ₅ or CHF ₃ and O ₂ are added, and an inert gas such as He, Ne, Ar, or Xe is used as a carrier gas.

Subsequently, the etch stop layer 407 is removed to expose the substrate 400 (specifically, an impurity diffusion region). The etching of the etch stop layer 407 mainly uses blanket etching. At this time, the etch stop layer 407 is removed on the side of the gate electrode patterns G1 to G4 where the contact holes 410 are formed to remain in the shape of the spacer 407a.

Subsequently, in order to remove the photoresist pattern 409 by applying a conventional photoresist strip process, to secure the CD of the bottom of the contact hole 410, and to remove the etching by-products remaining after the process such as SAC and blanket etching. Wet cleaning is performed using cleaning liquids, such as BOE. When washing, BOE or hydrofluoric acid is used. In the case of hydrofluoric acid, it is preferable to use dilute hydrochloric acid having a ratio of 50: 1 to 500: 1.

In addition, after the plug forming conductive film is deposited on the entire surface of the substrate 400 on which the contact hole 410 is formed, the contact hole 410 is sufficiently filled, and then an isolation process is performed to form a contact pad.                     

According to the present invention made as described above, in order to prevent the attack of the gate hard mask, the gate electrode pattern is formed in a structure in which a sacrificial hard mask of conductive material such as metal is stacked on the existing hard mask in advance when the gate electrode pattern is formed, After the deposition of the interlayer dielectric layer, the CMP process is performed until the upper portion of the gate electrode pattern is exposed or a portion of the sacrificial hard mask remains, thereby reducing the etching target by placing a hard mask or photoresist pattern, which is a SAC etching mask, on the gate electrode pattern. The embodiment has been found to prevent the attack of the gate hard mask of the gate electrode pattern and to sufficiently secure the contact area.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, only the T type SAC process is used as an example. In addition, the SAC process may be applied to a line type or hole type SAC process, and not only between the gate electrode patterns but also the bit line. The semiconductor device may be applied to various semiconductor manufacturing processes such as opening a gap (ie, a storage node contact hole forming step) or a via contact forming step.

 As described above, the present invention can avoid SAC fail by overcoming the limitation of the etching selectivity when forming the contact plug, thereby improving the process margin and yield of the semiconductor device.

Claims (12)

Forming a plurality of conductive patterns having a stacked structure of a conductive sacrificial hard mask / insulating hard mask / conductive film on the substrate; Forming an etch stop layer along a surface of the structure including the conductive pattern; Forming an interlayer insulating film on an entire surface of the substrate including the plurality of conductive patterns; Performing a chemical mechanical polishing process on the polishing target to which the insulating hard mask is exposed; Forming a photoresist pattern on the insulating hard mask and the interlayer insulating film; Etching the interlayer insulating layer using the photoresist pattern as an etch mask to form a contact hole exposing the etch stop layer between the conductive patterns; And Selectively etching the etch stop layer to expose a substrate under the contact hole and simultaneously forming spacers on sidewalls of the conductive pattern Self-aligning contact forming method of a semiconductor device comprising a. delete Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, A method of forming a self-aligned contact in a semiconductor device, characterized in that during the chemical mechanical polishing process, polishing conditions using an oxide selectivity and a nitride selectivity are 0.8: 1 to 1.2: 1. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The sacrificial hard mask, Polysilicon film, Al film, W film, WSix (x is 1-2) film, WN film, Ti film, TiN film, TiSix (x is 1-2) film, TiAlN film, TiSiN film, Pt film, Ir film , IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x is 1 to 2) film, Al ₂ O ₃ And at least one thin film selected from the group consisting of a film, an AlN film, a PtSix (x is 1 to 2) film, and a CrSix (x is 1 to 2) film. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein And forming the sacrificial hard mask in a thickness of 300 mW to 3000 mW. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The insulating hard mask is a nitride film-based method for forming a self-aligned contact of the semiconductor device. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, Forming an insulating hard mask having a thickness of 1000 mW to 5000 mW. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, In the etching of the interlayer insulating film, CxFy (x, y is 1 to 10) as a stock angle gas, and any one of CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ and O ₂ are added thereto, and as a carrier gas, He, Ne, Method for forming a self-aligned contact of a semiconductor device, characterized in that using any one of Ar or Xe gas. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, After the chemical mechanical polishing process, And forming an anti-reflection film between the insulating hard mask and the interlayer insulating film and the photoresist pattern. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, After forming the anti-reflection film, further comprising the step of forming a material layer for the hard mask on the anti-reflection film, After forming the photoresist pattern, etching the hardmask material layer using the photoresist pattern as an etching mask. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, The conductive pattern may include a gate electrode or a bit line. Claim 12 was abandoned upon payment of a registration fee. The method of claim 1, The contact hole is a self-aligned contact forming method of the semiconductor device, characterized in that the pattern of any one of the bar type, T type or hole type.

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