KR101046717B1 - Method for forming self-aligned contact of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a SAC of a semiconductor device that can suppress the occurrence of defects due to the difference in deposition rate, polishing rate and etching rate according to the portion of the wafer during the contact forming process to which the SAC etching process is applied. The present invention includes forming a plurality of conductive patterns having a structure in which a hard mask is stacked on a conductive film on a substrate; Depositing an interlayer insulating film on an entire surface of the substrate including the plurality of conductive patterns; Partially planarizing the interlayer insulating film by performing a polishing process on a target to which the hard mask is exposed at an edge of a wafer; Forming a flowable insulating film on the interlayer insulating film to alleviate the step difference between the wafer edge and the center portion of the wafer generated during the deposition and polishing of the interlayer insulating film; Forming a photoresist pattern on the flowable insulating film; And forming a contact hole exposing the substrate between the conductive patterns by etching the flowable insulating layer and the interlayer insulating layer using the photoresist pattern as an etch mask.

Contact Pads, Self Align Contact (SAC), Fluid Insulation, Hard Mask, SAC Fail, Gate Hard Mask, Chemical Mechanical Polishing (CMP).

Description

Method for forming self-aligned contact of semiconductor device {METHOD FOR FORMING SELF ALIGN CONTACT OF SEMICONDUCTOR DEVICE}             

1 is a schematic diagram showing the deposition rate according to each part of the wafer during the deposition of the interlayer dielectric film.

2 is a view showing the polishing rate according to each part of the wafer during the CMP process.

3 is a view illustrating an etching rate according to each part of a wafer in the SAC etching process.

4a and 4b are SEM images showing the loss amount of the gate hard mask according to the portion of the wafer after the SAC etching process.

5 is a photograph showing a comparison of the amount of loss of the substrate according to the portion of the wafer during SAC etching.

6A through 6C are cross-sectional views illustrating a SAC forming process of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

600: substrate 601: field oxide film

602 active region 603 gate insulating film                 

604: gate conductive film 605: gate hard mask

606: etching stop film 607: interlayer insulating film

608 fluid insulating film 610 contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of suppressing generation of steps according to a position of a wafer during a cell contact forming process of a semiconductor device.

As the degree of integration of semiconductor devices increases, a vertical arrangement of unit devices is used, and a pad (or plug) forming technology is employed for electrical connection between these unit devices. Currently, such a contact pad forming technology is a semiconductor device process technology. Generalized.

In addition, as the pitch decreases and the vertical thickness thereof increases, the etching margin is insufficient in an etching process, for example, an etching process for forming contact holes between gate electrode patterns, thereby improving an etching selectivity and obtaining an etching profile. For this purpose, an Self Align Contact (hereinafter referred to as SAC) etching process has been introduced and is currently used as a conventional semiconductor device process.

On the other hand, the process of forming a contact pad by applying the SAC etching process, forming a conductive pattern such as a gate electrode, depositing an interlayer insulating film, and then planarizing the interlayer insulating film, performing a SAC etching process, and then plug It consists of a structure which deposits a conductive film and performs isolation.

On the other hand, the deposition rate of the interlayer dielectric film and the polishing rate of chemical mechanical polishing (hereinafter referred to as CMP), the etching rate at the time of SAC etching is different in the die depending on the position of the wafer.

1 is a schematic diagram showing the deposition rate according to each portion of the wafer during the deposition of the interlayer dielectric film.

Referring to FIG. 1, the deposition rate of the interlayer dielectric layer at the center 10 of the wafer is significantly higher than the deposition rate at the edge 11 of the wafer, and the thickness of the interlayer dielectric layer deposited at the center of the wafer 10 after the interlayer dielectric layer is deposited. It can be seen that is significantly higher than the thickness of the interlayer insulating film deposited on the wafer edge (11).

2 is a view showing a polishing rate according to each part of the wafer during the CMP process.

Referring to FIG. 2, it can be seen that the polishing rate at the center 20 of the wafer is significantly lower than the polishing rate at the edge 11 of the wafer, resulting in excessive polishing at the edge 21 of the wafer during the CMP process.

FIG. 3 is a diagram illustrating etching rates of respective portions of a wafer in the SAC etching process.

Referring to FIG. 3, it can be seen that the etching rate at the center 30 of the wafer is significantly lower than the etching rate at the edge 31 of the wafer, resulting in excessive etching at the edge 31 of the wafer during the etching process.

Therefore, when the process for forming the cell contact is performed, the thickness of the interlayer insulating film deposited at the wafer edge is thin and the polishing rate and the etching rate are high. Therefore, when the process is performed under the same etching conditions under the same conditions, the gate hard mask is formed at the wafer edge. The loss of.

4A and 4B are SEM images illustrating the loss amount of the gate hard mask according to the portion of the wafer after the SAC etching process.

4A illustrates an etching profile in the cell region located at the edge of the wafer edge, and it can be seen that the gate hard mask is excessively lost as indicated by reference numeral 40.

4B illustrates an etching profile in the cell region located in the center of the wafer, and it can be seen that as shown by reference numeral '41', almost no loss of the gate hard mask occurs.

5 is a photograph showing a comparison of the loss of the substrate according to the portion of the wafer during SAC etching.

Referring to FIG. 5, the loss of the substrate was hardly noticeable at 'A' and 'B' located at the center of the wafer, but the loss of the substrate was hardly detected even at edges 'D' and 'E'. It can be seen that the attack of the substrate occurred excessively at the 'C' and 'F' located at the edges.

This may cause an increase in leakage current and an increase in contact resistance, and may cause an electrical short of a conductive pattern such as a gate electrode and a contact pad.

In order to improve this, the deposition may be performed through several steps in the deposition of the interlayer insulating film. However, in this case, the application of the aspect is difficult because productivity is reduced.

The present invention has been proposed to solve the above problems of the prior art, it is possible to suppress the occurrence of defects due to the difference in the deposition rate and the polishing rate and the etching rate according to the portion of the wafer during the contact forming process applying the SAC etching process It is an object of the present invention to provide a method for forming a SAC of a semiconductor device.

In order to achieve the above object, the present invention comprises the steps of forming a plurality of conductive patterns having a structure in which a hard mask is laminated on a conductive film on a substrate; Depositing an interlayer insulating film on an entire surface of the substrate including the plurality of conductive patterns; Partially planarizing the interlayer insulating film by performing a polishing process on a target to which the hard mask is exposed at an edge of a wafer; Forming a flowable insulating film on the interlayer insulating film to alleviate the step difference between the wafer edge and the center portion of the wafer generated during the deposition and polishing of the interlayer insulating film; Forming a photoresist pattern on the flowable insulating film; And forming a contact hole exposing the substrate between the conductive patterns by etching the flowable insulating layer and the interlayer insulating layer using the photoresist pattern as an etch mask.

The present invention is carried out by depositing an interlayer insulating film and then performing a planarization process up to the top of the hard mask of the lower conductive pattern (so that the hard mask is not lost at the edge of the wafer where the deposition thickness of the interlayer insulating film is relatively low). The etch target during the SAC etching process is reduced, and then a flowable insulating film is deposited thereon to overcome the step caused by the difference between the deposition rate and the polishing rate at the wafer edge and the center. Therefore, since the step between the edge and the center of the wafer hardly occurs, it is possible to prevent the loss of the hard mask at the wafer edge during the subsequent SAC etching process. In addition, since the etching target is relatively reduced during the SAC process, it is possible to minimize the attack of the lower part of the wafer edge due to the difference in the etching rate according to the portion of the wafer.

Hereinafter, with reference to FIGS. 3A to 3D, which are attached to the most preferred embodiments of the present invention, in order to explain in detail enough to enable those skilled in the art to easily implement the technical idea of the present invention. It demonstrates in detail.

6A through 6C are cross-sectional views illustrating a SAC forming process of a semiconductor device according to an embodiment of the present invention.

In the embodiments of the present invention described below, a process of forming a contact hole pattern for cell contact of a semiconductor device is described as an example, and the contact hole pattern to which the present invention is applied is a metal wiring contact and a storage of a bit line or a capacitor. The present invention can be applied to a process for forming a contact pad and contact with an impurity bonding layer in a substrate such as a source / drain junction for a node contact.

First, as shown in FIG. 6A, a field oxide film 601 is formed on a substrate 600 on which various elements for forming a semiconductor device are formed to define an active region 602. The field oxide layer 601 may use a LOCOS (LOCal Oxidation Of Silicon) or STI (Shallow Trench Isolation) scheme.

Subsequently, gate electrode patterns G1 to G8 having a structure in which a gate hard mask 605, a gate conductive film 604, and a gate insulating film 603 are stacked are formed on the substrate 600.

The gate insulating film 603 uses a conventional oxide film material film such as a silicon oxide film, and the gate conductive film 604 is made of polysilicon, tungsten (W), tungsten nitride film (WN _x ), tungsten silicide (WSi _x ), or the like. Use alone or in combination thereof.

The gate hard mask 605 is to prevent the gate conductive layer 604 from being attacked in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation, and the interlayer insulating layer and the etching speed are remarkably increased. Different materials are used. For example, when an oxide-based layer is used as an interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and an oxide-based material is used when a polymer-based low dielectric film is used as the interlayer insulating film. do.

The gate hard mask 605 is preferably formed to a thickness of 1000 kPa to 5000 kPa.                     

An impurity diffusion region (not shown) such as a source / drain junction is formed in the substrate 600 between the gate electrode patterns G1 to G8.

When source / drain junction regions are formed between the gate electrode patterns G1 to G8 through ion implantation, impurities are implanted into the substrate 600 through ion implantation so as to be aligned with the gate electrode patterns G1 to G8. Next, spacers are formed on the sidewalls of the gate electrode patterns G1 to G8 and ion implantation is performed again to form an LDD structure. Here, the LDD structure, the impurity diffusion region, and the spacer forming process are omitted.

On the other hand, in recent years, the spacer has a structure of a nitride film / oxide film / nitride film, specifically, a spacer nitride film / buffer oxide film / sealing nitride film.

Subsequently, an etch stop layer 606 is formed on the entire surface where the gate electrode patterns G1 to G8 are formed to serve as an etch stop to prevent attack of the substrate 600 in the SAC etching process. In this case, the etch stop film 606 may be formed along the profile of the gate electrode patterns G1 to G8. The etch stop film 606 may be formed of a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film. I use it.

Nitride-based materials are mainly used as the etch stop layer 606. The reason for this is that an etching selectivity with an oxide layer used as an interlayer insulating layer in the SAC etching process for the subsequent plug formation can be obtained, and the gate electrode pattern It is to prevent the loss of etching.

Meanwhile, the etch stop layer 606 may be used as a single layer or may be used as a plurality of layers. In addition, since the nitride film series causes stress upon contact with the substrate 600, a structure in which a buffer oxide film is formed in a portion in contact with the substrate may be used.

Next, an interlayer insulating film 607 is formed to sufficiently cover the gate electrode patterns G1 to G8 and the upper portion of the substrate 600. As the interlayer insulating film 607, a BPSG (Boro Phospho Silicate Glass) film, BSG (Boro Silicate Glass) film, PSG (Phospho Silicate Glass) film, TEOS (Tetra Ethyl Ortho Silicate) film, HDP (High Density Plasma) oxide film, low The dielectric constant film can be used alone or in combination.

On the other hand, when the interlayer insulating film 607 is deposited, a step of the interlayer insulating film 607 such as 't' occurs due to the difference in deposition rates at the wafer edge and the center of the wafer as described above.

Subsequently, as shown in FIG. 6B, a CMP process is performed to partially planarize the interlayer insulating film 607. At this time, the polishing target is preferably aligned so that the gate hard mask 605 is not lost at the edge of the wafer where the height of the interlayer insulating film 607 is relatively low.

By etching the interlayer insulating film 607 to the extent that no attack of the gate hard mask 605 occurs, the etching target may be reduced during the subsequent SAC etching process.

Subsequently, the interlayer insulating film 607 is etched to form a fluid insulating film 608 on the entire surface which is partially planarized.

The fluid insulating layer 608 is deposited to a minimum thickness to achieve planarization by overcoming the step difference between the two regions caused by the difference in the deposition rate and the polishing rate between the wafer edge and the center region of the wafer during deposition and polishing of the interlayer insulating film 607. Preferably, it is possible to deposit a thickness of 5000 GPa or more on the interlayer insulating film 607 and to planarize it by an etch back or CMP process.

The flowable insulating layer 608 includes a spin on glass (SOG) layer or an advanced planarization layer (APL) layer.

Subsequently, the photoresist is applied to the fluid insulating film 608 to a suitable thickness by a method such as spin coating, and then a predetermined reticle (not shown) for defining an exposure source such as KrF, ArF or F ₂ and the width of the contact hole is shown. SAC formation by selectively exposing a predetermined portion of the photoresist, leaving the exposed or unexposed portions through the developing process, and then removing the etching residues through a post-cleaning process, etc. A photoresist pattern 609, which is a cell contact open mask for forming a cell, is formed to define a cell contact formation region C / T.

Here, the cell contact open mask may use various types such as hole type, bar type, or tee type.

At the time of exposure for forming the pattern, that is, the light reflectance of the lower portion, that is, the fluid insulating film 608, is increased, thereby preventing unwanted reflections from being formed, and improving the adhesion between the underlying structure and the photoresist. An anti-reflection film (not shown) may be formed between the 609 and the lower structure. The anti-reflection film mainly uses an organic-based material having similar etching characteristics to that of the photoresist, and may be omitted depending on the process.                     

In addition, a hard mask may be formed between the lower structure and the photoresist or between the lower structure and the anti-reflection film. In this case, as the hard mask material, a nitride-based insulating material or a conductive material such as tungsten or polysilicon may be used.

Subsequently, as shown in FIG. 6C, the photoresist pattern 609 is etched using an etching mask to etch the fluid insulating film 608 and the interlayer insulating film 607 between the adjacent gate electrode patterns G1 to G8. The contact hole 610 is formed by performing a SAC etching process that exposes the etch stop layer 606.

Meanwhile, as described above, when the hard mask material film is formed before the photoresist pattern is formed, the hard mask material film is etched using the photoresist pattern 609 as a mask to transfer the pattern, and then the patterned hard mask material film is used. To etch the layer to be etched.

At this time, the etching of the fluid insulating film 608 and the interlayer insulating film 607 is applied to the recipe of the conventional SAC etching process, fluorine-based plasma, for example, C ₃ F ₃ , C ₂ F ₄ , C ₂ F ₆ , C ₃ CxFy (x, y is 1 to 10) such as F ₈ , C ₄ F ₆ , C ₅ F _8, or C ₅ F _{10 is used} as the stock angle gas, and the gas for generating the polymer in the SAC process, that is, CH ₂ F ₂ , C ₃ HF ₅ or a gas such as CHF ₃ and O ₂ are added, and an inert gas such as He, Ne, Ar, or Xe is used as a carrier gas.

Subsequently, the etch stop layer 606 is removed to expose the substrate 600 (specifically, an impurity diffusion region). The etching of the etch stop layer 606 mainly uses blanket etching. At this time, the etch stop layer 606 is removed from the gate electrode patterns G1 to G8 on which the contact holes 610 are formed to remain in a spacer shape.

Subsequently, a photoresist strip process is applied to remove the photoresist pattern 609, a CD of the bottom of the contact hole 610 is secured, and an etching byproduct such as BOE is removed to remove residual etching by-products such as SAC and blanket etching. Wet cleaning is performed using a cleaning liquid. When washing, BOE or hydrofluoric acid is used. In the case of hydrofluoric acid, it is preferable to use dilute hydrochloric acid having a ratio of 50: 1 to 500: 1.

In a subsequent process, a plug forming conductive film is deposited on the entire surface of the substrate 600 on which the contact holes 610 are formed to sufficiently fill the contact holes 610, and then an isolation process is performed to form contact pads.

According to the present invention as described above, the interlayer insulating film is partially planarized by the CMP process to reduce the etching target during the subsequent SAC etching process, and the step difference between the wafer edge and the center of the wafer is reduced by using a fluid insulating film such as an APL film. The process is performed to form contact holes.

Therefore, the use of the fluid insulating film reduces the step generation caused by the difference between the wafer regions during deposition and polishing of the interlayer insulating film, and reduces the SAC etching target to minimize the attack at the bottom of the SAC etching process, thereby reducing the wafer during the SAC etching process. The SAC fail and attack of the hard mask according to the portion of the to prevent the attack, it was found through the embodiment that the contact area can be sufficiently secured.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, only the T type SAC process is used as an example. In addition, the SAC process may be applied to a line type or hole type SAC process, and not only between the gate electrode patterns but also the bit line. The semiconductor device may be applied to various semiconductor manufacturing processes such as opening a gap (ie, a storage node contact hole forming step) or a via contact forming step.

As described above, the present invention can prevent the loss of the hard mask due to the difference in the process characteristics according to the portion of the wafer to prevent the SAC fail, thereby improving the process margin and yield of the semiconductor device.

Claims (8)

Forming a plurality of conductive patterns having a structure in which hard masks are stacked on a conductive film on a substrate; Depositing an interlayer insulating film on an entire surface of the substrate including the plurality of conductive patterns; Partially planarizing the interlayer insulating film by performing a polishing process on a target to which the hard mask is exposed at an edge of a wafer; Forming a flowable insulating film on the interlayer insulating film to alleviate the step difference between the wafer edge and the center portion of the wafer generated during the deposition and polishing of the interlayer insulating film; Forming a photoresist pattern on the flowable insulating film; And Forming a contact hole exposing the substrate between the conductive patterns by etching the flowable insulating layer and the interlayer insulating layer using the photoresist pattern as an etch mask. Self-aligning contact forming method of a semiconductor device comprising a. The method of claim 1, The flowable insulating film includes a SOG film or an APL film. The method of claim 1, Etching the flowable insulating film and the interlayer insulating film; CxFy (x, y is 1 to 10) is used as an etching gas, and any one of CH ₂ F ₂ , C ₃ HF ₅ or CHF ₃ and O ₂ is added as a polymer generating gas, and He, Method for forming a self-aligned contact of a semiconductor device, characterized in that using any one of Ne, Ar or Xe gas. The method of claim 1, After forming the conductive pattern, And forming an etch stop layer along the profile in which the conductive pattern is formed. The method of claim 1, After depositing the flowable insulating film, And forming an anti-reflection film between the flowable insulating film and the photoresist pattern. The method of claim 5, After forming the anti-reflection film, further comprising the step of forming a material layer for the hard mask, After forming the photoresist pattern, etching the hardmask material layer using the photoresist pattern as an etching mask. The method of claim 1, The conductive pattern may include a gate electrode or a bit line. delete

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