KR100507872B1 - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can reduce the defect of the semiconductor device due to the lifting of the pattern and contamination of the residue caused by excessive polishing at the wafer edge after the plug conductive layer deposition, the present invention is Forming a plurality of conductive layer patterns having a structure in which a sacrificial hard mask and a hard mask are stacked on the wafer; Forming a photoresist pattern masking only an edge region of the wafer; Removing the sacrificial hard mask in the center region of the wafer using the photoresist pattern as an etching mask; Removing the photoresist pattern; Depositing an insulating film over the entire structure; Selectively etching the insulating layer between the conductive layer patterns in the central region of the wafer to form a contact hole exposing the substrate; Forming a conductive plug conductive film on the entire structure of the contact hole; And a chemical mechanical polishing process of removing the contact plug conductive film, the insulating film, and the sacrificial hard mask in the wafer edge region from the wafer center region to the target where the hard mask is exposed. It provides a method for manufacturing a semiconductor device comprising the step of forming a plug.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of preventing the occurrence of residues or lifting of patterns in a wafer edge region during a chemical mechanical polishing (CMP) process. It relates to a manufacturing method.

As the degree of integration of semiconductor devices increases, a vertical arrangement of unit devices is used, and a plug forming technology has been adopted for electrical connection between these unit devices. At present, such a contact plug forming technology has become common in semiconductor device processing technology. .

When forming such a contact plug, a planarization process such as CMP for isolation between plugs is also required.

In addition, since the damascene process is applied due to an increase in etching difficulty of precious metals such as Pt used in forming conductive patterns such as metal wirings or bit lines, the above-described CMP process is used.

On the other hand, the wafer center portion and the edge region have a significant difference in polishing rate in the above-described CMP process.

1 is a graph showing the change of the polishing rate (mm / min) according to the distance (mm) from the wafer edge.

Referring to FIG. 1, the polishing rate is highest up to a distance of about 1 mm to 2 mm from the wafer and gradually decreases to about 3 mm, and a constant (low) polishing rate is obtained from an area beyond 3 mm from the wafer edge. It can be seen that this is due to the characteristics of the CMP process.

Hereinafter, the problems of the prior art will be described with reference to Japanese Laid-Open Patent Publication No. 14-025194.

2A to 2D are cross-sectional views illustrating a semiconductor device manufacturing process according to the prior art.

First, as illustrated in FIG. 2A, a BPSG (Boro Phospho Silicate Glass) film is formed on the semiconductor wafer 20 on which a predetermined process for forming a semiconductor device is completed as a first insulating film 21. And a planarization process, and then a lower layer wiring 22 is formed on the first insulating layer 21.

Next, a TEOS (TetraEthyl Ortho Silicate) film is deposited as the second insulating film 23 by a CVD method.

Here, in the case of the first insulating film 21, the tendency to be deposited at the wafer edge 24 or the center is almost no difference, so that the flatness is almost maintained in the subsequent CMP process.

However, in the case of the second insulating film 23, the deposited thickness becomes thinner toward the edge of the wafer due to the difference in the pattern density by the lower layer wiring 22.

Subsequently, as illustrated in FIG. 2B, the second insulating layer 23 is planarized through a CMP process.

Subsequently, as shown in FIG. 2C, the second insulating layer 23 is selectively etched through a photo lithography process and a dry etching process to form a contact hole 25 exposing the lower layer wiring 22. Next, a conductive film 26 such as a tungsten (W) film is deposited on the entire surface of the wafer 20 by CVD.

At this time, in order to improve the adhesion property and the diffusion preventing property of the conductive film 26, the laminated film of the Ti film / TiN film may be deposited before the conductive film 26 is deposited.

Subsequently, as illustrated in FIG. 2D, the conductive layer 26 on the second insulating layer 23 is removed through the CMP process to form a plug in which the conductive layer 26 exists only in the contact 25.

On the other hand, when the plug is formed through the above-described process, after the CMP process of the second insulating layer 23, the polishing rate is increased in the edge region of the wafer 20, and as shown in FIG. 2C, the wafer edge region ( The second insulating film 23 at 27 is almost lost, which has a constant slope from the edge 24 to the predetermined region 28.

Accordingly, the lower pattern may be lifted due to the loss of the second insulating layer 23, and the residue 30 of the conductive layer 25 may remain in the edge region 27 after the CMP process for forming the plug. It causes metal contamination.

On the other hand, in order to suppress the floating of the pattern caused by over-polishing in the wafer edge region, a method for reducing the step between the edge region and the center of the wafer is formed by forming a dummy pattern in the wafer edge region.

3 is a cross-sectional view of a semiconductor device according to the related art, which illustrates a state in which a dummy pattern is formed in a wafer edge region.

Referring to FIG. 3, a plurality of conductive patterns G on which a conductive film 32 and a hard mask 33 are stacked are formed on a wafer 31, and a plug 36 is formed between the conductive patterns G. In contact with the wafer 31, a dummy pattern 37 is formed in the edge region of the wafer 31.

Spacers 34 are formed on the sidewalls of the conductive pattern G. In the edge region of the wafer 31, the insulating film 35 is excessively polished when the plug 36 is formed, and a part of the dummy pattern 37 is denoted by reference numeral '38. 'Is exposed.

As described above, the dummy pattern is formed in the wafer edge area to solve the problem caused by overpolishing at the wafer edge. However, in this case, an additional problem occurs due to the exposure of the dummy pattern.

In addition, in order to solve the above-mentioned problem, US Patent Application No. US 09/062543 forms a dummy pattern of a nitride film only in the wafer edge region (approximately about 10 mm), thereby preventing contamination and lifting due to the CMP process on the metal. Attempt to suppress.

However, in this case, a separate nitride film deposition process for forming a dummy pattern and a photolithography process for pattern formation should be added, and in addition, ArF required as the semiconductor manufacturing process technology has a design rule of 0.1 μm or less. The problem also arises in application to a photolithography process using an exposure source such as (argon fluoride).

The present invention has been proposed to solve the above problems of the prior art, a semiconductor device that can reduce the defect of the semiconductor device due to the lifting of the pattern and contamination of the residue due to excessive polishing at the wafer edge after the plug conductive layer deposition Its purpose is to provide a process for the preparation.

In order to achieve the above object, the present invention comprises the steps of forming a plurality of conductive layer pattern having a structure in which a sacrificial hard mask and a hard mask are stacked on the wafer; Forming a photoresist pattern masking only an edge region of the wafer; Removing the sacrificial hard mask in the center region of the wafer using the photoresist pattern as an etching mask; Removing the photoresist pattern; Depositing an insulating film over the entire structure; Selectively etching the insulating layer between the conductive layer patterns in the central region of the wafer to form a contact hole exposing the substrate; Forming a conductive plug conductive film on the entire structure of the contact hole; And a chemical mechanical polishing process of removing the contact plug conductive film, the insulating film, and the sacrificial hard mask in the wafer edge region from the wafer center region to the target where the hard mask is exposed. It provides a method for manufacturing a semiconductor device comprising the step of forming a plug.

In the present invention, when forming a conductive pattern in which a conductive layer and an insulating hard mask are stacked in the center of the wafer, a dummy pattern having the same structure as that of the conductive pattern formed in the center of the wafer is formed in the wafer edge region. A sacrificial hard mask using a thin layer of a metal-based thin film having polishing resistance, for example, is formed on the dummy pattern hard mask as a hard mask and a laminated structure. Remove

As a result, even if a global step occurs due to the pattern density between the center and the edge of the wafer during the subsequent deposition of the insulating layer, the contact etching process for forming the plug is performed, followed by the deposition of the plug material. The polishing speed is slower than the center of the wafer due to the hard mask. At this time, if the thickness of the sacrificial hard mask is adjusted to the appropriate polishing thickness at the time of CMP at the center of the wafer, problems of pattern lifting and metal contamination due to overpolishing at the edge of the wafer are caused. Can be solved.

Hereinafter, with reference to FIGS. 3a to 3c attached to the most preferred embodiments of the present invention in order to explain in detail enough that those skilled in the art can easily implement the technical idea of the present invention. It demonstrates in detail.

4A through 4E are cross-sectional views illustrating a process of forming a contact plug in a semiconductor device according to an embodiment of the present invention.

In FIG. 4A, a plurality of conductive patterns, eg, gate electrode patterns or bit line patterns, are formed in the center region a-a ′ of the wafer 40. In this case, in the edge region b-b ′ of the wafer 40, a plurality of conductive patterns are formed. A series of process cross sections for forming a dummy pattern is disclosed, and the process will be briefly described. Meanwhile, in the exemplary embodiment of the present invention, the gate electrode pattern is taken as an example. However, the gate electrode pattern may be applied to a process of forming a capacitor contact plug formed by being aligned with the bit line.

A field oxide film (not shown) is formed on a wafer 40 on which various elements for forming a semiconductor device are formed by a LOCOS (LOCal Oxidation of Silicon) or STI (Shallow Trench Isolation) process to separate active and device isolation regions. do.

A plurality of conductive patterns adjacent to the active region, that is, a gate electrode pattern, are formed to deposit a gate insulating film (not shown) of an oxide film array, a metal film such as tungsten, a metal nitride film such as tungsten nitride film, and tungsten silicide By depositing a metal silicide or polysilicon or the like alone or in combination, the conductive layer 41a is formed, and then an insulating film for a hard mask based on a nitride film is deposited.

Subsequently, a sacrificial film for hard mask is deposited to prevent excessive polishing in the wafer edge region b-b '.

Here, the sacrificial film for the hard mask may be a polysilicon film, an Al film, a W film, a WSix (x is 1 to 2) film, a WN film, a Ti film, a TiN film, a TiSix (x is 1 to 2) film, a TiAlN film, or a TiSiN film. Film, Pt film, Ir film, IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x is 1 to 2) ), At least one thin film selected from the group consisting of an Al ₂ O ₃ film, an AlN film, a PtSix (x is 1 to 2) film and a CrSix (x is 1 to 2) film.

Subsequently, the photoresist pattern 44 for forming the gate electrode pattern is formed, and then the sacrificial layer for the hard mask and the insulating layer for the hard mask are selectively etched using the photoresist pattern 44 as an etch mask to sacrificial the hard mask 42 and the sacrificial layer. By forming a structure in which the hard masks 43 are stacked, the gate electrode pattern G and the dummy pattern D forming region are defined.

The photoresist pattern 44 may be formed by coating an organic anti-reflective coating on a sacrificial film for hard mask and applying a photoresist thereon, and then applying KrF or the like. Exposure is carried out with an exposure source using an ArF or F ₂ laser having a shorter wavelength of the light source, followed by a baking step and a developing step.

Subsequently, a photoresist strip process is performed to remove the photoresist pattern 44, which is illustrated by dotted lines in FIG. 4A.

Subsequently, the conductive layer 41a is selectively etched using the sacrificial hard mask 43 and the hard mask 42 as an etch mask to sacrificial hard at the wafer center region a-a 'and the wafer edge region a-a'. A gate electrode pattern G and a dummy pattern D in which the mask 43, the hard mask 42, and the conductive layer pattern 41 are stacked are formed, respectively.

Next, the sacrificial hard on the wafer center region a-a ', that is, on the gate electrode pattern G, so that the sacrificial hard mask 43 remains only on the dummy pattern D in the wafer edge region b-b'. The mask 43 is selectively removed.

That is, as shown in FIG. 4B, after forming the photoresist pattern 44 masking only the wafer edge region b-b ', the gate electrode pattern G is formed by using the photoresist pattern 44 as an etch mask. Only the sacrificial hard mask 43 in the formed wafer center region a-a 'is selectively removed as shown by the dotted line.

On the other hand, as described above, the photoresist pattern 44 masking only the wafer edge region b-b 'on which the dummy pattern is formed has a planar shape as shown in FIG.

Referring to FIG. 5, since the photoresist pattern 44 only masks the wafer edge region b-b ', only the sacrificial hard mask 43 in the wafer center region a-a' is selectively used as an etching mask. Can be removed

The process recipe for forming and removing the above-mentioned sacrificial hard mask will be described.

When the sacrificial hard mask 43 is a thin film containing tungsten (W) such as a W film, a WSix film, or a WN film, a plasma using a mixed gas of SF ₆ / N ₂ is used, in which case SF ₆ / N ₂ It is preferable to use those whose mixing ratio is 0.10 to 0.60.

When the sacrificial hard mask is a thin film containing titanium (Ti), such as a polysilicon film or a Ti film, a TiN film, a TiSix film, a TiAlN film, or a TiSiN film, chlorine-based gas, in particular, Cl ₂ is used as the stock angle gas. At this time, oxygen (O ₂ ) or CF gas is appropriately added to control the etching profile.

When the sacrificial hard mask contains noble metals such as Pt, Ir, Ru, or oxides thereof, plasma using chlorine or fluorine-based gas is used. In this case, high ion energy is used to control the etching profile. Since it is necessary to maintain the low pressure (High pressure) and high bias power (High bias power) conditions for this purpose.

Subsequently, the photoresist pattern 44 is removed through a photoresist strip process.

Therefore, the dummy pattern D in the wafer edge region b-b 'forms a structure in which the sacrificial hard mask 43, the hard mask 42, and the conductive layer pattern 41 are stacked, and in the wafer center region, the dummy pattern D is hard. Only the mask 42 and the conductive layer pattern 41 form a stacked structure.

Subsequently, as illustrated in FIG. 4C, the nitride stop layer 45 is thinly deposited along the entire profile in which the gate electrode pattern G and the dummy pattern D are formed. Here, the reason why the nitride-based material is used as the etch stop layer 45 is to determine the etch selectivity with the oxide layer in a subsequent process for forming a plug or the like, for example, a Self Align Contact (hereinafter referred to as SAC) process. It is possible to obtain, and to prevent the etching loss of the gate electrode pattern (G).

Subsequently, an oxide insulating film 46, such as a BPSG film, is formed to sufficiently cover the gate electrode pattern G, the dummy pattern D, and the upper portion of the substrate 40, for interlayer insulation. Meanwhile, as described above, the wafer edge region b-b 'becomes the wafer center region a-a' due to the pattern density difference between the wafer edge region b-b 'and the wafer center region a-a'. In contrast, its vertical height is low, resulting in a step like 'X' shown between the two regions.

Here, the insulating film 46 may be, for example, a phospho-silicate glass (PSG) film or a boro-silicate glass (BSG) film in addition to the above-described BPSG film. Entails.

In addition, a TEOS film, a high density plasma (HDP) oxide film, an advanced planarization layer (APL) film, or the like may be used.

Next, the contact 40 is formed between the substrate 40 between the gate electrode pattern in the wafer center region a-a ', specifically, the electrical connection between the active region in the substrate 40 and the device to be formed thereon by a subsequent process. In order to form a cell contact open mask (not shown), the substrate layer between the gate electrode pattern G may be selectively etched by using the cell contact open mask as an etch mask. 40) forming a contact hole (not shown) for opening the surface, and then contacting the open and exposed surface of the substrate 40 and forming polysilicon, tungsten (W) or titanium nitride (TiN) to fill the contact hole sufficiently. The conductive material 47 is formed by depositing a conductive material, and FIG. 4D illustrates a cross section of the process in which the conductive film 47a is formed.

On the other hand, when etching the insulating film 36 described above, fluorine-based plasma used in a normal SAC process, for example, C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F ₈ or C ₅ F _10, etc., and a CxFy (x, y is 1 to 10), the respective gas stock, gas for generating a SAC process during polymer herein i.e., CH ₂ F _2, the addition of gas, such as C ₃ HF _5, or CHF ₃ In this case, an inert gas such as He, Ne, Ar, or Xe is used as a carrier gas.

Here, the cell contact open mask may use a hole type, a bar type, a tee type, or the like.

In the related art, since the planarization process was performed to form a plug by separating the conductive film 47a collectively according to the etching target of the cell region regardless of the step difference between the two regions, the dummy pattern was formed in the wafer edge region b-b '. As the attack of (D) occurred, in the present invention, the speed difference of the CMP is alleviated through the sacrificial hard mask 43 formed in the dummy pattern D of the wafer edge region b-b ', so that the wafer center region a -a ') coincided with the point at which planarization took place.

That is, as shown in FIG. 4E, the conductive film 47a and the insulating film 46 and the etching in the sacrificial hard mask 43 and the wafer center region a-a 'of the wafer edge region b-b' are etched. The CMP process is performed under such a condition that the stop film 45 can be removed at about the same time, thereby forming the plugs 47 isolated from each other in the wafer center region A-A '.

Since the etching rate of the sacrificial hard mask 43 is significantly lower than that of the conductive layer 47a and the insulating layer 46, the insulating layer 46 and the etching stop layer 45 in the wafer center region a-a ′ are 45. The loss of the dummy pattern D in the wafer edge region b-b 'hardly occurs until) is removed.

Therefore, only the process of removing the sacrificial hard mask without the process of depositing and patterning a separate film may be added to prevent the dummy pattern from attacking at the wafer edge region, and to planarize and isolate the contact plugs 47 from each other.

In addition, the weak etching resistance of the ArF photoresist to fluorine-based gas can be overcome by using a sacrificial hard mask, as is well known in the application of an ultrafine pattern forming process for forming a pattern of 0.1 μm or less such as ArF or F ₂ . .

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent the polishing residue in the wafer edge region and the dummy pattern from being exposed in the process of forming a separate contact plug, so that the process margin and yield of the semiconductor device are ultimately reduced. You can expect an excellent effect to improve the.

1 is a graph showing the change in polishing with distance from the wafer edge.

2A to 2D are cross-sectional views showing a semiconductor device manufacturing process according to the prior art.

3 is a cross-sectional view showing a semiconductor device according to the improved prior art.

4A to 4E are cross-sectional views illustrating a process of forming a contact plug in a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a plan view showing the shape of the photoresist pattern of FIG. 4B; FIG.

Explanation of symbols on main parts of drawing

40: substrate 41: conductive layer pattern

42: Hard Mask 43: Sacrifice Hard Mask

45: etching stop film 46: insulating film

47: plug

Claims (9)

Forming a plurality of conductive layer patterns having a structure in which a sacrificial hard mask and a hard mask are stacked on the wafer; Forming a photoresist pattern masking only an edge region of the wafer; Removing the sacrificial hard mask in the center region of the wafer using the photoresist pattern as an etching mask; Removing the photoresist pattern; Depositing an insulating film over the entire structure; Selectively etching the insulating layer between the conductive layer patterns in the central region of the wafer to form a contact hole exposing the substrate; Forming a conductive plug conductive film on the entire structure of the contact hole; And A plurality of plugs separated from each other by performing a chemical mechanical polishing process of removing the conductive plug conductive film, the insulating film and the sacrificial hard mask in the wafer edge region from the wafer center region to the target exposed hard mask. Forming steps A semiconductor device manufacturing method comprising a. The method of claim 1, The thickness of the sacrificial hard mask is determined such that the time during which the sacrificial hard mask is etched in the wafer edge region and the time during which the conductive film and the insulating film are etched in the wafer center region coincide with each other during the chemical mechanical polishing process. A semiconductor device manufacturing method. The method of claim 1, And wherein the conductive layer pattern in the wafer edge region is a dummy pattern. The method of claim 1, And the conductive layer pattern is a gate electrode or a bit line. The method according to claim 1 or 2, The sacrificial hard mask, Polysilicon film, Al film, W film, WSix (x is 1-2) film, WN film, Ti film, TiN film, TiSix (x is 1-2) film, TiAlN film, TiSiN film, Pt film, Ir film , IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x is 1 to 2) film, Al ₂ O ₃ And at least one thin film selected from the group consisting of a film, an AlN film, a PtSix (x is 1 to 2) film, and a CrSix (x is 1 to 2) film. The method of claim 5, In the etching of the hard mask sacrificial film, When the hard mask for the sacrificial film including a W SF, but a mixed plasma of ₆ / N _2, method of manufacturing a semiconductor device characterized by using by a SF ₆ / N ₂ at a rate of 0.10 to 0.60. The method of claim 5, In the etching of the hard mask sacrificial film, When the hard mask sacrificial film includes polysilicon or Ti, the chlorine-based gas is used as the stock angle gas, and the semiconductor device manufacturing method comprises adding oxygen or CF gas for etching profile control. The method of claim 5, In the etching of the hard mask sacrificial film, And a chlorine or fluorine-based plasma when the hard mask sacrificial film contains a noble metal or an oxide thereof containing any one of Pt, Ir or Ru. The method of claim 1, The conductive plug conductive film comprises a polysilicon, tungsten or titanium nitride film.