KR100709447B1 - A method for forming a semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a semiconductor device, comprising a conductive wiring overlapping a mask insulating film pattern on a semiconductor substrate, an insulating film spacer formed on the sidewalls of the patterns, and an interlayer insulating film formed thereon to planarize a surface thereof. A photolithography process using a contact mask is performed to form a storage electrode contact hole and a bit line contact hole which expose the semiconductor substrate by etching the interlayer insulating layer, and then depositing a contact plug conductive layer filling the contact holes, and landing plug The first CMP process is performed to form poly (LPP) and to etch the contact plug conductive layer and the interlayer insulating film to an upper predetermined thickness, using a basic slurry, and then using an acid slurry to form a contact plug conductive layer. A second CMP process of polishing the interlayer insulating film and exposing the upper portion of the mask insulating film pattern By forming the lug, it is possible to prevent dishing of the mask insulating film pattern or contact plug, thereby preventing deterioration of device characteristics and consequently high integration of semiconductor devices.

Description

A method for forming a semiconductor device

1 is a SEM photograph of the dishing occurs when forming a semiconductor device according to the prior art.

Figure 2 is a detailed picture of the portion of the fail generated when forming the bit line by dishing.

3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

8 is a SEM photograph after the formation of the contact plug of the semiconductor device formed in accordance with the present invention.

9 and 10 are graphs for explaining the effects of the present invention.

11 and 12 are plan and cross-sectional photographs of the contact plug shape designed in the step of FIG.

<Description of Symbols for Major Parts of Drawings>

11: semiconductor substrate 13: device isolation film

15 gate oxide film 17 doped polysilicon layer

19 tungsten silicide layer 21 mask insulating film

23 insulating film spacer 25 HTO layer

27: interlayer insulating film 29: contact hole

31: conductive layer for contact plug 33: contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a technique of preventing dishing of a silicon oxide film, which is a peripheral interlayer insulating film, during a CMP process of a contact plug conductive layer using a landing plug poly.

The conventional CMP process uses a basic slurry to isolate the plug, polishing the plug material, the nitride film used as the hard mask layer of the word line, and the oxide film used as the planarization and gap fill material. In the process, due to the difference in etching selectivity between the nitride film, the plug material, and the oxide film, the phenomenon of dishing of the plug material and the oxide film is caused compared to the nitride film, and thus there is a problem in the process of depositing another oxide film.

When CMP abrasive residues fall into the plug material and oxide dishing area, residues are not removed in subsequent cleaning processes, resulting in a bridge between the bitline contact plugs and the storage contact plugs, reducing device yield. There is a problem.

1 and 2 are views for explaining a problem according to a method of forming a semiconductor device according to the prior art.

FIG. 1 shows a word line having a mask insulating layer pattern formed of a nitride film on the upper side and a nitride spacer formed on a sidewall thereof, and forming an interlayer insulating layer formed of BPSG to planarize the upper portion thereof, and then storing electrode contact holes and bit line contacts. In the photolithography process using an exposure mask capable of forming holes, the interlayer insulating layer is etched self-aligned to form a storage electrode contact hole and a bit line contact hole, and then the conductive layer filling the contact holes is formed on the entire surface. The conductive layer is etched to expose the interlayer insulating film, and then CMP is formed on the surface until the mask insulating film is exposed to form a contact plug.

In this case, the CMP process is performed by using an etching selectivity difference between the nitride film as the mask insulating film, the BPSG as the silicon oxide film, and the conductive layer for contact plug, using a basic slurry.

(a) shows that the contact plug conductive layer, which is the material for the contact plug, is over-etched and dished during the CMP process.

(b) shows that the BPSG, which is an interlayer insulating film, is over-etched and dished during the CMP process.

FIG. 2 is a photograph showing a fail generated due to the dishing phenomenon of FIG. 1, and is caused by residue generated during CMP of a landing plug poly (LPP). FIG. In a subsequent process, the short state between the bit line contact plug and the storage electrode contact plug has occurred.

(c) shows the column fail and (d) shows the bit fail.

As described above, the method for forming a contact plug of a semiconductor device according to the related art includes a contact plug conductive layer and an interlayer insulating film during a CMP process using a difference in etching selectivity between a nitride film as a mask insulating film and a silicon oxide film as an interlayer insulating film and a conductive layer for a contact plug. Due to the dishing phenomenon of the phosphorus silicon oxide film, there is a problem that deterioration of characteristics of the device and a decrease in yield may occur.

The present invention is to solve the above problems of the prior art, an object of the present invention is to perform a first CMP process using a basic slurry having a faster polishing rate for the silicon layer and the oxide film than the nitride film and to reduce dishing. By performing the second CMP process using an acidic slurry which can be used to suppress the occurrence of dishing phenomenon in the CMP process for forming the contact plug, the characteristics and reliability of the semiconductor device can be improved and the yield of the semiconductor device can be improved accordingly. A method of forming a semiconductor device is provided.

In order to achieve the above object, a method of forming a semiconductor device according to the present invention,

Forming a gate insulating film on the semiconductor substrate;

Forming a conductive wiring on the gate insulating film, the conductive wiring overlapping the mask insulating film pattern formed of a nitride film;

Forming an insulating film spacer on sidewalls of the conductive wiring and the mask insulating film pattern;

Forming an interlayer insulating film made of an oxide film to planarize the entire surface of the resultant;

Forming a storage electrode and a bit line contact hole to expose the semiconductor substrate by etching the interlayer insulating layer and the oxide layer by a photolithography process using a contact mask;

Forming a contact plug made of silicon to fill the contact hole;

Performing a first CMP process of etching the contact plug and the interlayer insulating film to a predetermined thickness, using a basic slurry;

The contact plug and the interlayer insulating film may be subjected to a second CMP process using an acidic slurry to expose the mask insulating film pattern.

In the method for forming a semiconductor device according to the present invention, the basic slurry has a pH of 6 to 12, the acid slurry has a pH of 6 or less, and the polishing selectivity of the (silicon layer / oxide layer) of the acid slurry is 0.5 to 2. It features.

In addition, another feature of the method for forming a semiconductor device according to the present invention includes an anti-reflection film on the mask insulating film, a silicon oxynitride film (SiON) as the anti-reflection film, and an organic lower anti-reflection film on the conductive wiring (organic) bottom ARC) is provided.

In addition, another feature of the method for forming a semiconductor device according to the present invention is that the contact plug is formed of amorphous silicon, polysilicon or epitaxially grown silicon, and the contact plug is provided in a circular or "T" shape. It is characterized by.

In addition, the method for forming a semiconductor device according to the present invention is characterized in that the CMP process only proceeds to an acidic slurry of pH 6 or less.                     

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

First, a device isolation film 13 defining an active region is formed on the semiconductor substrate 11, and a gate oxide film 15 is formed over the entire surface.

A gate electrode conductive layer is formed on the gate oxide film 15. In this case, the gate electrode conductive layer is formed of a stacked structure of the doped polysilicon layer 17 and the tungsten silicide layer 19.

A mask insulating film 21 is formed on the conductive layer for the gate electrode. In this case, the mask insulating film 21 is formed of a nitride film.

Next, a gate electrode having a stacked structure of the mask insulating layer 21 pattern and the gate electrode conductive patterns 17 and 19 is formed by a photolithography process using a gate electrode mask.

Here, an anti-reflection film (not shown) may be formed on the mask insulating layer 21. In this case, the anti-reflection film is formed of a silicon oxynitride film (SiON). The anti-reflection film may be formed as an organic lower anti-reflection film and formed under the gate electrode. (See Figure 3)

Then, an insulating film spacer 23 is formed on the sidewalls of the gate electrode and the like, a high temperature oxide (HTO) layer 25 is formed on the entire surface, and an interlayer insulating film 27 made of an oxide film is formed to planarize the entire surface. ). (See Figure 4)                     

Next, a portion predetermined as the storage electrode and the bit line contact region is etched to form a contact hole 29 exposing the semiconductor substrate 11.

Then, the contact plug conductive layer 31 filling the contact hole 29 is formed on the entire surface of the structure, and the difference in etching selectivity between the conductive layer 31 and the interlayer insulating layer 27 is used. The contact hole 29 is filled with the conductive layer 31 for contact plug by planar etching to expose the interlayer insulating layer 27.

In this case, the contact plug conductive layer 31 may be formed of a silicon film, an amorphous silicon film, or a polysilicon film grown by an epitaxial method. (See Figure 5)

Subsequently, a first thickness of the interlayer insulating film 27 and the contact plug conductive layer 31 is set to a first CMP.

In this case, the first CMP process is carried out using a basic slurry of pH 6-12 having a higher etching rate for the silicon layer and the oxide film than the nitride film. (See Figure 6)

Thereafter, the interlayer insulating layer 27 and the contact plug conductive layer 31 are second CMP until the mask insulating layer 21 is exposed to form the contact plug 33.

At this time, the second CMP process is carried out using an acidic slurry having a polishing selectivity of (silicon layer / oxide layer) of about 0.5 to about 2. (See Figure 7)

8 illustrates an SEM image after contact plug formation of a semiconductor device formed by the CMP process.

At this time, (e) shows a state where there is almost no dishing of the contact plug 33, and (f) shows a state where there is little dishing of the interlayer insulating film 27.

9 and 10 are graphs showing improved degree of dishing and defect level through the present invention.

9 is a graph showing the degree of dishing after the CMP process of LPP using an acid slurry and a basic slurry.

When using acid slurry (-■-) and basic slurry (-◆-) in CMP process, bit line nitride film (BL NIT), bit line contact poly (BLC POLY), storage electrode contact poly (SNC POLY) The difference between dishing in the bit line contact interlayer dielectric layer (BLC BPSG) and the storage electrode contact interlayer dielectric layer (SNC BPSG) is illustrated.

FIG. 10 is a graph illustrating dishing (-●-) and pinocchio defect levels (-○-) of a BPSG insulating film according to pH of a CMP slurry, and illustrating dishing reduction and defect reduction of an interlayer insulating film according to the present invention. will be.

11 and 12 illustrate plan and cross-sectional photographs of a landing plug formed according to the present invention, in which FIG. 11 illustrates a case in which the landing plug is formed in a circular shape, and FIG. 12 illustrates a landing plug in a "T" shape. The case of forming is shown.

As described above, the method for forming a semiconductor device according to the present invention includes dishing of an interlayer insulating film and a plug by a first CMP process using a basic slurry and a second CMP process using an acidic slurry in a semiconductor device using a landing plug poly. Minimize the phenomenon to provide the effect of improving the characteristics and reliability of the semiconductor device.

Claims (10)

Forming a gate insulating film on the semiconductor substrate; Forming a conductive wiring on the gate insulating film, the conductive wiring overlapping a mask insulating film pattern formed of a nitride film; Forming an insulating film spacer on sidewalls of the conductive wiring and the mask insulating film pattern; Forming an interlayer insulating film of an oxide film material to planarize a surface on the oxide film; Forming a storage electrode and a bit line contact hole to expose the semiconductor substrate by etching the interlayer insulating layer and the oxide layer by a photolithography process using a contact mask; Forming a contact plug made of silicon to fill the contact hole; Performing a first CMP process of etching the contact plug and the interlayer insulating film to a predetermined thickness, using a first slurry having a pH of 6 to 12; The contact plug and the interlayer insulating film have a pH of 6 or less, and the polishing selectivity of the (silicon layer / oxide layer) is subjected to a second CMP process using a second slurry having a second slurry to expose the mask insulating film pattern. A method of forming a semiconductor device. delete delete The method of claim 1, A method of forming a semiconductor device, characterized in that the anti-reflection film is provided on the mask insulating film. The method of claim 4, wherein The anti-reflection film is a silicon oxynitride (SiON) forming method of a semiconductor device. The method of claim 1, And forming an organic bottom antireflection film on the conductive wiring. The method of claim 1, The contact plug is a method of forming a semiconductor device, characterized in that any one material selected from amorphous silicon, polysilicon and epi-grown silicon. The method of claim 1, The contact plug is a semiconductor device forming method characterized in that the landing (land) is provided in a circular or "T" shape. delete delete

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