KR19990070614A - Bit line planarization method of semiconductor device - Google Patents
Bit line planarization method of semiconductor device Download PDFInfo
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- KR19990070614A KR19990070614A KR1019980005565A KR19980005565A KR19990070614A KR 19990070614 A KR19990070614 A KR 19990070614A KR 1019980005565 A KR1019980005565 A KR 1019980005565A KR 19980005565 A KR19980005565 A KR 19980005565A KR 19990070614 A KR19990070614 A KR 19990070614A
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- conductive layer
- bit line
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 238000000151 deposition Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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Abstract
본 발명은 반도체장치의 평탄화 방법에 관한 것으로서, 특히 소자가 형성된 반도체 기판상에 형성된 절연층에 대한 비트라인용 콘택홀형성 작업 후 그 콘택홀 내부에 비트라인 패드를 형성한 다음 그 위 및 절연층 상부에 비트라인용 제 1 도전층을 형성하고 평탄화시킨 후 다시 그 위에 비트라인용 제 2 도전층을 형성하여 이후 층간절연층(interlayer dielectric) 평탄화공정 마진(margin)을 향상시키므로서 고집적 DRAM 소자제조에 적합하도록한 반도체장치의 비트라인 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and in particular, after forming a bit line contact hole for an insulating layer formed on a semiconductor substrate on which a device is formed, forming a bit line pad in the contact hole, and then over and the insulating layer Forming and planarizing the first conductive layer for the bit line on top, and then forming the second conductive layer for the bit line on it, thereby increasing the margin of the interlayer dielectric planarization process, thereby manufacturing a highly integrated DRAM device. The present invention relates to a bit line planarization method of a semiconductor device suitable for use.
상기 목적을 달성하기 위한 본 발명은 반도체기판상에 게이트절연막을 형성하는 단계와, 게이트절연막 위에 제 1 도전층을 형성하는 단계와, 제 1 도전층 위에 캡(capping)절연막을 형성하는 단계와, 캡절연막과 제 1 도전층 및 게이트절연막의 소정부위를 제거하여 게이트를 패터닝하는 단계와, 게이트를 마스크로 이용하여 불순물영역을 반도체기판에 형성하는 단계와, 게이트 및 잔류한 캡절연막 그리고 게이트절연막의 측면에 측벽을 형성하는 단계와, 제 1 절연층을 일부 소자가 형성된 부위를 포함하는 기판의 전면에 형성하는 단계와, 제 2 절연층의 표면을 평탄화시키는 단계와, 측벽 표면 및 불순물영역의 일부 표면을 노출시키는 콘택홀을 형성하는 단계와, 노출된 불순물영역의 표면 부위에 비트라인용 패드를 형성하는 단계와, 콘택홀을 충분히 매립하며 제 2 절연층 표면에 제 2 도전층을 형성하는 단계와, 제 2 도전층의 표면을 표면을 평탄화시키는 단계와, 제 2 도전층의 표면에 도전성 향상을 위한 제 3 도전층을 형성하는 단계와, 제 3 도전층 및 제 2 도전층의 소정부위를 제거하여 비트라인패턴을 형성하는 단계로 이루어진다.The present invention for achieving the above object comprises the steps of forming a gate insulating film on a semiconductor substrate, forming a first conductive layer on the gate insulating film, forming a cap insulating film on the first conductive layer, Patterning the gate by removing predetermined portions of the cap insulating film, the first conductive layer, and the gate insulating film; forming an impurity region on the semiconductor substrate using the gate as a mask; Forming a sidewall on the side surface, forming a first insulating layer on the front surface of the substrate including the portion where the elements are formed, planarizing the surface of the second insulating layer, and part of the sidewall surface and the impurity region Forming a contact hole exposing the surface, forming a bit line pad in a surface portion of the exposed impurity region, and sufficiently forming the contact hole. Forming a second conductive layer on the surface of the second insulating layer, planarizing the surface of the second conductive layer, and forming a third conductive layer on the surface of the second conductive layer to improve conductivity. And removing predetermined portions of the third conductive layer and the second conductive layer to form a bit line pattern.
Description
본 발명은 반도체장치의 평탄화 방법에 관한 것으로서, 특히 소자가 형성된 반도체 기판상에 형성된 절연층에 대한 비트라인용 콘택홀형성 작업 후 그 콘택홀 내부에 비트라인 패드를 형성한 다음 그 위 및 절연층 상부에 비트라인용 제 1 도전층을 형성하고 평탄화시킨 후 다시 그 위에 비트라인용 제 2 도전층을 형성하여 이후 층간절연층(interlayer dielectric) 평탄화공정 마진(margin)을 향상시키므로서 고집적 DRAM 소자제조에 적합하도록한 반도체장치의 비트라인 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and in particular, after forming a bit line contact hole for an insulating layer formed on a semiconductor substrate on which a device is formed, forming a bit line pad in the contact hole, and then over and the insulating layer Forming and planarizing the first conductive layer for the bit line on top, and then forming the second conductive layer for the bit line on it, thereby increasing the margin of the interlayer dielectric planarization process, thereby manufacturing a highly integrated DRAM device. The present invention relates to a bit line planarization method of a semiconductor device suitable for use.
종래 기술은 반도체기판 위에 형성된 각각의 소자 또는 워드라인 등의 간격을 메꾸기 위하여 절연막인 갭매립용 산화막(gap filling oxide)을 증착한 후 씨엠피 작업을 수행하게 된다.In the prior art, a gap filling oxide, which is an insulating film, is deposited to fill a gap between each device or word line formed on a semiconductor substrate, and then a CMP operation is performed.
그리고 평탄화된 절연층의 일부를 제거하여 콘택홀을 형성한 다음 여기에 비트라인을 형성하기 위해서 도전층을 증착하게 되는데 이때 콘택홀 내부에 도전층의 형성이 불량하게 되는 문제점이 있다.Then, a portion of the planarization insulating layer is removed to form a contact hole, and then a conductive layer is deposited to form a bit line therein. In this case, there is a problem in that the formation of the conductive layer is poor in the contact hole.
도 1a 내지 도 1d는 종래의 기술에 의한 반도체장치의 평탄화방법을 나타낸 것으로서 반도체장치의 수직 단면도이며, 종래의 기술에 의한 반도체소자의 COB(capacitor over bitline) 구조에서 캐패시터 제조전 비트라인을 형성하는 공정단면도이다.1A to 1D illustrate a planarization method of a semiconductor device according to a prior art, which is a vertical cross-sectional view of a semiconductor device, and forms a bit line before capacitor manufacture in a COB (capacitor over bitline) structure of a semiconductor device according to the prior art. Process cross section.
도 1a에 있어서, 반도체기판인 실리콘기판(1)상에 활성영역 격리용 필드산화막(2)을 LOCOS 공정으로 형성하여 활성영역과 필드영역을 형성한 다음 채널영역의 문턱전압을 조절하기 위한 이온주입을 실시한다. 그리고 기판(1)의 전면에 열산화공정을 실시하여 게이트산화막(3)을 형성한 다음 그(3) 위에 게이트 형성용 제 1 도전층(4)으로 도핑된 폴리실리콘 및 그(4) 위에 실리사이드 형성용 제 2 도전층(5)을 WSi를 증착하여 형성한다. 이때 제 2 도전층은 이후 형성될 게이트의 저항을 감소시키는 역할을 한다. 그다음 제 2 도전층(5) 위에 게이트 보호용 캡(capping)절연막(6)을 증착하여 형성한다.In FIG. 1A, an active region isolation field oxide film 2 is formed on a silicon substrate 1, which is a semiconductor substrate, by an LOCOS process to form an active region and a field region, and then ion implantation for adjusting the threshold voltage of the channel region. Is carried out. Then, a thermal oxidation process is performed on the entire surface of the substrate 1 to form a gate oxide film 3, and then polysilicon doped with the first conductive layer 4 for gate formation thereon and silicide on the substrate 4. The formation second conductive layer 5 is formed by depositing WSi. At this time, the second conductive layer serves to reduce the resistance of the gate to be formed later. Next, a gate protective capping insulating film 6 is deposited on the second conductive layer 5.
그리고 캡절연막(6)과 제 2 도전층(5)/제 1 도전층(4) 및 게이트산화막(3)의 소정부위를 사진식각공정을 실시하여 차례로 제거하여 게이트(5, 4)를 형성한다. 그리고 불순물영역(7)을 이온주입을 통하여 형성한다. 그 다음 형성된 소자를 포함하는 기판(1)의 전면에 절연막을 증착한 후 에치백하여 게이트(4, 5) 및 잔류한 캡절연막(6) 그리고 게이트산화막(3)의 측면에 측벽(8)을 형성한다. 그 다음, 비트라인 형성전 층간절연막(interlayer dielectric)의 평탄화를 위한 절연막(9)을 일부 소자가 형성된 부위를 포함하는 기판(1)의 전면에 증착하여 형성한다. 그 후 다시 절연막(9)의 전면에 형성된 소자의 토포그라피에 기인한 골을 매꾸기 위한 충분한 두께로 평탄화용 층간절연막(10)을 형성한 다음 층간절연막(10)의 평탄화를 확보하기 위하여 씨엠피(chemical mechanical polishing)공정이나 에치백을 실시하여 층간절연막(10)의 표면을 평탄화시킨다.Then, the predetermined portions of the cap insulating film 6, the second conductive layer 5 / first conductive layer 4, and the gate oxide film 3 are sequentially removed by a photolithography process to form the gates 5 and 4. . The impurity region 7 is formed by ion implantation. Then, an insulating film is deposited on the entire surface of the substrate 1 including the formed device, and then etched back to form sidewalls 8 on the gates 4 and 5, the remaining cap insulating film 6, and the side surfaces of the gate oxide film 3. Form. Next, an insulating film 9 for planarization of an interlayer dielectric is formed by depositing the entire surface of the substrate 1 including a portion in which some elements are formed before forming the bit line. After that, the planarization interlayer insulating film 10 is formed to a sufficient thickness to fill the valleys due to the topography of the elements formed on the front surface of the insulating film 9, and then the CMP is formed to secure the planarization of the interlayer insulating film 10. A chemical mechanical polishing process or an etch back is performed to planarize the surface of the interlayer insulating film 10.
도 1b에 있어서, 평탄화된 층간절연막(10)의 표면에 포토레지스트를 도포한 다음 사진공정을 실시하여 제 1 포토레지스트패턴(100)을 정의한다. 이때 정의된 포토레지스트패턴(100)은 비트라인과 소자의 불순물영역(7)의 연결통로를 형성하기 위하여 형성된다.In FIG. 1B, a first photoresist pattern 100 is defined by applying a photoresist to the surface of the planarized interlayer insulating film 10 and then performing a photo process. In this case, the defined photoresist pattern 100 is formed to form a connection path between the bit line and the impurity region 7 of the device.
그리고 포토레지스트패턴(100)을 마스크로 이용한 식각공정을 실시하여 마스크로 보호되지 아니하는 부위의 층간절연막(10), 절연막(9)을 제거하여 측벽(88) 표면 및 불순물영역(7)의 일부 표면을 노출시키는 콘택홀을 형성한다.Then, an etch process using the photoresist pattern 100 as a mask is performed to remove the interlayer insulating film 10 and the insulating film 9 in portions not protected by the mask, thereby removing the surface of the sidewall 88 and a part of the impurity region 7. A contact hole is formed to expose the surface.
도 1c에 있어서, 제 1 포토레지스트패턴(100)을 제거한 다음 비트라인용 제 3 도전층(110)을 도핑된 폴리실리콘으로 잔류한 층간절연층(10) 표면 및 콘택홀내부에 증착하여 한다. 그리고 형성될 비트라인의 저항을 감소시키기 위하여 제 3 도전층(110)의 표면에 제 4 도전층(120)으로 WSi를 증착하여 형성한다. 이때 콘택홀 내부에 형성된 제 3 도전층 및 제 4 도전층은 가운데 부위가 움푹 패인 단면을 갖게 되어 이후 형성될 또 다른 층간절연층 평탄화 공정에서 열악한 공정 마진을 갖게 한다.In FIG. 1C, after removing the first photoresist pattern 100, the third conductive layer 110 for the bit line is deposited on the surface of the interlayer insulating layer 10 remaining in the doped polysilicon and inside the contact hole. In order to reduce the resistance of the bit line to be formed, the fourth conductive layer 120 is formed by depositing WSi on the surface of the third conductive layer 110. In this case, the third conductive layer and the fourth conductive layer formed inside the contact hole have a recessed cross section at the center thereof, and thus have a poor process margin in another planarization of the interlayer insulating layer to be formed later.
그 다음 비트라인 패턴 형성용 마스크를 형성하기 위하여 전술한 콘택홀 상부를 포함하는 부위에 제 2 포토레지스트패턴(101)을 형성한다.Next, in order to form a mask for forming a bit line pattern, a second photoresist pattern 101 is formed at a portion including the upper portion of the contact hole.
도 1d에 있어서, 제 2 포토레지스트패턴(도시 안함)을 마스크로 이용하는 사진식각공정으로 마스크로 보호되지 아니하는 부위의 제 4 도전층(120)/제 3 도전층(110)을 제거하여 비트라인(12, 11)을 완성한다.In FIG. 1D, a bit line is removed by removing the fourth conductive layer 120 / the third conductive layer 110 in a portion not protected by the mask by a photolithography process using a second photoresist pattern (not shown) as a mask. Complete (12, 11).
상술한 바와 같이 종래 기술에 의하여 형성된 비트라인은 비트라인과 소자의 불순물영역 연결통로로 이용되는 콘택홀 부위에서 깊은 골을 형성하게 되어 비트라인 형성공정과 이후의 층간절연층 평탄화공정에서 공정마진이 작아지게 되는 문제점이 있다.As described above, the bit line formed by the prior art forms a deep valley at the contact hole portion used as the connection line between the bit line and the impurity region of the device, so that the process margin is increased in the bit line forming process and subsequent interlayer insulating layer planarization process. There is a problem of becoming small.
따라서, 본 발명의 목적은 표면이 평탄화된 비트라인용 평탄화층을 형성하므로서 비트라인 패턴형성시 공정 마진이 확대되고, 비트라인패턴 형성 후 다른 층간절연층(interlayer dielectric)의 평탄화공정에서도 공정 마진이 커지게 되는 반도체장치의 비트라인 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to form a planarization layer for a bit line having a flattened surface, thereby increasing process margins when forming a bit line pattern, and process margins even during the planarization process of another interlayer dielectric after forming the bit line pattern. The present invention provides a method for forming a bit line in a semiconductor device that becomes large.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치에 있어서 비트라인평탄화 방법은 반도체기판상에 게이트절연막을 형성하는 단계와, 게이트절연막 위에 제 1 도전층을 형성하는 단계와, 제 1 도전층 위에 캡(capping)절연막을 형성하는 단계와, 캡절연막과 제 1 도전층 및 게이트절연막의 소정부위를 제거하여 게이트를 패터닝하는 단계와, 게이트를 마스크로 이용하여 불순물영역을 반도체기판에 형성하는 단계와, 게이트 및 잔류한 캡절연막 그리고 게이트절연막의 측면에 측벽을 형성하는 단계와, 제 1 절연층을 일부 소자가 형성된 부위를 포함하는 기판의 전면에 형성하는 단계와, 제 2 절연층의 표면을 평탄화시키는 단계와, 측벽 표면 및 불순물영역의 일부 표면을 노출시키는 콘택홀을 형성하는 단계와, 노출된 불순물영역의 표면 부위에 비트라인용 패드를 형성하는 단계와, 콘택홀을 충분히 매립하며 제 2 절연층 표면에 제 2 도전층을 형성하는 단계와, 제 2 도전층의 표면을 표면을 평탄화시키는 단계와, 제 2 도전층의 표면에 도전성 향상을 위한 제 3 도전층을 형성하는 단계와, 제 3 도전층 및 제 2 도전층의 소정부위를 제거하여 비트라인패턴을 형성하는 단계로 이루어진다.In the semiconductor device according to the present invention for achieving the above object, the bit line flattening method includes forming a gate insulating film on a semiconductor substrate, forming a first conductive layer on the gate insulating film, and capping the first conductive layer. forming a insulating film, removing a predetermined portion of the cap insulating film, the first conductive layer and the gate insulating film, patterning the gate, forming an impurity region on the semiconductor substrate using the gate as a mask; Forming sidewalls of the gate, the remaining cap insulating film, and the side surfaces of the gate insulating film, forming the first insulating layer on the entire surface of the substrate including the portion where the elements are formed, and planarizing the surface of the second insulating layer. Forming a contact hole exposing the sidewall surface and a portion of the impurity region, and forming a bit at the surface portion of the exposed impurity region. Forming a pad for lines, forming a second conductive layer on the surface of the second insulating layer with sufficient contact holes, planarizing the surface of the second conductive layer, and Forming a third conductive layer on the surface to improve conductivity, and forming a bit line pattern by removing predetermined portions of the third conductive layer and the second conductive layer.
도 1a 내지 도 1d 는 종래 기술에 따른 반도체장치의 비트라인 평탄화 방법을 나타낸 단면도이다.1A to 1D are cross-sectional views illustrating a bit line planarization method of a semiconductor device according to the related art.
도 2a 내지 도 2e 는 본 발명에 따른 반도체장치의 비트라인 평탄화 방법을 나타낸 단면도이다.2A to 2E are cross-sectional views illustrating a bit line planarization method of a semiconductor device according to the present invention.
본 발명에 따른 반도체장치의 비트라인 평탄화 방법은 다음의 공정들로 이루어진다.The bit line planarization method of the semiconductor device according to the present invention consists of the following steps.
도 2a 내지 도 2e는 본 발명에 따른 반도체장치의 평탄화방법을 나타낸 것으로서 반도체장치의 수직 단면도이며, 반도체소자의 COB(capacitor over bitline) 구조에서 캐패시터 제조전 비트라인 패드와 비트라인형성용 도핑된 폴리실리콘을 에치백으로 비트라인 평탄화를 이루는 공정단면도이다.2A to 2E illustrate a planarization method of a semiconductor device according to the present invention, which is a vertical cross-sectional view of a semiconductor device, wherein a doped poly for forming a bit line pad and a bit line before forming a capacitor in a capacitor over bitline (COB) structure A cross-sectional view of a process for achieving bit line planarization with silicon etch back.
도 2a에 있어서, 반도체기판인 실리콘기판(21)상에 활성영역 격리용 필드산화막(22)을 LOCOS 공정으로 형성하여 활성영역과 필드영역을 형성한 다음 채널영역의 문턱전압을 조절하기 위한 이온주입을 실시한다. 그리고 기판(21)의 전면에 열산화공정을 실시하여 게이트산화막(23)을 형성한 다음 그(23) 위에 게이트 형성용 제 1 도전층(24)으로 도핑된 폴리실리콘 및 그(24) 위에 실리사이드 형성용 제 2 도전층(25)을 WSi를 증착하여 형성한다. 이때 제 2 도전층은 이후 형성될 게이트의 저항을 감소시키는 역할을 한다. 그다음 제 2 도전층(25) 위에 게이트 보호용 캡(capping)절연막(26)을 증착하여 형성한다.In FIG. 2A, an active region isolation field oxide layer 22 is formed on a silicon substrate 21, which is a semiconductor substrate, by an LOCOS process to form an active region and a field region, and then ion implantation for adjusting the threshold voltage of the channel region. Is carried out. Then, a thermal oxidation process is performed on the entire surface of the substrate 21 to form the gate oxide film 23, and then polysilicon doped with the first conductive layer 24 for gate formation thereon and silicide on the 24. The formation second conductive layer 25 is formed by depositing WSi. At this time, the second conductive layer serves to reduce the resistance of the gate to be formed later. Next, a gate protective capping insulating film 26 is deposited on the second conductive layer 25.
그리고 캡절연막(26)과 제 2 도전층(25)/제 1 도전층(24) 및 게이트산화막(23)의 소정부위를 사진식각공정을 실시하여 차례로 제거하여 게이트(25, 24)를 형성한다. 그리고 불순물영역(27)을 게이트(25, 24)를 마스크로 이용하는 이온주입을 통하여 형성한다. 그 다음 형성된 소자를 포함하는 기판(21)의 전면에 절연막을 증착한 후 에치백하여 게이트(24, 25) 및 잔류한 캡절연막(26) 그리고 게이트산화막(23)의 측면에 측벽(28)을 형성한다. 그 다음, 비트라인 형성전 층간절연막(interlayer dielectric)의 평탄화를 위한 제 1 절연막(29)을 일부 소자가 형성된 부위를 포함하는 기판(21)의 전면에 증착하여 형성한다. 그 후 다시 제 1 절연막(29)의 전면에 형성된 소자의 토포그라피에 기인한 골을 매꾸기 위한 충분한 두께로 평탄화용 제 2 층간절연막(210)을 형성한 다음 층간절연막(210)의 평탄화를 확보하기 위하여 씨엠피(chemical mechanical polishing)공정이나 에치백을 실시하여 층간절연막(210)의 표면을 평탄화시킨다.Then, gates 25 and 24 are formed by sequentially removing the cap insulation layer 26, the second conductive layer 25 / first conductive layer 24, and predetermined portions of the gate oxide layer 23 by performing a photolithography process. . The impurity region 27 is formed through ion implantation using the gates 25 and 24 as masks. Next, an insulating film is deposited on the entire surface of the substrate 21 including the formed device, and then etched back to form sidewalls 28 on the gates 24 and 25, the remaining cap insulating film 26, and the side surfaces of the gate oxide film 23. Form. Subsequently, a first insulating layer 29 for planarization of an interlayer dielectric is formed by depositing the entire surface of the substrate 21 including portions in which some elements are formed before the formation of the bit line. Thereafter, the second interlayer insulating film 210 for planarization is formed to a sufficient thickness to fill the valley due to the topography of the element formed on the front surface of the first insulating film 29, and then the planarization of the interlayer insulating film 210 is secured. In order to do this, the surface of the interlayer insulating film 210 is planarized by performing a chemical mechanical polishing process or an etch back.
도 2b에 있어서, 평탄화된 제 2 층간절연층(210)의 표면에 포토레지스트를 도포한 다음 사진공정을 실시하여 제 1 포토레지스트패턴(200)을 정의한다. 이때 정의된 포토레지스트패턴(200)은 비트라인과 소자의 불순물영역(27)의 연결통로를 형성하기 위하여 형성된다.In FIG. 2B, the first photoresist pattern 200 is defined by applying photoresist to the surface of the planarized second interlayer insulating layer 210 and then performing a photo process. In this case, the defined photoresist pattern 200 is formed to form a connection path between the bit line and the impurity region 27 of the device.
그리고 포토레지스트패턴(200)을 마스크로 이용한 식각공정을 실시하여 마스크로 보호되지 아니하는 부위의 제 2 층간절연층(210), 절연층(29)을 제거하여 측벽(288) 표면 및 불순물영역(27)의 일부 표면을 노출시키는 콘택홀 내지는 트렌치를 형성한다.An etching process using the photoresist pattern 200 as a mask is performed to remove the second interlayer insulating layer 210 and the insulating layer 29 of portions not protected by the mask, thereby removing the surface of the sidewall 288 and the impurity region ( A contact hole or trench is formed to expose a portion of the surface of 27).
도 2c에 있어서, 제 1 포토레지스트패턴(200)을 제거한 다음, 콘택홀 형성시 노출된 기판의 불순물영역(27)의 표면 부위에 에피택샬(epitaxial) 방법으로 도핑된 실리콘을 콘택홀 내부를 충전시키며 콘택홀의 표면을 넘치지 않는 두께로 성장시켜 비트라인용 패드(213)를 형성한다.이때 패드(213)의 형성 두께는 캡절연막(26) 위에 형성된 제 1 절연층(29)의 높이정도인 3000-10000 Å 정도로 형성한다.In FIG. 2C, after removing the first photoresist pattern 200, the doped silicon is epitaxially filled in the contact hole inside the surface of the impurity region 27 of the substrate exposed when the contact hole is formed. The bit line pad 213 is formed by growing to a thickness not exceeding the surface of the contact hole. In this case, the thickness of the pad 213 is about 3000, which is about the height of the first insulating layer 29 formed on the cap insulating film 26. Form about -10000 Å.
그리고 비트라인패드(213)위의 나머지 콘택홀을 충분히 매립하며 제 2 층간절연층(210) 표면에 비트라인용 제 3 도전층(211)을 두껍게 증착하여 형성한다. 이때 증착두께는 1000-8000 Å 정도로 형성한다.The remaining contact hole on the bit line pad 213 is sufficiently filled with a third conductive layer 211 for bit line on the surface of the second interlayer insulating layer 210. At this time, the deposition thickness is formed to about 1000-8000 kPa.
도 2d에 있어서, 제 3 도전층(211)의 표면을 에치백하여 콘택홀 상부에 형성된 제 3 도전층(211)과 그 외 나머지 부위에 형성된 제 3 도전층(211)의 표면이 같아지도록 제 3 도전층의 표면을 평탄화시킨다. 이때 에치백 후 잔류한 제 3 도전층의 두께는 300-3000 Å 정도로 한다. 그 다음 비트라인의 저항을 감소시키기 위하여 비트라인용 제 4 도전층(212)을 WSi를 증착하여 형성한다.In FIG. 2D, the surface of the third conductive layer 211 is etched back so that the surface of the third conductive layer 211 formed on the contact hole and the third conductive layer 211 formed on the remaining portions are the same. 3 Planarize the surface of the conductive layer. At this time, the thickness of the third conductive layer remaining after the etch back is about 300-3000 Pa. A fourth conductive layer 212 for the bit line is then formed by depositing WSi to reduce the resistance of the bit line.
그리고 비트라인 패턴 형성용 마스크를 형성하기 위하여 전술한 콘택홀 상부를 포함하는 부위에 제 2 포토레지스트패턴(201)을 형성한다.In order to form a mask for forming a bit line pattern, a second photoresist pattern 201 is formed in a portion including the upper portion of the contact hole.
도 2e에 있어서, 제 2 포토레지스트패턴(도시 안함)을 마스크로 이용하는 사진식각공정으로 마스크로 보호되지 아니하는 부위의 제 4 도전층(212)/제 3 도전층(211)을 식각방법으로 제거하여 비트라인(212, 211)패턴을 완성한다.In FIG. 2E, the fourth conductive layer 212 / third conductive layer 211 in a portion not protected by the mask is removed by an etching method using a photolithography process using a second photoresist pattern (not shown) as a mask. By completing the bit line (212, 211) pattern.
즉 본 발명은 표면이 평탄화된 비트라인용 평탄화층을 형성하므로서 비트라인 패턴형성시 공정 마진이 확대되고, 비트라인패턴 형성 후 다른 층간절연층(interlayer dielectric)의 평탄화공정에서도 공정 마진이 커지게 되는 장점이 있다.That is, according to the present invention, the process margin is increased when the bit line pattern is formed by forming the planarization layer for the bit line having the flattened surface, and the process margin is increased even during the planarization process of another interlayer dielectric after the bit line pattern is formed. There is an advantage.
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| KR1019980005565A KR19990070614A (en) | 1998-02-23 | 1998-02-23 | Bit line planarization method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19990070614A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100484258B1 (en) * | 2001-12-27 | 2005-04-22 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| US7598569B2 (en) | 2005-06-23 | 2009-10-06 | Seiko Epson Corporation | Semiconductor device |
| KR100926406B1 (en) * | 2005-07-06 | 2009-11-12 | 세이코 엡슨 가부시키가이샤 | Semiconductor device |
| US7777334B2 (en) | 2005-07-06 | 2010-08-17 | Seiko Epson Corporation | Semiconductor device having active element formation region provided under a bump pad |
| US7936064B2 (en) | 2005-07-19 | 2011-05-03 | Seiko Epson Corporation | Semiconductor device |
| US8878365B2 (en) | 2005-07-13 | 2014-11-04 | Seiko Epson Corporation | Semiconductor device having a conductive layer reliably formed under an electrode pad |
-
1998
- 1998-02-23 KR KR1019980005565A patent/KR19990070614A/en not_active Application Discontinuation
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100484258B1 (en) * | 2001-12-27 | 2005-04-22 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| US7598569B2 (en) | 2005-06-23 | 2009-10-06 | Seiko Epson Corporation | Semiconductor device |
| KR100926406B1 (en) * | 2005-07-06 | 2009-11-12 | 세이코 엡슨 가부시키가이샤 | Semiconductor device |
| US7649260B2 (en) | 2005-07-06 | 2010-01-19 | Seiko Epson Corporation | Semiconductor device |
| US7777334B2 (en) | 2005-07-06 | 2010-08-17 | Seiko Epson Corporation | Semiconductor device having active element formation region provided under a bump pad |
| US8878365B2 (en) | 2005-07-13 | 2014-11-04 | Seiko Epson Corporation | Semiconductor device having a conductive layer reliably formed under an electrode pad |
| US7936064B2 (en) | 2005-07-19 | 2011-05-03 | Seiko Epson Corporation | Semiconductor device |
| US8441125B2 (en) | 2005-07-19 | 2013-05-14 | Seiko Epson Corporation | Semiconductor device |
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