KR20060001151A - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can simultaneously solve the isolation problem and the bit line hard mask attack occurring during the chemical mechanical polishing process for the isolation of the contact plug for the storage node, the present invention, Forming a first insulating film on the film; Forming a bit line on the first insulating layer; Forming a second insulating film on the bit line; Performing a chemical mechanical polishing process on the target to expose the upper part of the bit line to substantially planarize the bit line and the second insulating layer; Forming a mask pattern on the planarized front surface; Etching the second insulating layer and the first insulating layer between the bit lines using the mask pattern as an etch mask to form an open portion exposing the conductive layer when the second insulating layer and the first insulating layer are aligned with the side surfaces of the bit line; Removing the mask pattern; Depositing a conductive film for plug formation on the entire surface where the open portion is formed; And removing the plug forming conductive film on the bit line and the second insulating layer by performing an etch back process to form a plug electrically connected to the conductive film and being isolated through the open portion. Provide a method.

Contact plugs for etch backs, chemical mechanical polishing (CMP), plugs, bitlines, and storage nodes.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}             

1A to 1D are cross-sectional views illustrating a process of forming a contact plug for a storage node according to the prior art.

FIG. 2 is a planar SEM photograph showing a semiconductor device having a contact plug for a storage node. FIG.

3 is a planar photograph illustrating a case where isolation between contact plugs for storage nodes is not sufficient.

4A through 4C are cross-sectional views illustrating a process of forming a contact plug for a storage node according to an embodiment of the present invention.

Explanation of symbols on main parts of drawing

400: substrate 401: first interlayer insulating film

402: cell contact plug 403: second interlayer insulating film

404: bit line conductive film 405: bit line hard mask

406: third interlayer insulating film 410: contact plug for storage node

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact plug for a storage node.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, as the design rules decrease in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

Meanwhile, as the high integration of semiconductor devices is accelerated, various elements of the semiconductor devices have a stacked structure, and thus, a contact plug (or pad) concept has been introduced.

In order to form such a contact, there is a difficulty in etching between structures having a high aspect ratio, and at this time, an SAC process for obtaining an etching profile using an etching selectivity between two materials, for example, an oxide film and a nitride film, has been introduced.

For the SAC process, CF and CHF-based gases are used, and an etch stop film and a spacer using a nitride film are needed to prevent attack on the conductive pattern below.

Hereinafter, a storage node contact plug process using the aforementioned SAC etching process will be described, and FIGS. 1A to 1D are cross-sectional views illustrating a process of forming a contact plug for a storage node according to the prior art.

First, as shown in FIG. 1A, a first interlayer insulating film 101 is formed on a semiconductor substrate 100 on which various elements for forming semiconductor devices such as wells and transistors are formed.

When the first interlayer insulating film 101 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, BPSG (Boro-Phopho-Silicate-Glass) film, PSG (Phospho-Silicate-Glass) film, TEOS (Tetra-Ethyl-Ortho-Silicate) film, HDP (High Density Plasma) film, SOG (Spin On Glass) film, or APL (Advanced Planarization Layer) film, etc. It is available.

For reference, the gate electrode pattern is omitted here.

Subsequently, the first interlayer insulating layer 101 is selectively etched to form a contact hole exposing an impurity diffusion region (not shown) of the substrate 100. At this time, the SAC etching process is applied.

Subsequently, a conductive film such as polysilicon is deposited to fill the contact hole, and then a planarization process is performed on the target to which the gate hard mask is exposed to form a plurality of isolated cell contact plugs 102.                         

Subsequently, a second interlayer insulating film 103 is formed on the entire surface where the cell contact plug 102 is formed. The second interlayer insulating film 103 uses an oxide film-based material film or a low dielectric constant film that is substantially the same as the first interlayer insulating film 102.

Subsequently, although not shown in the drawing, the second interlayer insulating film 103 is selectively etched to expose a portion of the cell contact plug 102 to define a bit line formation region, and then similar to the process of forming the cell contact plug 102. The process forms a bitline contact plug (not shown). Subsequently, a bit line B / L electrically connected to the bit line contact plug is formed.

The bit line has a structure in which the bit line hard mask 105 / bit line conductive film 104 is stacked. The bit line conductive film 104 typically uses polysilicon, W, WN, WSi _x alone or in combination thereof. Ti, TiN, TiSi ₂ to prevent diffusion of metal into the substrate or cell contact plug when the bit line conductive film 104 is deposited between the bit line and the bottom bit line contact plug or bit line and cell contact plug 102. A barrier film made of or the like is formed, not shown here.

The bit line hard mask 105 is to protect the bit line conductive layer 104 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for forming the contact hole for the subsequent storage node, the interlayer insulating layer and the etching rate Use materials that differ significantly. For example, when an oxide-based layer is used as an interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as an interlayer insulation film, an oxide-based material is used. use.

Subsequently, spacers are formed to prevent attack of the underlying structure such as the bit line (B / L) in an etching process using a subsequent SAC method along the profile in which the bit lines (B / L) are formed. Omit.

In the case of a spacer, an insulating film based on a nitride film is deposited along the profile in which the bit lines B / L are formed, and then formed on the sidewalls of the bit lines B / L through front etching.

Next, an oxide-based third interlayer insulating film 106 is formed on the entire structure where the bit lines B / L are formed. The third interlayer insulating film 106 is also used as a material similar to the first and second interlayer insulating films 101 and 103.

Subsequently, a mask pattern 107 is formed on the third interlayer insulating layer 106 to form a contact hole for a storage node.

The mask pattern 107 includes a structure of a photoresist and a photoresist / sacrificial hard mask.

The sacrificial hard mask is used to compensate for the weak etching resistance of the photoresist pattern, and polysilicon, silicon nitride, tungsten, and the like are used.

Meanwhile, an anti-reflection film is generally used for the purpose of preventing diffuse reflection and increasing adhesion between the photoresist pattern and the sacrificial hard mask or the photoresist and the third interlayer insulating film.

Subsequently, as shown in FIG. 1B, the third interlayer insulating film 106 and the second interlayer insulating film 103 are etched using the mask pattern 107 as an etch mask to align the side surfaces of the bit lines B / L. As a result, an open portion 108 that exposes the cell contact plug 102 to which the storage node contacts are to be formed, that is, forms a contact hole for the storage node.

The process of forming the open portion 108 is generally a SAC etching process using an etching selectivity of the third and second interlayer insulating films 106 and 103 and the bit line hard mask 105. The SAC etching process of etching the third and second interlayer insulating films 106 and 103 with an etching mask to stop the etching from the etching stop film (not shown), and removing the etching stop film and the spacer, thereby removing the cell contact plug 102. ) Is divided into an open process and a cleaning process for extending the opening of the open portion 108 and removing the etching residue.

In such an etching process, CxFy (x, y is 1 to 10) gas, such as CF ₄ , and CaHbFc (a, b, c is 1 to 10) gas, such as CH ₂ F ₂ , are mixed and used.

Subsequently, as shown in FIG. 1C, after removing the mask pattern 107, the conductive layer 109a for forming the contact plug for the storage node is deposited on the entire surface where the open portion 108 is formed to form the open portion 108. It is electrically connected to the exposed cell contact plug 102.

Subsequently, as illustrated in FIG. 1D, a chemical mechanical polishing process (CMP) is performed on the target to which the bit line hard mask 105 is exposed, thereby performing the third interlayer insulating film 406 and the bit line hard. By removing the conductive film 109a on the mask 405, the isolated contact plug for storage node 109b is formed.                         

Here, the conductive film 109a for forming the contact plug for the storage node includes a polysilicon film.

FIG. 2 is a planar SEM photograph illustrating a semiconductor device in which a contact plug for a storage node is formed.

Referring to FIG. 2, a plurality of bit lines B / L in a line form are arranged at regular intervals, and are arranged for side surfaces of the bit lines B / L and are isolated by a CMP process. It can be seen that the contact plug is formed.

On the other hand, when using the CMP process when plug isolation as shown in Figure 1d may cause the following problems.

A) If the polishing is insufficient, the isolation between the plugs may not be possible.

B) Even if the grinding is sufficient, there may be some places where the isolation between the plugs is not possible or the bridge between the plugs may occur because the isolation between the plugs is insufficient.

A. Differences in Topology and Pattern Formation in the Die Between the Gate Electrode and Bitline

N. Reasons why grinding does not occur uniformly in wafer due to the characteristics of CMP equipment

C. Why does the process not work uniformly before the CMP process?

3 is a planar view illustrating a case where isolation between contact plugs for storage nodes is not sufficient.

Referring to FIG. 3, since the isolation between the contact plugs SNC for the storage node is not sufficient, the possibility of a bridge between plugs in an 'A' portion is increased.

C) If the polishing process is excessively performed to solve the problem in b), the bit line hard mask may be excessively polished in some areas of the wafer, which may cause the bit line attack.

The present invention has been proposed to solve the above problems of the prior art, the semiconductor device manufacturing that can simultaneously solve the isolation problem and bit line hard mask attack occurring during the chemical mechanical polishing process for the isolation of the contact plug for storage nodes Its purpose is to provide a method.

In order to achieve the above object, the present invention, forming a first insulating film on the conductive film; Forming a bit line on the first insulating layer; Forming a second insulating film on the bit line; Performing a chemical mechanical polishing process on the target to expose the upper part of the bit line to substantially planarize the bit line and the second insulating layer; Forming a mask pattern on the planarized front surface; Etching the second insulating layer and the first insulating layer between the bit lines using the mask pattern as an etch mask to form an open portion exposing the conductive layer when the second insulating layer and the first insulating layer are aligned with the side surfaces of the bit line; Removing the mask pattern; Depositing a conductive film for plug formation on the entire surface where the open portion is formed; And removing the plug forming conductive film on the bit line and the second insulating layer by performing an etch back process to form a plug electrically connected to the conductive film and being isolated through the open portion. Provide a method.

After the formation of the bit line and the deposition of the interlayer dielectric layer, the CMP process is performed to expose the bit line hard mask, thereby forming an open portion exposing the cell contact plug to form a storage node. In addition, the conductive film for forming a plug is deposited and the contact plug for the storage node is isolated through an etch back process rather than a CMP.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4A to 4C are cross-sectional views illustrating a process of forming a contact plug for a storage node according to an embodiment of the present invention, and with reference to this, a process of forming a contact plug for a storage node according to an embodiment of the present invention will be described.

On the other hand, in the open portion forming process of the present invention to be described later can be applied to various forms such as T-type, I-type, hole-type in the form of a pattern for forming a contact hole for a storage node.

First, as shown in FIG. 4A, a first interlayer insulating film 401 is formed on a semiconductor substrate 400 on which various elements for forming semiconductor devices such as wells and transistors are formed.

When the first interlayer insulating film 401 is used as an oxide film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, an SOG film, or an APL film is used. A low dielectric constant film can be used.

For reference, the gate electrode pattern does not appear in the cross section corresponding to the embodiment of the present invention.

Subsequently, the first interlayer insulating layer 401 is selectively etched to form a contact hole exposing an impurity diffusion region (not shown) of the substrate 400. At this time, the SAC etching process is applied.

Subsequently, a conductive film such as polysilicon is deposited to fill the contact hole, and then a planarization process is performed on the target to which the gate hard mask is exposed to form a plurality of isolated cell contact plugs 402.

Subsequently, a second interlayer insulating film 403 is formed on the entire surface where the cell contact plug 402 is formed. The second interlayer insulating film 403 uses an oxide film-based material film or a low dielectric constant film that is substantially the same as the first interlayer insulating film 402.

Subsequently, although not shown in the drawing, the second interlayer insulating film 403 is selectively etched to expose a portion of the cell contact plug 402 to define a bit line formation region, and then the process of forming the cell contact plug 402 A similar process forms bitline contact plugs (not shown). Subsequently, a bit line B / L electrically connected to the bit line contact plug is formed.

The bit line has a structure in which a bit line hard mask 405 / bit line conductive film 404 is stacked. The bit line conductive film 404 typically uses polysilicon, W, WN, WSi _x alone or in combination thereof. Ti, TiN, TiSi ₂ to prevent diffusion of metal into the substrate or cell contact plug during bit line conductive film 404 deposition between the bit line and the lower bit line contact plug or bit line and cell contact plug 402. A barrier film made of or the like is formed, not shown here.

The bit line hard mask 405 is to protect the bit line conductive layer 404 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for forming the contact hole for the subsequent storage node, the interlayer insulating layer and the etching rate Use materials that differ significantly. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

Subsequently, spacers are formed to prevent attack of the underlying structure such as the bit line (B / L) in an etching process using a subsequent SAC method along the profile in which the bit lines (B / L) are formed. Omit.                     

In the case of a spacer, an insulating film based on a nitride film is deposited along the profile in which the bit lines B / L are formed, and then formed on the sidewalls of the bit lines B / L through front etching.

Next, an oxide film-based third interlayer insulating film 406 is formed on the entire structure where the bit lines B / L are formed. The third interlayer insulating film 406 is also used as a material similar to the first and second interlayer insulating films 401 and 403.

Subsequently, the third interlayer insulating film 406 and the bit line hard mask 404 are planarized by performing the CMP process 407 on the target to which the bit line hard mask 404 is exposed to remove the third interlayer insulating film 406. Let's do it.

In this case, as the abrasive, ammonia steamed (Fumed silica), gelatinous silica (Colloidal silica) or cerium oxide (Ceria) is used.

By planarizing the third interlayer insulating layer 406, an etching target may be reduced when forming a contact hole for a subsequent storage node.

Subsequently, as illustrated in FIG. 4B, a mask pattern 408 for forming a contact hole for a storage node is formed on the planarized thirty-third interlayer insulating layer 406.

The mask pattern 408 includes a structure of photoresist and photoresist / sacrificial hardmask.

The sacrificial hard mask is used to compensate for the weak etching resistance of the photoresist pattern, and polysilicon, silicon nitride, tungsten, and the like are used.

Meanwhile, an anti-reflection film is generally used for the purpose of preventing diffuse reflection and increasing adhesion between the photoresist pattern and the sacrificial hard mask or the photoresist and the third interlayer insulating film.

Subsequently, the third interlayer insulating layer 406 and the second interlayer insulating layer 403 are etched using the mask pattern 408 as an etch mask to align the sidewalls of the bit lines B / L, thereby forming a storage node contact. An open portion 409 exposing the plug 402, that is, a contact hole for the storage node is formed.

The above-described open portion 409 forming process is a SAC etching process using an etching selectivity of the third interlayer insulating film 406, the second interlayer insulating film 403, and the bit line hard mask 405. SAC etching process of etching the third interlayer insulating film 406 and the second interlayer insulating film 403 by the etching mask to stop the etch stop in the etch stop film (not shown), and removing the etch stop film and the spacer, etc. The plug 402 is divided into an open process and a cleaning process for extending the opening of the open portion 108 and removing the etching residue.

In such an etching process, CxFy (x, y is 1 to 10) gas, such as CF ₄ , and CaHbFc (a, b, c is 1 to 10) gas, such as CH ₂ F ₂ , are mixed and used.

On the other hand, since the third interlayer insulating film 406 is removed to the bit line hard mask 404 by the CMP process, the etching target is reduced, thereby reducing the generation of fail during the SAC process.

Subsequently, as shown in FIG. 4C, after removing the mask pattern 408, a conductive film for forming a contact plug for a storage node is deposited on the entire surface where the open portion 409 is formed, thereby exposing the cell exposed through the open portion 409. The contact plug 402 is electrically connected.                     

Subsequently, an etch back process is performed on the target to which the bit line hard mask 405 is exposed, thereby removing the third interlayer insulating film 406 and the conductive film on the bit line hard mask 405, thereby maintaining the number of isolated north node storage nodes. The plug 410 is formed.

Here, the conductive film for forming the contact plug for the storage node includes a polysilicon film. In the etchback process, a fluorine-based gas such as CF ₄ or SF ₆ is used, or a chlorine-based gas such as Cl ₂ or CCl ₄ is used.

According to the present invention, the CMP process is performed to expose the bit line hard mask after the formation of the bit line and the deposition of the interlayer insulating layer, thereby planarizing the interlayer insulating layer and the upper part of the bit line, and then exposing the cell contact plug to form a storage node. After forming the open part to be formed, by depositing a conductive film for forming a plug and isolating the contact plug for the storage node through an etch back process other than the CMP, it was seen through the embodiment has the following advantages.

A) It can solve the problem of the isolation failure between the contact plugs for storage nodes, which occurs when the polishing is insufficient.

B) Solving a problem of poor isolation between storage node contact plugs in some areas of the die, which may occur due to a difference in topology and pattern formation in the die between the gate electrode and the bit line.

C) Due to the characteristics of CMP equipment, the polishing uniformity varies depending on the position within the wafer, which can solve the problem of poor isolation between plugs in some areas of the wafer.

D) The problem of poor isolation between contact plugs for storage nodes can be solved because the process was not uniformly performed in the factory before CMP.

E) By preventing excessive grinding, it is possible to secure a full margin in a subsequent process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can solve the isolation problem and the bit line hard mask attack during the chemical mechanical polishing process for the isolation of the contact plug for the storage node, thereby improving the yield of the semiconductor device. have.

Claims (7)

Forming a first insulating film on the conductive film; Forming a bit line on the first insulating layer; Forming a second insulating film on the bit line; Performing a chemical mechanical polishing process on the target to expose the upper part of the bit line to substantially planarize the bit line and the second insulating layer; Forming a mask pattern on the planarized front surface; Etching the second insulating layer and the first insulating layer between the bit lines using the mask pattern as an etch mask to form an open portion exposing the conductive layer when the second insulating layer and the first insulating layer are aligned with the side surfaces of the bit line; Removing the mask pattern; Depositing a conductive film for plug formation on the entire surface where the open portion is formed; And Performing an etch back process to remove the plug forming conductive film on the bit line and the second insulating film to form an isolated and electrically connected plug through the open part Semiconductor device manufacturing method comprising a. The method of claim 1, The plug forming conductive film includes a polysilicon film. The method of claim 2, In the step of performing the etch back process, a method of manufacturing a semiconductor device, characterized in that using a florin gas or chlorine gas. The method of claim 1, And the conductive film comprises a cell contact plug. The method of claim 1, And the first insulating film and the second insulating film comprise an oxide film. The method of claim 5, In the step of substantially planarizing the bit line and the second insulating film through the chemical mechanical polishing process, a semiconductor device manufacturing method characterized in that any one of silica, gelatinous silica or cerium oxide steamed with ammonia as an abrasive. . The method of claim 5, In the etching of the second insulating layer and the first insulating layer, A method for manufacturing a semiconductor device, comprising using a self-aligned contact etching process.

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