CN116113231A

CN116113231A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN116113231A
Application number: CN202111311525.3A
Authority: CN
Inventors: 于业笑; 陈龙阳; 刘忠明
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-11-08
Filing date: 2021-11-08
Publication date: 2023-05-12
Also published as: WO2023077666A1; US20230180465A1

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of more bit line loss, and the manufacturing method of the semiconductor structure comprises the following steps: forming a spin-on hard mask layer on a substrate, wherein a plurality of spaced active areas are arranged in the substrate, a plurality of spaced bit lines extending along a first direction are arranged on the substrate, each bit line is electrically connected with at least one active area, and the spin-on hard mask layer is filled between the bit lines and covers the bit lines; removing part of the spin-on hard mask layer to form a plurality of first channels arranged at intervals; forming a first sacrificial layer in the first channel; removing the spin-on hard mask layer between the first sacrificial layers to form a second channel; forming a first support layer in the second channel; the first sacrificial layer is removed, and a first channel between adjacent bit lines is extended to the active region. The spin-on hard mask layer is utilized to reduce bit line loss in subsequent etches.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

With the development of semiconductor technology, semiconductor structures are becoming more and more widely used. Dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is becoming a semiconductor memory device commonly used in electronic devices. The dynamic random access memory includes a plurality of memory cells, each memory cell including a transistor and a capacitor. The capacitor stores data information, and the transistor controls reading and writing of the data information in the capacitor. The grid electrode of the transistor is electrically connected with a Word Line (WL) and is controlled to be turned on and off by the voltage on the Word Line; one of a source and a drain of the transistor is electrically connected to a Bit Line (BL), and the other of the source and the drain is electrically connected to a capacitor, and data information is stored or output through the Bit Line.

In the related art, bit lines are generally formed on a substrate, the bit lines are arranged at intervals and extend along a first direction, and then a first supporting layer is formed between adjacent bit lines, wherein the bit lines and the first supporting layer enclose a filling hole. However, during the formation of the filling hole, the part of the bit line far from the substrate is more lost, which affects the performance of the bit line.

Disclosure of Invention

In view of the above, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which are used for reducing damage to a bit line and ensuring performance of the bit line.

A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: forming a spin-on hard mask layer on a substrate, wherein a plurality of active areas which are arranged at intervals are arranged in the substrate, a plurality of bit lines which are arranged at intervals and extend along a first direction are arranged on the substrate, each bit line is at least electrically connected with one active area, and the spin-on hard mask layer is filled between the bit lines and covers the bit lines; removing part of the spin-on hard mask layer to form a plurality of first channels which are arranged at intervals and extend along the second direction; forming a first sacrificial layer in the first channel, wherein the first sacrificial layer is filled in the first channel; removing the spin-on hard mask layer between the first sacrificial layers to form a second channel; forming a first supporting layer in the second channel, wherein the first supporting layer is filled in the second channel; the first sacrificial layer is removed and the first channel between adjacent bit lines is extended to the active region.

The manufacturing method of the semiconductor structure provided by the embodiment of the application has at least the following advantages:

according to the manufacturing method of the semiconductor structure, the spin-on hard mask layer filled between the bit lines and covering the bit lines is formed, and the characteristic that the spin-on hard mask layer is difficult to etch is utilized, so that the spin-on hard mask layer and the bit lines have a high selection ratio, the loss of the part of the bit lines away from the substrate in the subsequent etching is reduced, and the performance of the bit lines is guaranteed.

The second aspect of the embodiments of the present application provides a semiconductor structure obtained by the method for manufacturing a semiconductor structure, so that the semiconductor structure has at least the advantage of less bit line loss, and specific effects are described above and will not be repeated herein.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief description will be given below of the drawings that are needed in the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a substrate and bit lines according to an embodiment of the present application;

FIG. 3 is a perspective view of the photoresist layer formed according to an embodiment of the present application;

FIG. 4 is a schematic cross-sectional view at A-A of FIG. 3;

FIG. 5 is a perspective view of the first sacrificial layer formed in an embodiment of the present application;

FIG. 6 is a schematic cross-sectional view at B-B in FIG. 5;

FIG. 7 is a perspective view of an embodiment of the present application after forming a second channel;

FIG. 8 is a perspective view of the first support layer formed in an embodiment of the present application;

FIG. 9 is a perspective view of the spin-on hard mask layer after removal of the remaining spin-on hard mask layer in an embodiment of the present application;

FIG. 10 is a schematic cross-sectional view at C-C of FIG. 9;

fig. 11 is a schematic structural diagram of the contact hole in the embodiment of the present application after extending to the active area;

fig. 12 is a schematic structural diagram of the embodiment of the present application after forming the first trench;

fig. 13 is a schematic structural diagram of the first filling layer after formation in the embodiment of the present application;

FIG. 14 is a schematic view of a structure after exposing a second sacrificial layer in an embodiment of the present application;

fig. 15 is a schematic structural diagram of the first etching groove formed in the embodiment of the present application;

FIG. 16 is a schematic view illustrating a structure of a first etching trench penetrating through a silicon-containing anti-reflective layer according to an embodiment of the present disclosure;

fig. 17 is a schematic structural diagram of the first trench formed in the embodiment of the present application;

FIG. 18 is a schematic view of a structure after forming a first intermediate groove in an embodiment of the present application;

FIG. 19 is a schematic view of a structure after forming a third sacrificial layer according to an embodiment of the present application;

FIG. 20 is a schematic diagram of a structure after removing a portion of the third sacrificial layer according to an embodiment of the present disclosure;

FIG. 21 is a schematic diagram of a structure after forming a first sacrificial layer according to an embodiment of the present application;

FIG. 22 is a schematic diagram of a structure after removing the film layer over the spin-on hard mask layer in an embodiment of the present application;

fig. 23 is a schematic structural diagram of the first conductive layer formed in the embodiment of the present application;

fig. 24 is a schematic structural diagram of the conductive post formed in the embodiment of the present application;

fig. 25 is a schematic structural diagram of the first protective layer after formation in the embodiment of the present application.

Reference numerals illustrate:

100-substrate; 110-a substrate; 111-active region;

112-shallow trench isolation; 113-word lines; 120-an insulating layer;

130-a barrier layer; 140-bit line plugs; 150-bit lines;

151-a second conductive layer; 152-a second support layer; 153-oxide layer;

200-spin-coating a hard mask layer; 210-a first channel; 211-a second trench;

212-filling the hole; 220-a first sacrificial layer; 230-a second channel;

240-a first support layer; 250-conductive posts; 251-a first conductive layer;

260-a protective layer; 300-an intermediate layer; 400-a silicon-containing antireflective layer;

410-a first trench; 420-a second sacrificial layer; 430-a first fill layer;

440-a first etch tank; 500-a first mask layer; 510-a first base layer;

520-a first antireflective layer; 600-a second mask layer; 610-a second base layer;

620-a second anti-reflective layer; 630-a first intermediate tank; 640-a third sacrificial layer;

650-a second intermediate tank; 700 photoresist layer.

Detailed Description

In order to reduce the bit line loss in the manufacturing process of the semiconductor structure, the embodiment of the application provides a manufacturing method of the semiconductor structure, by forming a spin-on hard mask layer filled between bit lines and covering the bit lines, the spin-on hard mask layer and the bit lines are utilized to have a higher selection ratio, so that the loss of the bit lines in the subsequent etching process is reduced, and the performance of the bit lines is ensured.

In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, the following description will make the technical solutions of the embodiments of the present application clear and complete with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which are within the scope of the protection of the present application, will be within the purview of one of ordinary skill in the art without the exercise of inventive faculty.

Referring to fig. 1, an embodiment of the present application provides a method for manufacturing a semiconductor structure, which at least includes the following steps:

step S101: and forming a spin-on hard mask layer on the substrate, wherein a plurality of active areas are arranged in the substrate at intervals, a plurality of bit lines are arranged on the substrate at intervals and extend along the first direction, each bit line is electrically connected with at least one active area, and the spin-on hard mask layer is filled between the bit lines and covers the bit lines.

Referring to fig. 2 to 4, the filling patterns in the drawings in the embodiments of the present application are only used to distinguish different structures in the drawings, and are not used to represent the materials of the structures in the drawings. As shown in fig. 2 to 4, the substrate 100 serves to support a film layer, such as a bit line 150 and a spin-on hard mask layer 200, formed on the substrate 100.

As shown in fig. 2 to 4, a plurality of active regions 111 are disposed in the substrate 100 at intervals. Each active region 111 may be defined by a shallow trench isolation 112 (Shallow Trench Isolation, STI for short). Specifically, a portion of the substrate 100 is removed to a predetermined depth by an etching process to form a recess surrounding the plurality of active regions 111, and an insulating material is deposited in the recess to isolate the active regions 111 from each other. The insulating material may be silicon oxide or silicon nitride, or the like.

Illustratively, the base 100 may include a substrate 110, an insulating layer 120, and a barrier layer 130, which are sequentially stacked. The substrate 110 may be a semiconductor substrate 110, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a germanium arsenic substrate, a silicon-on-insulator (Silicon On Insulator, SOI) substrate, or a germanium-on-insulator (Germanium On Insulator, GOI) substrate. The substrate 110 may be doped or undoped, and the substrate 110 may be an N-type substrate or a P-type substrate, for example.

The active region 111 is formed in the substrate 110 and is exposed to the upper surface of the substrate 110. A plurality of word lines 113 are also formed in the substrate 110 at intervals. As shown in fig. 4, a plurality of word lines 113 extend in the second direction, and each word line 113 is insulated from the active region 111. The Word lines 113 may be Buried Word Lines (BWL) and the active regions 111 are disposed obliquely with respect to an extending direction of the Word lines 113 to increase an arrangement density of the active regions 111.

With continued reference to fig. 2 and 3, an insulating layer 120 is formed on the substrate 110 covering the active region 111 to isolate and protect the active region 111. The material of the insulating layer 120 may be the same as the insulating material in the shallow trench isolation 112, and after the insulating material is deposited to form the shallow trench isolation 112, the insulating material is continuously deposited to form the insulating layer 120, so as to simplify the manufacturing steps of the semiconductor structure.

A barrier layer 130 is formed on the insulating layer 120, the barrier layer 130 corresponding to the bit line 150. The material of the barrier layer 130 may be silicon nitride or silicon oxynitride, which may be subsequently used as an etch stop layer to reduce the etching of the insulating layer 120. A plurality of contact holes are formed in the barrier layer 130 and the insulating layer 120, each of which exposes the active region 111. Illustratively, two contact holes correspond to one active region 111, each of which exposes one end of the active region 111.

With continued reference to fig. 2 and 3, a plurality of bit lines 150 are disposed on the substrate 100 and spaced apart, each bit line 150 extending along a first direction, each bit line 150 being electrically connected to at least one active region 111. Illustratively, a Bit Line plug (Bit Line Contact) 140 is disposed in the Contact hole, the Bit Line plug 140 being in Contact with the active region 111. The bit line plugs 140 may have a plurality of pillar structures filled in the contact holes, or, as shown in fig. 2, the bit line plugs 140 may have a comb-tooth structure, each tooth being filled in a contact hole. During the etching formation of the bit line plugs 140 and the bit lines 150, the barrier layer 130 is also etched such that the barrier layer 130 corresponds to the bit line plugs 140, i.e., the bit line plugs 140 located outside the contact holes are disposed on the barrier layer 130. It will be appreciated that the A-A cross-section shown in fig. 4 is a plane between adjacent bit lines in which the barrier layer 130 is not truncated.

With continued reference to fig. 2 and 3, in some possible examples, the bit line 150 includes a second conductive layer 151, and a second support layer 152 overlying the second conductive layer 151. The second conductive layer 151 extends in the first direction and contacts the bit line plug 140, and electrical connection of the bit line 150 and the active region 111 is achieved through the bit line plug 140. As shown in fig. 2 and 3, the second support layer 152 may also cover the substrate 100 between the second conductive layers 151.

As shown in fig. 2, the second supporting layer 152 is further provided with an oxide layer 153 located beside the second conductive layer 151, for example, two sides of the second conductive layer 151 are respectively provided with an oxide layer 153, and the oxide layer 153 is not in contact with the second conductive layer 151. Oxide layer 153 is not shown in fig. 3.

As shown in fig. 2, the material of the bit line plug 140 may be polysilicon (poly-silicon), the second conductive layer 151 may be a metal layer or a metal stack, for example, the second conductive layer 151 includes a titanium nitride layer contacting the bit line plug 140, and a tungsten layer on the titanium nitride layer, and the second supporting layer 152 may be a nitride layer, for example, a silicon nitride layer. Nitride, oxide, nitride (NON) are sequentially disposed in a direction away from the sidewall of the second conductive layer 151.

Referring to fig. 3 and 4, a Spin on hard mask layer 200 (SOH) fills between the bit lines 150 and covers the bit lines 150. The spin-on hard mask layer 200 may have a larger selectivity to the second support layer 152 of the bit line 150, so that the etching loss of the second support layer 152 is smaller in the subsequent etching process of the spin-on hard mask layer 200, thereby reducing the loss of the bit line 150 and ensuring the performance of the bit line 150. Illustratively, the spin-on hard mask layer 200 to the second support layer 152 has a selectivity of greater than or equal to 5.

Step S102: and removing part of the spin-on hard mask layer to form a plurality of first channels which are arranged at intervals and extend along the second direction.

The dry etching or the wet etching removes a portion of the spin-on hard mask layer 200 (refer to fig. 4) to form a plurality of first trenches spaced apart and extending in the second direction. The second direction is angled from the first direction, e.g., the second direction is perpendicular to the first direction. After forming the first trench, the spin-on hard mask layer 200 is separated into a plurality of blocks by the first trench.

It is understood that each first trench includes a second trench located above the bit line and extending in the second direction, and a filling hole located between adjacent bit lines and communicating with the second trench. That is, in the process of forming the first trench, a second trench is formed in the spin-on hard mask layer 200 above the bit lines, and a filling hole is formed in the spin-on hard mask layer 200 between the bit lines, the second trench being in communication with the filling hole located below the second trench.

Step S103: a first sacrificial layer is formed in the first channel, and the first sacrificial layer is filled in the first channel.

Referring to fig. 5 and 6, a first sacrificial layer 220 is deposited within the first trench, the first sacrificial layer filling the first trench. Illustratively, the first sacrificial layer 220 is formed by chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition, PVD for short), atomic layer deposition (Atomic Layer Deposition, ALD for short), or the like, and the material of the first sacrificial layer 220 may be an oxide, such as silicon oxide, so as to facilitate subsequent removal.

Step S104: and removing the spin-on hard mask layer between the first sacrificial layers to form a second channel.

Referring to fig. 7, after the first sacrificial layers 220 are formed, the spin-on hard mask layer 200 between the first sacrificial layers 220 is etched away. It will be appreciated that the spin-on hard mask layer 200 is removed in two steps, a first trench is formed after removing a portion of the spin-on hard mask layer 200, and a second trench 230 is formed after removing the remaining spin-on hard mask layer 200. The shape of the second channel 230 is substantially the same as the shape of the first channel.

Step S105: and forming a first supporting layer in the second channel, wherein the first supporting layer is filled in the second channel.

Referring to fig. 7 and 8, a first support layer 240 is deposited within the second channel 230, the first support layer 240 filling the second channel 230. The material of the first supporting layer 240 may be the same as that of the second supporting layer 152 of the bit line 150, and may be an insulating material, such as silicon nitride.

Step S106: the first sacrificial layer is removed, and a first channel between adjacent bit lines is extended to the active region.

Referring to fig. 8 to 11, the first sacrificial layer 220 is etched and removed, and illustratively, the first sacrificial layer 220 is removed by a wet method using an acidic etchant, and the first sacrificial layer 220 has a larger selectivity than the first supporting layer 240 to reduce damage of the first supporting layer 240. After the first sacrificial layer 220 is removed, the first channel 210 is exposed. As shown in fig. 11, the first channel 210 between adjacent bit lines 150 also extends to the active region 111 to expose the active region 111 within the first channel 210.

In one possible embodiment, the base 100 includes a substrate 110, an insulating layer 120 disposed on the substrate 110, and a barrier layer 130 disposed on the insulating layer, the substrate 110 having a plurality of active regions 111 disposed therein, the insulating layer 120 overlying the active regions 111. Accordingly, removing the first sacrificial layer 220 and extending the first channel 210 between adjacent bit lines 150 to the active region 111 specifically includes:

Referring to fig. 8 to 10, the first sacrificial layer 220 is etched to expose the first trenches 210, each of the first trenches 210 including a second trench 211 located above the bit lines 150 and extending in the second direction, and a filling hole 212 located between adjacent bit lines 150 and communicating with the second trench 211. As shown in fig. 9 and 10, the second support layer 152 extending in the second direction and the first support layer 240 extending in the first direction enclose the filling hole 212.

Referring to fig. 11, the insulating layer 120 is etched along the filling hole 212 of the first trench 210 such that the filling hole 212 exposes the active region 111. The filling hole 212 penetrates the insulating layer 120 and extends to the active region 111 as shown in fig. 11, so that the active region 111 is exposed in the filling hole 212, facilitating the electrical connection of the active region 111 with the conductive pillar 250 formed in the filling hole 212. It should be noted that, when the second supporting layer 152 further covers the substrate 100, the filling hole 212 further penetrates the second supporting layer 152, i.e., the filling hole 212 penetrates the second supporting layer 152 and the insulating layer 120 and extends to the active region 111.

In summary, in the method for manufacturing a semiconductor structure according to the embodiments of the present application, by forming the spin-on hard mask layer 200 that fills between the bit lines 150 and covers the bit lines 150, the loss of the portion of the bit lines 150 away from the substrate 100 during the subsequent etching is reduced by using a higher selectivity of the spin-on hard mask layer 200 to the bit lines 150 (refer to fig. 2), so as to ensure the performance of the bit lines 150.

In some possible examples, referring to fig. 12 to 17, removing a portion of the spin-on hard mask layer, forming a plurality of first trenches disposed at intervals and extending in the second direction (step S102) may include the steps of:

step S1021: an intermediate layer and a silicon-containing anti-reflection layer are formed on the spin-on hard mask layer, wherein the intermediate layer and the silicon-containing anti-reflection layer are sequentially stacked, and the silicon-containing anti-reflection layer is provided with a plurality of first grooves which are arranged at intervals and extend along the second direction.

Referring to fig. 12, an intermediate layer 300 may be formed on the spin-on hard mask layer 200 by a deposition process and covers the spin-on hard mask layer 200. A silicon-containing anti-reflective layer 400 (SiARC) is formed on the intermediate layer 300 by a deposition process and covers the intermediate layer 300. Of course, the silicon-containing anti-reflective layer 400 may also be formed on the intermediate layer 300 by a spin-coating process. The material of the intermediate layer 300 may be amorphous carbon (Amorphous Carbon Layer, ACL for short). The silicon-containing anti-reflection layer 400 has higher hardness, is not easy to collapse and deform when the first groove 410 or other structures of the silicon-containing anti-reflection layer 400 are etched, and the pattern precision formed after etching is also better.

As shown in fig. 12, the first trenches 410 are formed in the silicon-containing anti-reflective layer 400 in a plurality, and the plurality of first trenches 410 are spaced apart and extend in the second direction. The first trench 410 may or may not extend through the silicon-containing anti-reflective layer 400. As shown in fig. 12, the bottom of the first trench 410 is located in the silicon-containing anti-reflective layer 400, that is, the first trench 410 is formed on the upper portion of the silicon-containing anti-reflective layer 400 away from the substrate 100, and then a first etching trench is formed in the lower portion of the silicon-containing anti-reflective layer 400 by using the first trench 410, wherein the width of the first etching trench is smaller than the width of the first trench 410, and the density of the first etching trench is greater than the density of the first trench 410, so that the feature size of the semiconductor structure is further reduced, and the integration level of the semiconductor structure is improved.

Step S1022: and forming a second sacrificial layer on the side wall of the first groove, and enclosing the second sacrificial layer in the first groove into a third groove.

Specifically, referring to fig. 12 and 13, a second sacrificial layer 420 is deposited on the sidewalls and bottom of the first trench 410 and the silicon-containing anti-reflective layer 400, and the second sacrificial layer 420 covers the surface of the silicon-containing anti-reflective layer 400 on the side facing away from the substrate 100, i.e., the second sacrificial layer 420 is an integral layer, so as to facilitate the formation of the second sacrificial layer 420. The material of the second sacrificial layer 420 may be silicon oxide.

Step S1023: and forming a first filling layer in the third groove.

With continued reference to fig. 12 and 13, a first filling layer 430 is deposited in the third trench, and the material of the first filling layer 430 may be a spin-on hard mask. In some possible examples, as shown in fig. 13, a first fill layer 430 is deposited within the third trench, and over the second sacrificial layer 420. The first filling layer 430 fills in the third trench and covers the second sacrificial layer 420.

Referring to fig. 14, a portion of the first filling layer 430 and a portion of the second sacrificial layer 420 are removed again to expose the second sacrificial layer 420 on the sidewalls of the first trench 410. Specifically, the second sacrificial layer 420 and the first filling layer 430 on the surface of the silicon-containing anti-reflective layer 400 facing away from the substrate 100 are removed to expose the surface of the silicon-containing anti-reflective layer 400 and the second sacrificial layer 420 on the sidewalls of the first trench 410. For example, a portion of the first filling layer 430 and a portion of the second sacrificial layer 420 are removed by an etching process or a planarization process.

Step S1024: and removing the second sacrificial layer on the side wall of the first groove to form a first etching groove.

Referring to fig. 15, the second sacrificial layer 420 is etched to form a first etch groove 440. It will be appreciated that during the etching of the second sacrificial layer 420, portions of the silicon-containing anti-reflective layer 400 and the first fill layer 430 are also etched away. The bottom of the first etch groove 440 exposes the silicon-containing anti-reflective layer 400.

With continued reference to fig. 15, the silicon-containing anti-reflective layer 400 and the first filling layer 430 have different selection ratios, and after etching, the silicon-containing anti-reflective layer 400 and the first filling layer 430 have a certain height difference therebetween. Illustratively, the etch rate of the silicon-containing anti-reflective layer 400 is slower than the etch rate of the first fill layer 430, and when the second sacrificial layer 420 is etched away, the silicon-containing anti-reflective layer 400 is etched to a lesser height in the height direction, i.e., in a direction perpendicular to the substrate 10, and the first fill layer 430 is etched to a greater height. As shown in fig. 15, the remaining silicon-containing antireflective layer 400 faces away from the surface of the substrate 110, and is higher than the remaining first fill layer 430 faces away from the surface of the substrate 110.

Step S1025: etching to the spin-coating hard mask layer along the first etching groove to form a first channel.

Referring to fig. 16 and 17, the silicon-containing anti-reflective layer 400, the intermediate layer 300, and the spin-on hard mask layer 200 are etched along the first etch groove 440, forming a first channel 210 in the spin-on hard mask layer 200. In the embodiment of the present application, the silicon-containing anti-reflection layer 400 is used as the transfer layer of the etched pattern to reduce the size of the first etching groove 440, and an extreme ultraviolet (Extreme Ultra Violet, abbreviated as EUV) lithography process is not used in the process, so that the production cost is reduced.

In some possible embodiments, referring to fig. 3, 4, and 18 to 20, forming a stacked arrangement of an intermediate layer and a silicon-containing anti-reflective layer on the spin-on hard mask layer, the silicon-containing anti-reflective layer having a plurality of first trenches disposed at intervals and extending in a second direction comprises:

step a: and forming a first mask layer, a second mask layer and a photoresist layer which are sequentially stacked on the silicon-containing anti-reflection layer.

Referring to fig. 3 and 4, a first mask layer 500 is deposited on the silicon-containing anti-reflection layer 400, the first mask layer 500 covers the silicon-containing anti-reflection layer 400, a second mask layer 600 is deposited on the first mask layer 500, the second mask layer 600 covers the first mask layer 500, and a photoresist layer 700 is formed on the first mask layer 500 by Spin Coating, spray Coating, brush Coating, or the like.

As illustrated in fig. 3 and 4, the first mask layer 500 includes a first base layer 510 disposed on the silicon-containing anti-reflective layer 400, and a first anti-reflective layer 520 disposed on the first base layer 510; the second mask layer 600 includes a second base layer 610 disposed on the first anti-reflection layer 520, and a second anti-reflection layer 620 disposed on the second base layer 610. Namely, the silicon-containing anti-reflection layer 400, the first base layer 510, the first anti-reflection layer 520, the second base layer 610, the second anti-reflection layer 620, and the photoresist layer 700 are sequentially stacked in a direction away from the substrate 100.

With continued reference to fig. 3 and 4, the photoresist layer 700 is a patterned Photoresist (PR) layer, that is, the photoresist layer 700 is formed with a predetermined pattern through exposure, development, and other processes. The photoresist layer 700 is exposed with a portion of the second anti-reflection layer 620. The second anti-reflection layer 620 may absorb light used for exposing the photoresist layer 700, thereby reducing or preventing light from being reflected at the second anti-reflection layer 620 to improve the accuracy of the predetermined pattern of the photoresist layer 700. The material of the first base layer 510 is the same as that of the second base layer 610, and the material of the first anti-reflection layer 520 and the material of the second anti-reflection layer 620 are the same, so as to reduce the variety of materials used in the manufacturing process of the semiconductor structure. Illustratively, the first base layer 510 and the second base layer 610 may be made of a spin-on hard mask composition, and the first anti-reflective layer 520 and the second anti-reflective layer 620 may be made of silicon oxynitride.

Step b: and etching the second mask layer by taking the photoresist layer as a mask, wherein a plurality of first intermediate grooves which are arranged at intervals and extend along the second direction are formed in the second mask layer.

Referring to fig. 4 and 18, the second mask layer 600 is etched using the photoresist layer 700 as a mask, and portions of the second mask layer 600 not covered by the photoresist layer 700 are removed, and portions of the second mask layer 600 covered by the photoresist layer 700 remain. A plurality of first intermediate grooves 630 are formed in the second mask layer 600, the first intermediate grooves 630 being disposed at intervals and extending in the second direction, the first intermediate grooves 630 penetrating the second mask layer 600 to expose the first mask layer 500. So configured, the predetermined pattern in the photoresist layer 700 is transferred to the second mask layer 600, and the first intermediate groove 630 is formed in the second mask layer 600.

Step c: and depositing a third sacrificial layer on the side wall and the bottom of the first intermediate groove and the second mask layer, wherein the third sacrificial layer positioned in the first intermediate groove is enclosed to form a second intermediate groove.

Referring to fig. 18 and 19, a third sacrificial layer 640 is deposited on the sidewalls and the bottom of the first intermediate trench 630, and the second mask layer 600, for example, by an atomic layer deposition process to form the third sacrificial layer 640 with good quality. The third sacrificial layer 640 may be made of silicon oxide.

Step d: and removing the third sacrificial layer positioned at the top of the second mask layer and the bottom of the second middle groove, and reserving the third sacrificial layer positioned on the side wall of the first middle groove.

Referring to fig. 20, the third sacrificial layer 640 at the top of the second mask layer 600 and the bottom of the second intermediate trench 650 is removed by an etching process, leaving the third sacrificial layer 640 at the sidewalls of the first intermediate trench 630. After etching, the second mask layer 600 and the first mask layer 500 are exposed. I.e., by deposition and etching back, a third sacrificial layer 640 is formed at the sidewalls of the first intermediate trench 630.

Step e: and etching the second mask layer, the first mask layer and the silicon-containing anti-reflection layer by taking the reserved third sacrificial layer as a mask so as to form a first groove.

Referring to fig. 20 and 12, the second mask layer 600, the first mask layer 500, and the silicon-containing anti-reflection layer 400 between the third sacrificial layers 640 are etched away, forming the first trenches 410 in the silicon-containing anti-reflection layer 400. After the first trench 410 is formed, other film layers on the silicon-containing anti-reflective layer 400 are removed to expose the silicon-containing anti-reflective layer 400.

It should be noted that, forming the interlayer and the silicon-containing anti-reflection layer stacked on the spin-on hard mask layer, the silicon-containing anti-reflection layer having a plurality of first trenches disposed at intervals and extending in the second direction may also be formed by other means, and in other possible examples, it includes the following steps:

Step a': and forming a first mask layer, a second mask layer and a photoresist layer which are sequentially stacked on the silicon-containing anti-reflection layer.

Step b': and etching the second mask layer by taking the photoresist layer as a mask, wherein a plurality of first intermediate grooves which are arranged at intervals and extend along the second direction are formed in the second mask layer.

Step c': and depositing a third sacrificial layer on the side wall and the bottom of the first intermediate groove and the second mask layer, wherein the third sacrificial layer positioned in the first intermediate groove is enclosed to form a second intermediate groove.

The steps a ', b ', and c ' in this example may refer to the steps a, b, and c in the above examples, respectively, and are not described herein.

Step d': a second filling layer is formed on the second intermediate trench and the third sacrificial layer.

And forming a second filling layer through a deposition process, wherein the second filling layer fills the second intermediate groove and covers the third sacrificial layer. The material of the third filling layer can be spin-coating hard mask composition.

Step e': and removing part of the second filling layer and part of the third sacrificial layer to expose the third sacrificial layer on the side wall of the first intermediate layer.

Illustratively, a portion of the second fill layer and a portion of the third sacrificial layer on a surface of the second mask layer facing away from the substrate are removed by a planarization process to expose the surface and the third sacrificial layer on a sidewall of the first intermediate layer.

Step f': and etching the third sacrificial layer, the first mask layer and the silicon-containing anti-reflection layer to form a first groove.

And etching the third sacrificial layer, and forming a first groove in the silicon-containing anti-reflection layer and the first mask layer positioned below the third sacrificial layer. The film layer over the silicon-containing anti-reflective layer is also removed at least in part during etching. The remaining film layer can be removed separately by an etching process, and after the remaining film layer is removed, the silicon-containing anti-reflection layer is exposed.

It should be noted that, in different examples where the intermediate layer and the silicon-containing anti-reflection layer are formed on the spin-on hard mask layer, and the silicon-containing anti-reflection layer has a plurality of first trenches disposed at intervals and extending along the second direction, the patterns of the photoresist layers are different to ensure that the positions of the finally formed first trenches are the same.

In this embodiment, the first trench 410 is formed in the silicon-containing anti-reflective layer 400 by a Self-aligned double patterning (SADP) process, so that the feature size of the first trench 410 is reduced and the density is increased. In addition, during the subsequent formation of the first etching trench 440 in the silicon-containing anti-reflective layer 400, the self-aligned double patterning process is performed again, so that the feature size of the first etching trench 440 is further reduced, and the density is further increased, thereby further improving the integration level of the subsequently formed semiconductor structure.

In one possible example of the present application, referring to fig. 12 to 14, a second sacrificial layer is deposited on the sidewall and the bottom of the first trench and the silicon-containing anti-reflection layer, and correspondingly, the step of forming the first filling layer in the third trench includes:

referring to fig. 13, a first fill layer 430 is deposited within the third trench and over the second sacrificial layer 420. As shown in fig. 13, the first filling layer 430 fills the third trench and covers the second sacrificial layer 420, i.e., the surface of the first filling layer 430 facing away from the substrate 100 is higher than the surface of the second sacrificial layer 420 facing away from the substrate 100.

Referring to fig. 14, a portion of the first filling layer 430 and a portion of the second sacrificial layer 420 are removed to expose the second sacrificial layer 420 on the sidewalls of the first trench 410. As shown in fig. 14, a part of the first filling layer 430 and a part of the second sacrificial layer 420 are removed by a planarization process, and the silicon-containing anti-reflection layer 400 and the second sacrificial layer 420 are exposed.

In this embodiment, after forming the first channel, the step of forming the first sacrificial layer in the first channel includes: a first sacrificial layer 220 is deposited within the first etch trench and within the first channel 210. Referring to fig. 21, the first sacrificial layer 220 fills in the first trenches 210 and the first etched trenches, and may also cover the intermediate layer 300 or the silicon-containing anti-reflective layer 400. It is appreciated that during the etching of the spin-on hard mask layer 200 to form the first trenches 210, portions of the silicon-containing anti-reflective layer 400 are also etched away. When the silicon-containing anti-reflection layer 400 is not completely removed, the first sacrificial layer 220 covers the silicon-containing anti-reflection layer 400, and when the silicon-containing anti-reflection layer 400 is completely removed, the intermediate layer 300 is exposed, and the first sacrificial layer 220 covers the intermediate layer 300.

After the step of forming the first sacrificial layer in the first channel, the method further includes: the intermediate layer, the first sacrificial layer, and the silicon-containing anti-reflective layer located over the spin-on hard mask layer are removed to expose the spin-on hard mask layer. Referring to fig. 22, other film layers located above the spin-on hard mask layer 200 are removed by a planarization process to expose the spin-on hard mask layer 200, facilitating subsequent removal of the spin-on hard mask layer 200.

In some possible examples of the present application, the step of removing the first sacrificial layer to expose the first trench, and extending the filling hole of the first trench to the active region further includes: conductive posts are formed in the filled holes and electrically connected to the active region.

Referring to fig. 10, 23 to 25, the conductive pillars 250 are in contact with the active region 111 to electrically connect the conductive pillars 250 with the active region 111. One conductive post 250 is disposed in each of the fill holes 212, and the conductive posts 250 are not connected to each other. An active region 111 and a word line 113 are provided in the substrate 110, and the word line 113 is provided to be insulated from the active region 111 and offset from the conductive pillar 250. Illustratively, the word line 113 passes through a middle region of the active region 111, and the conductive pillar 250 is electrically connected with an end region of the active region 111.

Specifically, referring to fig. 11, 23, and 24, forming the conductive pillars 250 in the filling holes 212, the conductive pillars 250 electrically connected to the active region 111 may include:

a first conductive layer 251 is deposited within the first channel 210 and on the first support layer 240, the first conductive layer 251 filling within the first channel 210 and covering the first support layer 240, the first conductive layer 251 being electrically connected to the active region 111. As shown in fig. 11 and 23, the first conductive layer 251 fills in the first channel 210 and covers the first support layer 240. The material of the first conductive layer 251 may be polysilicon.

After the first conductive layer 251 is formed, the first conductive layer 251 is etched, a portion of the first conductive layer 251 located within the filling hole 212 remains, and the remaining first conductive layer 251 forms a plurality of conductive pillars 250. As shown in fig. 11 and 24, the first conductive layer 251 located at the upper portion of the bit line is removed, and the first conductive layer 251 located at the upper portion of the filling hole 212 remains the first conductive layer 251 located at the bottom of the filling hole 212. The remaining first conductive layer 251 is separated into a plurality of conductive layers by the first support layer 240 and the bit line, and the conductive pillars 250 are spaced apart from each other and are not connected to each other. Specifically, as shown in fig. 24, at least the first conductive layer 251 located over the second support layer 152 of the bit line is removed to isolate the first conductive layer 251 into a plurality of conductive layers.

It should be noted that, after the step of forming the conductive pillars 250 in the filling holes 212 and electrically connecting the conductive pillars 250 to the active regions 111, the method further includes: a protective layer 260 is deposited over the conductive pillars 250, the protective layer 260 covering the conductive pillars 250. Referring to fig. 25, a protective layer 260 is deposited on the conductive pillars 250, the protective layer 260 covering the surface of the conductive pillars 250 remote from the substrate 100. The material of the protection layer 260 may be nitride, such as silicon nitride. The thickness of the protective layer 260 is thinner, for example, the protective layer 260 may reduce or prevent the conductive pillars 250 from being oxidized due to exposure to air.

The embodiment of the present application further provides a semiconductor structure obtained by the method for manufacturing a semiconductor structure, so that the semiconductor structure has at least the advantage of less loss of the bit line 150, and specific effects are described above and will not be repeated herein.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, reference is made to "one embodiment," "some embodiments," "an exemplary embodiment," "an example," "a particular instance," or "some examples," etc., meaning that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a spin-on hard mask layer on a substrate, wherein a plurality of active areas which are arranged at intervals are arranged in the substrate, a plurality of bit lines which are arranged at intervals and extend along a first direction are arranged on the substrate, each bit line is at least electrically connected with one active area, and the spin-on hard mask layer is filled between the bit lines and covers the bit lines;

removing part of the spin-on hard mask layer to form a plurality of first channels which are arranged at intervals and extend along the second direction;

forming a first sacrificial layer in the first channel, wherein the first sacrificial layer is filled in the first channel;

Removing the spin-on hard mask layer between the first sacrificial layers to form a second channel;

forming a first supporting layer in the second channel, wherein the first supporting layer is filled in the second channel;

the first sacrificial layer is removed and the first channel between adjacent bit lines is extended to the active region.

2. The method of claim 1, wherein removing a portion of the spin-on hard mask layer to form a plurality of spaced apart first trenches, the first trenches exposing the substrate comprises:

forming an intermediate layer and a silicon-containing anti-reflection layer which are sequentially stacked on the spin-on hard mask layer, wherein the silicon-containing anti-reflection layer is provided with a plurality of first grooves which are arranged at intervals and extend along a second direction;

forming a second sacrificial layer on the side wall of the first groove, and enclosing the second sacrificial layer in the first groove into a third groove;

forming a first filling layer in the third groove;

removing the second sacrificial layer on the side wall of the first groove to form a first etching groove;

etching to the spin-on hard mask layer along the first etching groove to form the first channel.

3. The method of claim 2, wherein a bottom of the first trench is located in the silicon-containing anti-reflective layer.

4. The method of fabricating a semiconductor structure of claim 2, wherein forming a stacked arrangement of an intermediate layer and a silicon-containing anti-reflective layer on the spin-on hard mask layer, the silicon-containing anti-reflective layer having a plurality of first trenches disposed at intervals and extending in a second direction comprises:

forming a first mask layer, a second mask layer and a photoresist layer which are sequentially stacked on the silicon-containing anti-reflection layer;

etching the second mask layer by taking the photoresist layer as a mask, wherein a plurality of first intermediate grooves which are arranged at intervals and extend along a second direction are formed in the second mask layer;

depositing a third sacrificial layer on the side wall and the bottom of the first intermediate groove and the second mask layer, wherein the third sacrificial layer in the first intermediate groove is enclosed to form a second intermediate groove;

removing the third sacrificial layer positioned at the top of the second mask layer and the bottom of the second middle groove, and reserving the third sacrificial layer positioned on the side wall of the first middle groove;

And etching the second mask layer, the first mask layer and the silicon-containing anti-reflection layer by taking the reserved third sacrificial layer as a mask so as to form the first groove.

5. The method of claim 4, wherein the first mask layer comprises a first base layer disposed on the silicon-containing anti-reflective layer, and a first anti-reflective layer disposed on the first base layer;

the second mask layer comprises a second base layer arranged on the first anti-reflection layer and a second anti-reflection layer arranged on the second base layer;

the material of the first base layer is the same as that of the second base layer, and the material of the first anti-reflection layer is the same as that of the second anti-reflection layer.

6. The method of claim 2, wherein forming a second sacrificial layer on a sidewall of the first trench, the second sacrificial layer within the first trench surrounding a third trench comprises:

and depositing a second sacrificial layer on the side wall and the bottom of the first groove and the silicon-containing anti-reflection layer.

7. The method of fabricating a semiconductor structure of claim 6, wherein forming a first fill layer within the third trench comprises:

Depositing the first filling layer in the third groove and on the second sacrificial layer;

and removing part of the first filling layer and part of the second sacrificial layer to expose the second sacrificial layer on the side wall of the first groove.

8. The method of fabricating a semiconductor structure of claim 7, wherein the step of forming a first sacrificial layer within the first trench comprises:

the first sacrificial layer is deposited within the first etch trench and within the first trench.

9. The method of fabricating a semiconductor structure of claim 8, further comprising, after the step of forming a first sacrificial layer within the first trench:

the intermediate layer, the first sacrificial layer, and the silicon-containing antireflective layer over the spin-on hard mask layer are removed to expose the spin-on hard mask layer.

10. The method of fabricating a semiconductor structure according to any one of claims 1-9, wherein removing the first sacrificial layer exposes the first trench, and wherein after the step of extending the filling hole of the first trench to the active region, further comprises:

and forming a conductive column in the filling hole, wherein the conductive column is electrically connected with the active region.

11. The method of any of claims 1-9, wherein the base comprises a substrate, an insulating layer disposed on the substrate, and a barrier layer disposed on the insulating layer, the active region disposed within the substrate, the insulating layer covering the active region;

the step of removing the first sacrificial layer and extending the first channel between adjacent bit lines to the active region includes:

etching the first sacrificial layer to expose the first trenches, each of the first trenches including a second trench located above the bit line and extending in a second direction, and a filling hole located between adjacent bit lines and communicating with the second trench;

and etching the insulating layer along the filling holes of the first channels so that the filling holes expose the active areas.

12. The method of claim 11, wherein forming a conductive pillar in the filled hole, the conductive pillar electrically connecting the active region comprises:

depositing a first conductive layer in the first channel and on the first supporting layer, wherein the first conductive layer is filled in the first channel and covers the first supporting layer, and the first conductive layer is electrically connected with the active region;

And etching the first conductive layer, reserving part of the first conductive layer positioned in the filling hole, and forming a plurality of conductive columns by the reserved first conductive layer.

13. The method of claim 12, wherein a plurality of word lines are disposed in the substrate at intervals and extend in the second direction, and the word lines are disposed in an insulating manner from the active region and are offset from the conductive pillars.

14. The method of fabricating a semiconductor structure according to any one of claims 1-9, wherein forming a conductive pillar in the filled hole, the conductive pillar electrically connecting the active region, further comprises:

and depositing a protective layer on the conductive column, wherein the protective layer covers the conductive column.

15. The method for fabricating a semiconductor structure according to any one of claims 1 to 9, wherein the bit line includes a second conductive layer, and a second support layer covering the second conductive layer, and an oxide layer located beside the second conductive layer is further disposed in the second support layer, and the second support layer and the first support layer are made of the same material;

the selection ratio of the spin-on hard mask layer to the second support layer is greater than or equal to 5.

16. A semiconductor structure, characterized in that it is obtained by a method of manufacturing a semiconductor structure according to any of claims 1-15.