CN110867409B - Method for manufacturing contact hole - Google Patents
Method for manufacturing contact hole Download PDFInfo
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- CN110867409B CN110867409B CN201911162973.4A CN201911162973A CN110867409B CN 110867409 B CN110867409 B CN 110867409B CN 201911162973 A CN201911162973 A CN 201911162973A CN 110867409 B CN110867409 B CN 110867409B
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- line width
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
The invention discloses a method for manufacturing a contact hole, which comprises the following steps: step one, forming an interlayer film. And step two, measuring the thickness of the interlayer film of each area. And step three, adjusting the photoetching defined line width of the contact hole in the corresponding area according to the thickness value of the interlayer film so as to compensate the influence of the thickness of the interlayer film on the opening line width of the etched contact hole. And step four, carrying out a photoetching process. And step five, carrying out an etching process to form an opening of the contact hole. The invention can eliminate the influence of the thickness of the interlayer film on the line width of the contact hole, can enable the opening line width of the contact hole after etching in each area to meet the required value, is beneficial to the isometric reduction of the device size and can improve the electrical performance and yield of the reduced semiconductor device.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a contact hole.
Background
Conductive regions such as source, drain or gate regions in a semiconductor device need to be connected to a drain electrode composed of a front metal layer through a contact hole. The conventional contact hole manufacturing method generally includes the steps of: defining a forming area of the contact hole by photoetching, and etching the interlayer film according to the photoetching definition to form an opening of the contact hole; and filling metal in the opening to form a contact hole. Typically, After the development of the photolithography process is completed, an After-development Inspection (ADI) is required, and After the etching is completed, an After-etching Inspection (AEI) is required.
With the continuous development of semiconductor manufacturing technology, the process node of a semiconductor device is continuously reduced, the line width (CD) of a contact hole is also continuously reduced, and at this time, the deviation of the line width of the etched contact hole can generate a large influence on the electrical performance of the semiconductor device and influence the yield of products. In the existing contact hole manufacturing method, the photoetching defined line width and the etching process of the contact hole are fixed, and the line width measured by ADI is the opening line width of the contact hole after development, so the line width measured by ADI is not changed generally. However, since the semiconductor device structure is formed on the surface of the wafer composed of the semiconductor substrate and the influence of the forming process of the interlayer film itself causes the thickness deviation of the interlayer film in each region of the wafer, the influence on the line width of the contact hole caused by the thickness deviation of the interlayer film becomes non-negligible and more serious as the line width of the contact hole decreases. The process nodes of semiconductor devices are decreasing, the gate dielectric layer of the gate structure usually employs a high dielectric constant (HK) layer, the layer group of gate conductive materials employs a Metal Gate (MG), the gate structure including the high dielectric constant layer and the metal layer is called HKMG, and the HKMG process of the 28nm process node is usually called 28HKMG process. In the 28HKMG process, the line width of the etched contact hole is likely to be shifted.
Disclosure of Invention
The invention aims to provide a method for manufacturing a contact hole, which can eliminate the influence of the thickness of an interlayer film on the line width of the contact hole, thereby being beneficial to the reduction of the size of a device.
In order to solve the above technical problem, the method for manufacturing the contact hole provided by the invention comprises the following steps:
step one, an interlayer film (ILD) is formed on a first wafer having a semiconductor substrate.
And step two, measuring the thickness of the interlayer film in each area of the first wafer.
And step three, adjusting the photoetching defined line width of the contact hole in the corresponding area according to the thickness value of the interlayer film in each area of the first wafer so as to compensate the influence of the thickness of the interlayer film on the opening line width of the contact hole after subsequent etching and ensure that the opening line width of the contact hole in the corresponding area after etching meets the required value.
Fourthly, defining an opening area of the contact hole in each area of the first wafer by a photoetching process; and the opening size of the contact hole in each area is defined by the corresponding adjusted photoetching definition line width.
And fifthly, removing the interlayer film in the opening area of the contact hole by an etching process to form an opening of the contact hole.
In a further improvement, the semiconductor substrate is a silicon substrate.
Semiconductor devices are formed on the semiconductor substrate, each of the semiconductor devices including a gate structure.
Each of the semiconductor devices further includes a source region and a drain region.
In a further improvement, the gate structure comprises a gate dielectric layer and a polysilicon (Poly) gate which are sequentially stacked.
The further improvement is that the grid structure comprises a grid dielectric layer and a metal grid which are sequentially superposed.
In a further improvement, the process node of the semiconductor device is below 28 nm.
In a further improvement, the gate dielectric layer comprises a high dielectric constant layer, and the metal gate comprises a work function layer.
In a further improvement, the interlayer film covers the top surface, the side surfaces and the surface of the semiconductor substrate outside the gate structure.
In a further improvement, a Contact Etching Stop Layer (CESL) is further formed at the bottom of the interlayer film, the contact etching stop layer covers the top surface and the side surface of the gate structure and the surface of the semiconductor substrate outside the gate structure, and the interlayer film is formed on the surface of the contact etching stop layer.
The further improvement is that in the fourth step, the photoetching process comprises the following sub-steps:
and sequentially forming an amorphous carbon material (APF) layer, a medium anti-reflection layer (DARC) layer, a bottom anti-reflection layer (BARC) layer and Photoresist (PR) on the surface of the interlayer film.
And carrying out exposure development on the photoresist.
The further improvement is that after the step four is completed, the method further comprises an ADI detection step, wherein the ADI detection step measures the opening line width of the contact hole after the development, and the opening line width of the contact hole after the development is determined by the adjusted photoetching defined line width.
The further improvement is that after the fifth step is finished, AEI detection is carried out, the AEI detection is used for measuring the opening line width of the etched contact hole, the opening line width of the etched contact hole is in direct proportion to the size of the opening line width of the developed contact hole, the opening line width of the etched contact hole is related to the thickness of the interlayer film, and the influence of the thickness of the interlayer film on the opening line width of the etched contact hole is compensated through the adjusted photoetching defined line width, so that the opening line width of the etched contact hole in each area with different thicknesses meets the requirement value.
The further improvement is that the third step comprises the following sub-steps:
step 31, the step before adjusting the photoetching defined line width of the contact hole, includes: under the condition that the photoetching definition line width of the contact hole is kept to be an unadjusted design value, determining a first proportional coefficient between a first change value of the thickness of the interlayer film and a second change value of the opening line width of the etched contact hole, wherein the first change value is the deviation between the actual thickness value and the design value of the interlayer film, and the second change value is the corresponding deviation of the opening line width of the etched contact hole when the thickness of the interlayer film is at the actual value and the design value.
And step 32, calculating a first variation value of the interlayer film in each region according to the measured thickness value of the interlayer film, and calculating a second variation value corresponding to the photoetching-defined line width of the contact hole with an unadjusted design value according to the first scale coefficient.
And step 33, adjusting the photoetching defined line width of the contact hole in the corresponding area according to the second change value by utilizing the proportional relation between the opening line width of the etched contact hole and the opening line width of the developed contact hole, so that the corresponding second change value tends to 0nm when the photoetching defined line width of the contact hole adopts the adjustment value.
In a further improvement, step 31 is performed before step one, and comprises the following steps:
and providing a second wafer which finishes the opening etching process of the contact hole, wherein the photoetching defined line width of the contact hole of the second wafer adopts an unadjusted design value, and the opening etching process parameters of the contact hole of the second wafer are the same as those of the contact hole of the first wafer.
The thickness of the interlayer film was measured for each region on the second wafer.
And measuring the opening line width of the contact hole after the development and the opening line width of the contact hole after the etching of each area on the second wafer.
And calculating the first proportional coefficient according to the thickness of the interlayer film in each area and the opening line width of the etched contact hole.
And determining the proportional relation between the opening line width of the contact hole after the development and the opening line width of the contact hole after the etching.
A further improvement is that when the thickness of the interlayer film is increased, the opening line width of the etched contact hole is reduced, and the photolithography definition line width of the contact hole needs to be increased in step 33.
When the thickness of the interlayer film is reduced, the opening line width of the etched contact hole is increased, and the photolithography definition line width of the contact hole needs to be reduced in step 33.
In a further improvement, the first scaling factor is greater than 0 and equal to or less than 0.7.
According to the invention, before the photoetching process of the contact hole is carried out, the thickness distribution of the interlayer film is measured in advance, and then the photoetching defined line width of the contact hole is adjusted according to the thickness distribution of the interlayer film, namely, the photoetching defined line width of the contact hole is fixed and unchanged compared with the photoetching defined line width of the contact hole in the prior art, the photoetching defined line width of the contact hole can change along with the thickness change of the interlayer film, so that the influence of the thickness change of the interlayer film on the opening line width of the etched contact hole can be counteracted, the opening line width of the contact hole in a corresponding area after etching can be ensured to meet a required value, the size of a device can be reduced in an equal proportion, and the electrical property and yield of the reduced semiconductor device can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of a method for fabricating a contact hole according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a contact hole in the method for forming a contact hole according to the embodiment of the present invention.
Detailed Description
FIG. 1 is a flow chart of a method for fabricating a contact hole according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of a contact hole in the method for manufacturing a contact hole according to the embodiment of the present invention; the manufacturing method of the contact hole comprises the following steps:
step one, an interlayer film 5 is formed on a first wafer having a semiconductor substrate 1.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate.
Semiconductor devices are formed on the semiconductor substrate 1, each of which includes a gate structure.
Each of the semiconductor devices further includes a source region and a drain region.
The grid structure comprises a grid dielectric layer and a polysilicon grid 2 which are sequentially overlapped. In fig. 2, the polysilicon gate 2 is also denoted by Poly. A top mask layer 3 is also formed on top of the polysilicon gate 2. And side walls are also formed on the side surfaces of the polysilicon gate 2. In other embodiments can also be: the grid structure comprises a grid dielectric layer and a metal grid which are sequentially overlapped. The gate dielectric layer comprises a high dielectric constant layer, the metal gate comprises a work function layer, the gate structure is HKMG, and the gate structure of the semiconductor device below a 28nm process node is usually HKMG.
The interlayer film 5 covers the top surface and the side surface of the gate structure and the surface of the semiconductor substrate 1 outside the gate structure. Preferably, a contact etch stop layer 4 is also formed at the bottom of the interlayer film 5, and in fig. 2, the contact etch stop layer 4 is also denoted by CESL. The contact etching stop layer 4 covers the top surface and the side surface of the gate structure and the surface of the semiconductor substrate 1 outside the gate structure, and the interlayer film 5 is formed on the surface of the contact etching stop layer 4. In fig. 2, d3 represents the sum of the thicknesses of the sidewall of the side of the polysilicon gate 2 and the contact etch stop layer 4, and d3 is listed as 15nm in fig. 2.
Step two, measuring the thickness of the interlayer film 5 of each area of the first wafer.
And step three, adjusting the photoetching defined line width of the contact hole in the corresponding area according to the thickness value of the interlayer film 5 in each area of the first wafer so as to compensate the influence of the thickness of the interlayer film 5 on the opening line width of the contact hole after subsequent etching and ensure that the opening line width of the contact hole in the corresponding area after etching meets the required value.
Fourthly, defining an opening area of the contact hole in each area of the first wafer by a photoetching process; and the opening size of the contact hole in each area is defined by the corresponding adjusted photoetching definition line width.
In the fourth step, the photoetching process comprises the following sub-steps:
in fig. 2, the APF layer 6 is further marked by APF, the DARC layer 7 is further marked by DARC, the BARC layer 8 is further marked by BARC, and the photoresist 9 is further marked by PR.
And exposing and developing the photoresist 9.
And after the step four is finished, carrying out ADI detection, wherein the ADI detection measures the opening line width of the contact hole after development, and the opening line width of the contact hole after development is determined by the adjusted photoetching defined line width.
Taking fig. 2 as an example, in fig. 2, the surface corresponding to the mark 101 is a surface corresponding to the thickness of the interlayer film 5 as a design value. After the photolithography process is completed, the photoresist 9 and the BARC layer 8 are opened, d1 is the width of the opened region of the photoresist 9, and d1 is determined by the corresponding photolithography-defined line width. D1 in fig. 2 can be detected by ADI. Fig. 2 lists d1 as 0.065 micrometers (um).
In fig. 2, the surface corresponding to the broken line 102 is a surface when the thickness of the interlayer film 5 is larger than a design value. The surface corresponding to the broken line 103 is a surface when the thickness of the interlayer film 5 is smaller than a design value.
And fifthly, removing the interlayer film 5 in the opening area of the contact hole by an etching process to form an opening of the contact hole.
And after the fifth step is finished, AEI detection is further carried out, the AEI detection is used for measuring the opening line width of the etched contact hole, the opening line width of the etched contact hole is in direct proportion to the size of the opening line width of the developed contact hole, the opening line width of the etched contact hole is related to the thickness of the interlayer film 5, the influence of the thickness of the interlayer film 5 on the opening line width of the etched contact hole is compensated through the adjusted photoetching defined line width, and the opening line width of the etched contact hole in each area with different thicknesses meets the requirement value.
Taking fig. 2 as an example, in fig. 2, when the thickness of the interlayer film 5 is a design value, the side surface of the opening of the contact hole after the etching is completed is shown as reference 10, the opening line width of the corresponding etched contact hole is d2, and fig. 2 shows that d2 is 0.040 um.
In the embodiment of the present invention, the opening line widths of the contact holes formed after the contact hole etching is performed on the interlayer film 5 having the surfaces corresponding to the dotted lines 102 and 103 as the top surfaces are both approximately equal to d2 in fig. 2. This is because in the embodiment of the present invention, the lithographically defined line width of the contact hole corresponding to the interlayer film 5 after the modification is changed, that is, the corresponding d1 in fig. 2 is changed, and finally, d2 is kept unchanged.
Fig. 2 also shows a schematic structure of a change in d2 when the lithographically-defined line width of the contact hole is unchanged, i.e., d1 is unchanged, in the conventional method, which is described as follows: in fig. 2, a dotted line 10a indicates a side surface of the opening of the contact hole etched by the thicker interlayer film 2 corresponding to the dotted line 102 when the lithographically-defined line width of the contact hole is not adjusted, that is, d1 is fixed, and it can be seen that d2 is reduced. And the dotted line 10b represents the side of the opening of the contact hole etched when the lithographically-defined line width of the contact hole is not adjusted, i.e., d1 is fixed, for the thinner interlayer film 2 corresponding to the dotted line 103, and it can be seen that d2 is increased.
In the embodiment of the invention, the third step comprises the following sub-steps:
step 31, the step before adjusting the photoetching defined line width of the contact hole, includes: under the condition that the photoetching definition line width of the contact hole is kept to be an unadjusted design value, determining a first proportional coefficient between a first variation value of the thickness of the interlayer film 5 and a second variation value of the opening line width of the etched contact hole, wherein the first variation value is the deviation between the actual thickness value and the design value of the interlayer film 5, and the second variation value is the corresponding deviation of the opening line width of the etched contact hole when the actual value and the design value of the thickness of the interlayer film 5 are reached.
May be represented by a company as: Δ d2 ═ K1 × Δ L, Δ L denotes the first change value, Δ d2 denotes the second change value, and K1 denotes the first scaling factor.
Step 32, calculating a first variation value of the interlayer film 5 in each region according to the measured thickness value of the interlayer film 5, and calculating a second variation value corresponding to the lithography-defined line width of the contact hole using an unadjusted design value according to the first scale factor.
And step 33, adjusting the photoetching defined line width of the contact hole in the corresponding area according to the second change value by utilizing the proportional relation between the opening line width of the etched contact hole and the opening line width of the developed contact hole, so that the corresponding second change value tends to 0nm when the photoetching defined line width of the contact hole adopts the adjustment value.
Wherein the relationship that the opening line width of the etched contact hole and the opening line width of the developed contact hole are in direct proportion is also as follows: after the opening line width of the contact hole after development is increased, the opening line width of the contact hole after etching is reduced, and vice versa, namely d2 is also increased after d1 is increased; as d1 decreases, d2 also decreases.
When the thickness of the interlayer film 5 is reduced, the opening line width of the etched contact hole is increased, that is, the photolithography-defined line width of the contact hole needs to be reduced in step 33. Namely: if Δ d2 is positive, it indicates that d2 is large, and d2 needs to be reduced, while d2 can be reduced by reducing d 1. Since the d1 value is the opening of the developed photoresist, the lithographically defined line width of the contact hole can be directly determined by the d1 value.
When the thickness of the interlayer film 5 is increased, the opening line width of the etched contact hole is reduced, and the photolithography definition line width of the contact hole needs to be increased in step 33. Namely: if the tested Δ d2 is negative, it indicates that d2 is smaller, and it is necessary to increase d2, but the increase of d2 can be realized by increasing d 1. Since the d1 value is the opening of the developed photoresist, the lithographically defined line width of the contact hole can be directly determined by the d1 value.
Typically, step 31 is performed before step one, and comprises the following steps:
and providing a second wafer which finishes the opening etching process of the contact hole, wherein the photoetching defined line width of the contact hole of the second wafer adopts an unadjusted design value, and the opening etching process parameters of the contact hole of the second wafer are the same as those of the contact hole of the first wafer.
The thickness of the interlayer film 5 was measured for each region on the second wafer.
And measuring the opening line width of the contact hole after the development and the opening line width of the contact hole after the etching of each area on the second wafer.
And calculating the first proportional coefficient according to the thickness of the interlayer film 5 in each area and the opening line width of the etched contact hole. Typically, the first scaling factor is greater than 0 and equal to or less than 0.7.
And determining the proportional relation between the opening line width of the contact hole after the development and the opening line width of the contact hole after the etching.
In the embodiment of the invention, the thickness distribution of the interlayer film 5 is measured in advance before the photoetching process of the contact hole is carried out, and then the photoetching defined line width of the contact hole is adjusted according to the thickness distribution of the interlayer film 5, namely, the photoetching defined line width of the contact hole is constant and different from the photoetching defined line width of the contact hole in the prior art, the photoetching defined line width of the contact hole in the embodiment of the invention can change along with the thickness change of the interlayer film 5, thereby being capable of offsetting the influence of the thickness change of the interlayer film 5 on the opening line width of the etched contact hole, and can ensure that the opening line width of the contact hole in the corresponding area after etching meets the required value, finally is beneficial to the equal proportional reduction of the device size and can improve the electrical performance and yield of the reduced semiconductor device, for example, when the embodiment of the invention is applied to a 28HKMG process, the opening of the etched contact hole can meet the requirement value, so that the electrical performance and the product yield of the device can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A method for manufacturing a contact hole is characterized by comprising the following steps:
forming an interlayer film on a first wafer with a semiconductor substrate;
measuring the thickness of the interlayer film in each area of the first wafer;
adjusting the photoetching defined line width of the contact hole in the corresponding area according to the thickness value of the interlayer film in each area of the first wafer so as to compensate the influence of the thickness of the interlayer film on the opening line width of the contact hole after subsequent etching and ensure that the opening line width of the contact hole in the corresponding area after etching meets the required value;
fourthly, defining an opening area of the contact hole in each area of the first wafer by a photoetching process; the opening size of the contact hole in each area is defined by the corresponding adjusted photoetching definition line width;
and fifthly, removing the interlayer film in the opening area of the contact hole by an etching process to form an opening of the contact hole.
2. The method for manufacturing a contact hole according to claim 1, wherein: the semiconductor substrate is a silicon substrate;
forming semiconductor devices on the semiconductor substrate, each of the semiconductor devices including a gate structure;
each of the semiconductor devices further includes a source region and a drain region.
3. The method for manufacturing a contact hole according to claim 2, wherein: the grid structure comprises a grid dielectric layer and a polysilicon grid which are sequentially overlapped.
4. The method for manufacturing a contact hole according to claim 2, wherein: the grid structure comprises a grid dielectric layer and a metal grid which are sequentially overlapped.
5. The method for manufacturing a contact hole according to claim 4, wherein: the process node of the semiconductor device is below 28 nanometers.
6. The method for manufacturing a contact hole according to claim 4, wherein: the gate dielectric layer comprises a high dielectric constant layer, and the metal gate comprises a work function layer.
7. The method for manufacturing a contact hole according to claim 2, wherein: the interlayer film covers the top surface and the side surface of the gate structure and the surface of the semiconductor substrate outside the gate structure.
8. The method for manufacturing a contact hole according to claim 7, wherein: and a contact etching stop layer is also formed at the bottom of the interlayer film, the contact etching stop layer covers the top surface and the side surface of the grid structure and the surface of the semiconductor substrate outside the grid structure, and the interlayer film is formed on the surface of the contact etching stop layer.
9. The method for manufacturing a contact hole according to claim 1, wherein: in the fourth step, the photoetching process comprises the following sub-steps:
sequentially forming an APF layer, a DARC layer, a BARC layer and photoresist on the surface of the interlayer film;
and carrying out exposure development on the photoresist.
10. The method for manufacturing a contact hole according to claim 1, wherein: and after the step four is finished, carrying out ADI detection, wherein the ADI detection measures the opening line width of the contact hole after development, and the opening line width of the contact hole after development is determined by the adjusted photoetching defined line width.
11. The method for manufacturing a contact hole according to claim 10, wherein: and after the step five is finished, AEI detection is further carried out, the AEI detection is used for measuring the opening line width of the etched contact hole, the opening line width of the etched contact hole is in direct proportion to the size of the opening line width of the developed contact hole, the opening line width of the etched contact hole is related to the thickness of the interlayer film, and the influence of the thickness of the interlayer film on the opening line width of the etched contact hole is compensated through the adjusted photoetching defined line width, so that the opening line width of the etched contact hole in each area with different thicknesses meets the requirement value.
12. The method for manufacturing a contact hole according to claim 11, wherein: the third step comprises the following sub-steps:
step 31, the step before adjusting the photoetching defined line width of the contact hole, includes: determining a first proportionality coefficient between a first variation value of the thickness of the interlayer film and a second variation value of the opening line width of the etched contact hole under the condition that the photoetching definition line width of the contact hole is kept to be an unadjusted design value, wherein the first variation value is a deviation between an actual thickness value and a design value of the interlayer film, and the second variation value is a corresponding deviation of the opening line width of the etched contact hole when the thickness of the interlayer film is at the actual value and the design value;
step 32, calculating a first variation value of the interlayer film in each region according to the measured thickness value of the interlayer film, and calculating a second variation value corresponding to the lithographic defined line width of the contact hole when the lithographic defined line width adopts an unadjusted design value according to the first scale coefficient;
and step 33, adjusting the lithography definition line width of the contact hole in the corresponding area according to the second variation value by utilizing the proportional relation between the opening line width of the etched contact hole and the size of the developed opening line width of the contact hole, so that the corresponding second variation value tends to 0nm when the lithography definition line width of the contact hole adopts the adjustment value.
13. The method for manufacturing a contact hole according to claim 12, wherein: step 31, which is performed before step one, comprises the following steps:
providing a second wafer which finishes the opening etching process of the contact hole, wherein the photoetching defined line width of the contact hole of the second wafer adopts an unadjusted design value, and the opening etching process parameters of the contact hole of the second wafer are the same as those of the contact hole of the first wafer;
measuring the thickness of the interlayer film at each region on the second wafer;
measuring the opening line width of the contact hole after the development and the opening line width of the contact hole after the etching of each area on the second wafer;
calculating the first proportional coefficient according to the thickness of the interlayer film in each area and the opening line width of the etched contact hole;
and determining the proportional relation between the opening line width of the contact hole after the development and the opening line width of the contact hole after the etching.
14. The method for manufacturing a contact hole according to claim 13, wherein: when the thickness of the interlayer film is increased, the opening line width of the etched contact hole is reduced, and the photoetching definition line width of the contact hole needs to be increased in step 33;
when the thickness of the interlayer film is reduced, the opening line width of the etched contact hole is increased, and the photolithography definition line width of the contact hole needs to be reduced in step 33.
15. The method for manufacturing a contact hole according to claim 13, wherein: the first scale factor is greater than 0 and equal to or less than 0.7.
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| JP2006093533A (en) * | 2004-09-27 | 2006-04-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| KR100950553B1 (en) * | 2007-08-31 | 2010-03-30 | 주식회사 하이닉스반도체 | Method for forming contact in semiconductor device |
| DE102009006798B4 (en) * | 2009-01-30 | 2017-06-29 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | A method of fabricating a metallization system of a semiconductor device using a hard mask to define the size of the via |
| CN102299100B (en) * | 2010-06-23 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of contact hole |
| CN103915378B (en) * | 2014-04-08 | 2017-03-29 | 上海华力微电子有限公司 | A kind of lithographic method for improving contact hole live width homogeneity |
| CN110767602B (en) * | 2019-10-17 | 2022-03-18 | 上海华力集成电路制造有限公司 | Contact hole forming method |
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