KR20060064998A - Method for forming a deep contact hole in semiconductor device - Google Patents

Abstract

The present invention solves a phenomenon in which the bottom of a deep contact hole, which occurs during a deep contact hole forming process of a semiconductor device using a hard mask, does not open, and a bending (or bending) phenomenon of a deep contact hole profile is solved, thereby contacting an underlying conductive layer. The present invention relates to a method for forming a deep contact hole of a semiconductor device capable of increasing a contact resistance and thereby reducing contact resistance. The present invention provides a semiconductor substrate having a ground conductive layer formed in an interlayer insulating film; Forming a hard mask on the semiconductor substrate, the opening of the upper portion having a larger width than the opening of the lower portion; A method of forming a deep contact hole in a semiconductor device, the method including forming a deep contact hole through which an underlying conductive layer is exposed by performing an etching process using the hard mask.

Semiconductor element, deep contact hole, hard mask, amorphous carbon film, SiON film

Description

Method for forming deep contact hole in semiconductor device {METHOD FOR FORMING A DEEP CONTACT HOLE IN SEMICONDUCTOR DEVICE}             

1A to 1D are cross-sectional views illustrating profiles of a hard mask according to a critical dimension of a deep contact hole.

2A to 2C are cross-sectional views for explaining an overlap margin with an underlying conductive layer when the opening of the lower portion of the hard mask has an elliptical shape.

3 is a cross-sectional view illustrating a problem of a contact hole formed through a deep contact hole forming method of a semiconductor device according to the prior art;

4A to 4E are cross-sectional views illustrating a method for forming a deep contact hole in a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10 semiconductor substrate 11: base conductive layer

12 interlayer insulating film 13 amorphous carbon film

14 SiON film (or SiN film) 15 hard mask                 

16: antireflection film 17: photoresist pattern

18: deep contact hole 13a, 13b: opening

The present invention relates to a deep contact hole forming method of a semiconductor device, and more particularly, to a deep contact hole forming process for metal contact of a semiconductor device using a hard mask.

Due to the reduction of design rules due to the high integration of semiconductor devices, more precise process control is required in the manufacturing process of semiconductor devices. In particular, in the case of DRAM, the thickness of 0.115 μm or less may be used to connect a metal line and a bit line, between a conductive layer and a bit line on a substrate, or between an active region of a substrate and a capacitor electrode. There is a growing interest in the process of forming metal contacts.

However, due to an increase in the level difference due to the high integration of the semiconductor device, many difficulties are caused in the etching process for forming the deep contact hole for the metal contact of the semiconductor device. In general, a photoresist is used as an etching mask in the deep contact hole etching process. However, in recent years, as the DRAM devices have been highly integrated, the thickness of the photoresist has been inevitably reduced. As a result, when the photoresist is used alone as an etching mask in the deep contact hole etching process, the upper portion of the lower layer etched during the etching process is lost. Phenomenon occurs. This phenomenon occurs due to the loss of a portion of the photoresist due to the lack of a margin of thickness in the deep contact hole etching process.

Accordingly, recently, a hard mask scheme has been proposed and applied to a deep contact hole etching process. The hard mask scheme is a process of using a hard mask instead of a photoresist as an etching mask, and typically a tungsten or polysilicon film is used as the hard mask.

However, when the hard mask is used as a tungsten or polysilicon film, the following problems arise.

First, in the case of performing the deep contact hole etching process using the polysilicon film as a hard mask, the polysilicon film should be deposited to a thickness of at least 3000 GPa in order to secure sufficient etching margin during the deep contact hole etching process. As a result, the polysilicon film deposition time is increased to increase the process time and delay. In addition, as the thickness of the polysilicon film is increased, the hard mask etching becomes more difficult, thereby obtaining a worsted profile after the hard mask etching process as illustrated in FIGS. 1A to 1D. As a result, as the etching process is performed using a hard mask having a warped profile, the area of the bottom of the deep contact hole is reduced. Here, FIG. 1A is a case where the critical dimension of the deepest contact hole is the smallest, and FIG. 1D is the case where it is the largest.                         

In the case of performing the deep contact hole etching process using tungsten as the hard mask, the etching selectivity characteristics are superior to the hard mask using the polysilicon film, but the hard mask removal process is difficult after forming the deep contact hole. In addition, when tungsten is used as a hard mask, residues such as metal particles are generated during the process, thereby causing a problem in the process. Moreover, tungsten has not yet been sufficiently verified as a hard mask material, and thus there is a limit to applying tungsten to the hard mask.

As described above, when the deep contact hole etching process is performed using the hard mask according to the related art, as shown in FIGS. 2A to 2C, the area of the lower side of the hard mask is not only reduced, but also has an elliptical shape. As a result, there is a lack of overlap margin with the underlying conductive layer, which causes device defects. In extreme cases, as shown in FIG. 3, not only the bottom of the deep contact hole does not open during the deep contact hole etching process, but also a bending of the deep contact hole profile in which the deep contact hole is bent is caused. There is an urgent need to develop comprehensive measures to improve these problems.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, the phenomenon that the bottom of the deep contact hole that occurs during the deep contact hole formation process of the semiconductor device using a hard mask is not opened, and the bending of the deep contact hole profile It is an object of the present invention to provide a method for forming a deep contact hole in a semiconductor device capable of improving the yield of the semiconductor device by reducing the contact resistance by increasing the contact area with the underlying conductive layer by solving the phenomenon.

According to an aspect of the present invention, there is provided a semiconductor substrate having a base conductive layer formed in an interlayer insulating film, and a hard mask having an opening at an upper portion of the semiconductor substrate having a width greater than that of a lower portion. And forming a deep contact hole through which the underlying conductive layer is exposed by performing an etching process using the hard mask to form the deep contact hole.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

4A through 4E are cross-sectional views illustrating a method of forming a deep contact hole for a metal contact of a DRAM device in order to explain a method of forming a deep contact hole in a semiconductor device according to an exemplary embodiment of the present invention.

As shown in FIG. 4A, a base conductive layer 11 is formed on a semiconductor substrate 10 on which a semiconductor structure layer (not shown) is formed through a series of semiconductor manufacturing processes. In this case, the semiconductor structure layer may include a junction region, a conductive layer, a contact plug, an insulating film, and the like.

Next, an interlayer insulating film 12 is deposited over the entire structure including the underlying conductive layer 11. In this case, the interlayer insulating film 12 is formed of an oxide film-based material. For example, the interlayer insulating layer 12 may include a high density plasma (HDP) film, a boron phosphorus silicate glass (BPSG) film, a phosphorus silicate glass (PSG) film, a tetra ethoxy ortho silicate (TEOS) film, and an un-doped silicate glass (USG) film. It can be formed in a single layer using any one of a film, a Fluorinated Silicate Glass (FSG) film, a Carbon Doped Oxide (CDO) film, and an Organo Silicate Glass (OSG) film, or they can be formed in a laminated structure in which at least two layers are laminated. have.

Subsequently, a planarization process using a chemical mechanical polishing (CMP) process may be performed to planarize the upper portion of the interlayer insulating layer 12.

Subsequently, a hard mask 15 is deposited on the interlayer insulating film 12. At this time, the hard mask 15 is formed in a laminated structure of an amorphous carbon film 13 and a SiON film 14 (or SiN film). In addition, the hard mask 15 may be formed of a polysilicon film, tungsten, a TiN film, or the like.

Next, the anti-reflection film 16 is applied on the hard mask 15. In this case, the anti-reflection film 16 is formed of an organic bottom anti-reflection coating film. Here, the antireflection film is made of an organic material or an inorganic material.

Subsequently, after the photoresist is applied on the hard mask 15, the photoresist pattern 17 is formed by sequentially performing exposure and development processes using the photomask.

Subsequently, as illustrated in FIG. 4B, an etching process using the photoresist pattern 17 as an etching mask is performed to etch the SiON film 14, which is an upper layer of the antireflection film 16 and the hard mask 15. At this time, the etching process is performed using CF ₄ and O ₂ plasma gas.

Subsequently, as shown in FIG. 4C, an etching process using N ₂ and O ₂ plasma gases is performed in-situ to etch the amorphous carbon film 13, which is the lower layer of the hard mask 15. . By this etching process, the photoresist pattern 17 and the antireflection film 16 are removed. If not removed, it may be removed by a separate strip process and / or cleaning process.

Next, as shown in FIG. 4D, the SiON film 14, which is the upper layer of the hard mask 15, is removed. In this case, a portion of the exposed interlayer insulating layer 12 may be recessed to form a groove 18a.

Subsequently, as shown in FIG. 4E, an etching process using CF ₄ and O ₂ plasma is performed to form an amorphous carbon film 13 having a tapered profile in the upper portion in the etched portion direction. . That is, the opening 13b is formed in the lower portion of the direction in contact with the interlayer insulating film 12 so as to have a circular profile, and the upper portion thereof is tapered so that the opening 13a has a larger circular profile than the opening 13b in the lower portion. Form a profile. Thus, the lower opening 13b of the amorphous carbon film 13, which is used as an etch mask during the etching process of the deep contact hole 18 (see FIG. 4F), maximizes the opening 13a of the upper portion while maintaining the circular shape. The etching margin may be improved during the etching process while improving the overlap margin with the layer 11. Meanwhile, the interlayer insulating layer 12 exposed by the etching process is etched to deepen the groove 18a formed in the interlayer insulating layer 12.

Subsequently, as shown in FIG. 4F, an etching process using an amorphous carbon film 13 having a tapered profile 13a is performed to form a deep contact hole 19 through which the underlying conductive layer 11 is exposed. . At this time, the etching process uses a fluorine-based gas. Here, the fluorine-based gas is C ₄ F ₆ , C ₃ F ₆ , C ₅ F ₈ , C ₃ F ₃ as the main etching gas.

Subsequently, the stripped amorphous carbon film 13 is removed by performing a strip process using N ₂ and O ₂ plasma gases.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment using a DRAM device as an example, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a deep contact is formed after the tapered profile is formed in the upper portion of the hard mask used as an etch mask in the deep contact hole forming process for the metal contact of the semiconductor device to have an opening larger than the opening in the lower portion. By performing the hole etching process, the etching margin can be improved while maintaining the overlap margin with the underlying conductive layer.

Accordingly, in the present invention, the bottom contact of the deep contact hole is not opened, and the contact resistance between the metal contact and the underlying conductive layer formed through a subsequent process is solved by increasing the contact area with the underlying conductive layer by solving the phenomenon of bending the deep contact hole profile. It is possible to improve the yield of the semiconductor device by reducing the.

Claims (11)

Providing a semiconductor substrate having an underlying conductive layer formed in an interlayer insulating film; Forming a hard mask on the semiconductor substrate, the opening of the upper portion having a larger width than the opening of the lower portion; And Forming a deep contact hole through which the underlying conductive layer is exposed by performing an etching process using the hard mask; Deep contact hole forming method of a semiconductor device comprising a. The method of claim 1, The hard mask is a deep contact hole forming method of a semiconductor device, which is formed of a laminated film in which an amorphous carbon film and a SiON film or an amorphous carbon film and a SiN film are laminated. The method of claim 1, The hard mask is a deep contact hole forming method of a semiconductor device formed of a single film using a polysilicon film, tungsten, TiN film or amorphous carbon film. The method of claim 1, wherein the forming of the hard mask comprises: Depositing the hard mask in a stacked structure of first and second layers on the semiconductor substrate; Forming a photoresist pattern on the hard mask; Etching the second layer and the first layer of the hard mask by performing an etching process using the photoresist pattern; Removing the second layer, which is an upper layer of the hard mask; And Recessing an upper portion of the first layer to form a tapered profile such that the opening of the upper portion of the first layer has a larger circle than the opening of the lower portion of the first layer; Deep contact hole forming method of a semiconductor device comprising a. The method of claim 4, wherein The etching of the second layer may be performed by an etching process using CF ₄ and O ₂ plasma. The method of claim 4, wherein The etching of the first layer may be performed by using an etching process using N ₂ and O ₂ plasma. The method of claim 4, wherein Removing the second layer is a deep contact hole forming method of a semiconductor device is performed by an etching process using CF ₄ and O ₂ plasma. The method of claim 4, wherein The tapered profile of the first layer is a deep contact hole forming method of a semiconductor device is formed by an etching process using N ₂ and O ₂ plasma. The method of claim 4, wherein And forming an anti-reflection film on the hard mask after depositing the hard mask, wherein the anti-reflection film is an organic material or an inorganic material. The method of claim 1, The etching process is a deep contact hole forming method of a semiconductor device using a fluorine-based gas. The method of claim 10, The fluorine-based gas is C ₄ F ₆ , C ₃ F ₆ , C ₅ F ₈ , C ₃ F ₃ The deep contact hole forming method of a semiconductor device as the main etching gas.

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