KR20010005156A - Fabricating method for semiconductor device - Google Patents

Abstract

PURPOSE: A method for making a semiconductor device is provided to prevent a loss of a junction area of a semiconductor substrate without adding a new fabrication process for preventing an excessive etching, by forming a landing plug contact. CONSTITUTION: An element isolation layer(31) is formed on a part which is determined as an element isolation area on a semiconductor substrate(30). A gate insulating layer is formed on the semiconductor substrate, and forms a gate electrode(32) on the gate insulating layer. A low-density impurity is ion-implanted on both semiconductor substrates of the gate electrode, thereby forming a source/drain junction area. An insulating layer spacer(34) is formed on a sidewall of the gate electrode. A conductive layer(35a) for a landing plug contact is formed on the total structure. A photoresist pattern for protecting a landing plug contact part is formed on the conductive layer for the landing plug contact. The photoresist pattern is used as an etching mask, the conductive layer for the landing plug contact is etched, and then the photoresist pattern is formed. The photoresist pattern is used as an etching mask, the conductive layer for the landing plug contact is etched, and then the photoresist pattern is removed. An interfacial insulating layer(37) is formed on the total structure, and is smoothened. The interfacial insulating layer and the conductive layer for the landing plug contact are removed by CMP(chemical mechanical polishing) process, thereby forming a landing plug contact.

Description

Fabrication method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for forming a landing plug contact without damaging the junction region.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure is limited using a deep ultra violet (DUV) light, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.

In addition, the contact holes connecting the upper and lower conductive wirings have a multi-layered structure due to the high integration of devices, and the gap between the size of the contact holes and the peripheral wirings is reduced and the aspect ratio, which is the ratio of the diameter and depth of the contact holes, is increased. In the highly integrated semiconductor device having the conductive wiring of, a precise and strict alignment between the masks in the manufacturing process is required to form a contact, thereby reducing the process margin.

In order to solve the problems caused by the high integration of the device as described above, the contact plugs are used when the conductive lines are connected to each other and the bit line and the storage electrode contacts are formed to increase the process margin.

Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 10 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the semiconductor substrate 10. An element isolation film 11 is formed on the portion intended as the element isolation region.

Next, a gate insulating film (not shown) is formed on the semiconductor substrate 10, a gate electrode 12 is formed, and ion implantation of low concentrations of impurities into both semiconductor substrates 10 of the gate electrode 12 is performed. The source / drain junction region 13 is formed. In this case, a mask insulating film pattern is stacked on the gate electrode 12.

Next, an insulating film spacer 14 is formed on the sidewall of the gate electrode 12.

Next, a pad nitride film 15 is formed over the entire surface for interlayer insulation with the device formed in a subsequent process.

Next, an interlayer insulating layer 16 having an etch selectivity with the pad nitride layer 15 is formed on the pad nitride layer 15 and planarized. (See FIG. 1A)

Next, a photoresist pattern 17 is formed on the interlayer insulating layer 16 to expose a portion where the landing plug contact is to be formed.

The interlayer insulating layer 16 is etched using the photoresist pattern 17 as an etch mask, and the pad nitride layer 15 is used as an etch stop layer. (See FIG. 1B)

Next, the pad nitride layer 15 is etched using the photoresist pattern 17 as an etching mask to expose the semiconductor substrate 10. In this case, the pad nitride layer 15 is formed to prevent the bonding region 13 of the semiconductor substrate 10 from being lost during the etching process of the interlayer insulating layer 16.

Next, the photoresist pattern 17 is removed and a landing plug contact conductive layer 18a is formed on the entire surface. (See FIG. 1C)

Thereafter, the landing plug contact conductive layer 18a is removed by a full surface etching or chemical mechanical polishing (hereinafter referred to as CMP) process to form the landing plug contact 18b. (See FIG. 1D)

As described above, the semiconductor device manufacturing method according to the related art has an interlayer insulating film and an etching selectivity in order to prevent the junction region of the semiconductor substrate from being lost due to the excessive etching during the etching process for exposing the part where the landing plug contact is to be formed. Although a pad nitride film having a thickness is formed, the thickness of the pad nitride film is so thin that it is removed by an overetching process, and thus there is a problem in that the characteristics of the device are adversely affected, such as loss of a junction area and causing leakage current.

The present invention, in order to solve the above problems of the prior art, to form a MOS field effect transistor and to form a conductive layer for the landing plug contact, and then to form a photosensitive film pattern to protect the portion where the landing plug contact is to be formed Using the photoresist pattern as an etching mask, the conductive layer for landing plug contact is etched, and then an interlayer insulating layer is formed and planarized, and then the insulating layer and the conductive layer for landing plug contact are etched by a CMP process. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can prevent the loss of the junction region of the semiconductor substrate without the addition of a new process for preventing excessive etching.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols on main parts of the drawing>

10, 30: semiconductor substrate 11, 31: device isolation film

12, 32: gate electrode 13, 33: junction region

14, 34 insulating film spacer 15 pad nitride film

16, 37: interlayer insulating film 17, 36: photosensitive film pattern

18a, 35a: conductive layer for landing plug contact 18b, 35b: landing plug contact

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

Forming a device isolation film on a portion of the semiconductor substrate, the device isolation region being formed on the semiconductor substrate;

Forming a gate insulating film over the semiconductor substrate and forming a gate electrode over the gate insulating film;

Forming a source / drain junction region by ion implanting low concentration impurities into both semiconductor substrates of the gate electrode;

Forming an insulating film spacer on sidewalls of the gate electrode;

Forming a conductive layer for landing plug contact on the entire surface;

Forming a photoresist pattern on the conductive layer for the landing plug contact to protect a portion intended as a landing plug contact;

Etching the conductive layer for landing plug contact using the photoresist pattern as an etching mask, and then removing the photoresist pattern;

Forming an interlayer insulating film over the entire surface to planarize it,

And removing the interlayer dielectric layer and the conductive layer for landing plug contact by chemical mechanical polishing to form a landing plug contact.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 30 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the semiconductor substrate 30 An element isolation film 31 is formed on the portion intended as the element isolation region. The device isolation layer 31 is formed by a trench method.

Next, a gate insulating film (not shown) is formed on the entire surface, and a gate electrode 32 is formed thereon, and a mask insulating film pattern (not shown) is stacked on the gate electrode 32.

Subsequently, a low concentration of n-impurities are ion-implanted on both semiconductor substrates 30 of the gate electrode 32 to form a source / drain junction region 33, and an insulating film spacer ( 34).

Next, the conductive layer 35a for landing plug contact is formed on the entire surface to be planarized. (See Figure 2A)

Next, a photosensitive film pattern 36 is formed on the conductive layer 35a of the landing plug contact to protect a region in which the landing plug contact is to be formed.

Next, the landing layer plug conductive layer 35a is etched using the photoresist pattern 36 as an etching mask. (See Figure 2b)

Thereafter, the photoresist pattern 36 is removed, and an interlayer insulating film 37 is formed on the entire surface to be planarized. (See FIG. 2C)

Then, the interlayer insulating layer 37 and the landing plug contact conductive layer 35a are removed by a CMP process, but the landing plug contact conductive layer 35a is separated from each other between the gate electrodes, thereby landing plug contact 35b. It is carried out to form. (See FIG. 2D)

As described above, in the method of manufacturing a semiconductor device according to the present invention, in the manufacturing process of a contact plug of a highly integrated semiconductor device, a MOS field effect transistor is formed and a conductive layer for landing plug contact is formed. After forming a photoresist pattern protecting the portion where the landing plug contact is to be formed on the layer, the conductive layer for the landing plug contact is etched using the photoresist pattern as an etch mask, and an interlayer insulating film is formed to be planarized, followed by chemical mechanical polishing By forming the landing plug contact by etching the interlayer insulating layer and the conductive layer for landing plug contact by a step, the semiconductor is not formed by an etching process for forming a contact hole without forming an etch stop layer for preventing excessive etching. Simplifies the process by preventing the loss of bonding area of the substrate It has the advantage that it and improve the characteristics and reliability of the semiconductor device thereof.

Claims (1)

Forming a device isolation film on a portion of the semiconductor substrate, the device isolation region being formed on the semiconductor substrate; Forming a gate insulating film over the semiconductor substrate and forming a gate electrode over the gate insulating film; Forming a source / drain junction region by ion implanting low concentration impurities into both semiconductor substrates of the gate electrode; Forming an insulating film spacer on sidewalls of the gate electrode; Forming a conductive layer for landing plug contact on the entire surface; Forming a photoresist pattern on the conductive layer for the landing plug contact to protect a portion intended as a landing plug contact; Etching the conductive layer for landing plug contact using the photoresist pattern as an etching mask, and then removing the photoresist pattern; Forming an interlayer insulating film over the entire surface to planarize it, And removing the interlayer dielectric layer and the conductive layer for landing plug contact by chemical mechanical polishing to form a landing plug contact.