KR100420413B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a MOS field effect transistor is formed on an upper surface of a semiconductor substrate during a bit line and a storage electrode contact plug forming process of a highly integrated semiconductor device, and then a bit line contact or a storage electrode contact on an entire surface Forming a laminated structure of a low dielectric material pattern and a hard mask to protect a predetermined portion, forming an isolation insulating film on the entire surface, and then planarizing to separate the low dielectric material pattern from the low dielectric material pattern. Removing the exposed portions to expose the contact plugs, and then forming a conductive layer and then flattening the contact plugs to form the low dielectric material pattern used as the sacrificial insulating layer. The laminated nitride film can be prevented from being damaged and the damage of the semiconductor substrate can be prevented. Since the technique of the contact resistance and can improve the leakage current characteristics, and correct the misalignment problem and ensure the contact area problem due to the inclined end surface etching is generated in the etching process resulting from the photolithography process to increase the tolerance of the process.

Description

Manufacturing method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which contact plugs are formed at portions defined as bit line contacts and storage electrode contacts of highly integrated devices.

The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the light source wavelength? And the process variable k of the reduced exposure apparatus, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a light source of deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 193 nm, to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is highly integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes have misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.

In order to overcome the limitations of the lithography process when forming the contact holes, a self aligned contact (SAC) technology for forming contact holes by a self alignment method has been developed.

The SAC method may be divided into a polysilicon layer, a nitride film, or an oxynitride film according to the material used as the etch barrier layer, and the most promising method is to use a nitride film as an etch barrier.

Although not shown, the SAC manufacturing method of the conventional semiconductor device will be described as follows.

First, a MOS field effect transistor (MOS FET) such as a gate electrode and a source / drain region overlapping a predetermined substructure, for example, a device isolation insulating film, a gate insulating film, and a mask oxide film pattern on a semiconductor substrate. And the like, and then sequentially form an etch stop film and an interlayer insulating film made of an oxide film on the entire surface of the structure.

Next, a photoresist pattern is formed on the semiconductor substrate to expose an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact such as a storage electrode or a bit line, and then an etch barrier is formed by dry etching the interlayer insulating film exposed by the photosensitive film pattern. It exposes and etches an etch stop layer again, and forms a contact hole.

However, according to the manufacturing method of the semiconductor device according to the prior art as described above, when forming the bit line contact and the storage electrode contact of the device to which the technology of 0.15㎛ or less is applied, the conventional circular type contacts are misaligned in the lithography process. Because of misalignment, there is a problem in securing contact area, so it is not applicable to device manufacturing. In order to improve this, a technique has been proposed to form a conductive layer after etching an oxide film by etching a T-type and an I-type, and then forming a plug by chemical mechanical polishing (hereinafter referred to as CMP). .

However, the T-type has a sufficient margin of misalignment of the bit line contact, but the storage electrode contact formation region has a technology of 0.13 μm or less in the problem of securing the contact region due to the inclined cross section that occurs during the misalignment and the contact oxide etching. It is difficult to apply in the device to which is applied. In addition, the I-type is to etch the oxide film by shifting the device isolation mask on the device isolation film. The etching area is wider than the mask area, so it is very difficult to secure a high selectivity for the nitride film. In order to secure a high selectivity with respect to the nitride film during oxide etching, the etching area should be larger than the unetched area. This is because the polymer may not sufficiently protect the nitride film if the etching area is larger than the non-etched area. In addition, since the etching is performed in the active region of the semiconductor substrate, the T-type or the I-type has a problem in that the contact resistance and the junction leakage current are large because the active region is exposed to plasma and damaged.

The present invention, in order to solve the above problems of the prior art, to form a low dielectric material pattern on the portion where the contact plug is formed by etching the low dielectric material on the device isolation insulating film for insulation between the contact plug, the contact plug as the isolation insulating film After insulating the liver and removing the low dielectric material pattern and forming a contact plug, a low dielectric material is etched without damage to the semiconductor substrate, thereby providing a method of manufacturing a semiconductor device which improves contact characteristics and leakage current characteristics. There is a purpose.

1 is a layout diagram of a method of manufacturing a semiconductor device according to the present invention;

2 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device along a line A-A 'of FIG.

<Description of Symbols for Major Parts of Drawings>

10 semiconductor substrate 12 device isolation insulating film

14 gate electrode 16 mask insulating film pattern

18: insulating film spacer 20a: low dielectric sacrificial insulating film

20b: low dielectric sacrificial insulating film pattern 22a: thin film for hard mask

22b: hard mask 24: photoresist pattern

26a: Separation insulating film 26b: Separation insulating pattern

28a: conductive layer 28b: contact plug

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a stacked structure of a gate insulating film, a gate electrode, and a mask insulating film pattern on a semiconductor substrate; Forming a source / drain region on both semiconductor substrates of the insulating film spacer, and forming a laminate structure of a low dielectric sacrificial insulating film pattern and a hard mask on a semiconductor substrate of a portion intended as a bit line contact and a storage electrode contact. Forming a separation insulating film on the entire surface, and planarizing the separation insulating film and the hard mask to expose the low dielectric sacrificial insulating film pattern, and removing the exposed low dielectric sacrificial insulating film pattern;

And forming a contact plug to bury a portion of the bit line contact and the storage electrode contact.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout diagram illustrating a method of manufacturing a semiconductor device according to the present invention, and FIGS. 2 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device along the line A-A 'of FIG. 1.

First, a device isolation film 12 is formed in a portion of the semiconductor substrate 10 that is intended as a device isolation region, and a gate insulating film (not shown) is formed over the entire surface.

Next, a stacked structure of a gate electrode conductive layer (not shown) and a mask insulating film (not shown) are formed on the gate insulating layer, and the gate electrode mask is etched using an etching mask to etch the gate electrode 14 and the mask. The insulating film pattern 16 is formed. Here, the mask insulating film is formed of a SiN film, a SiON film, a SiON film containing a large amount of Si (hereinafter referred to as SRON film), an Al ₂ O ₃ film or a Ta ₂ O ₅ film, and the etching process is performed using CF ₄ / O. _{Use 2} / Ar mixed gas or CHF ₃ / O ₂ / Ar mixed gas to make the etching surface vertical.

Next, an insulating film is formed on the entire surface and then etched to form an insulating film spacer 18 on the sidewalls of the gate electrode 14 and the mask insulating film pattern 16. The insulating film spacer 18 is formed of a SiN film. (See Fig. 2)

Next, although not shown, a low concentration of impurities are implanted into both semiconductor substrates 10 of the insulating film spacer 18 to form a source / drain region (not shown).

Next, a low dielectric sacrificial insulating film 20a is formed on the entire surface, and a thin film for hard mask 22a is formed on the low dielectric sacrificial insulating film 20a. In this case, the low dielectric sacrificial insulating film 20a is formed using an organic material such as SiLK, Flare, Velok, Cytop, Alcap, BCB and FlowFill and one selected from the group consisting of SiC and the thin film for hard mask ( 22a) is formed of an oxide film. (See Figure 3)

Next, a photoresist pattern 24 is formed on the hard mask thin film 22a to protect a portion where the contact plug is to be formed in the semiconductor substrate 10. The photoresist pattern 24 may be an I-type or a line type. Or T-shaped. (See Figure 4)

Next, a low dielectric sacrificial insulating pattern 20b for protecting a portion where a contact plug is to be formed by an etching process using the photoresist pattern 24 as an etching mask and a hard mask 22b on the low dielectric sacrificial insulating pattern 20b. ). In this case, the etching process is performed using a high etching selectivity so that the insulating film spacer 18 and the device isolation insulating film 12 are not damaged.

In addition, the etching process uses a gas containing oxygen, such as O ₂ , NO ₂ , N ₂ , SO ₂ , CO or CO ₂ as the first etching gas, N ₂ H ₂ , NH ₃ or C ₂ H ₄ By using a gas including, for example, hydrogen as the second etching gas, an etching selectivity can be increased with respect to the insulating film spacer 18 and the mask insulating film pattern 16 under the low dielectric sacrificial insulating film 20a, thereby improving the etching cross section. can do. In addition, an inert gas such as He, Ne, Ar, and Xe or an N ₂ gas may be used as the third etching gas in order to improve the uniformity of the plasma and to control the etching section or the etching rate.

Next, the photoresist pattern 24 is removed. (See Figure 5)

Next, a separation insulating film 26a is formed over the entire surface. In this case, the isolation insulating layer 26a is formed using a dielectric material such as an oxide film, a nitride film, or an oxynitride film, and is formed on the device isolation insulating film 12 to void in the isolation insulating film 26a. Does not cause a problem of shorting between contact plugs. (See Figure 6)

Next, the isolation dielectric layer 26a and the hard mask 22b are removed by a chemical mechanical polishing process or an entire surface etching process to expose the low dielectric sacrificial insulation layer pattern 20b. In the process, a separation insulating layer pattern 26b is formed between the low dielectric sacrificial insulating layer patterns 20b. (See Figure 7)

Next, the low dielectric sacrificial insulating film pattern 20b is removed. In this case, the low dielectric sacrificial insulating film pattern 20b is a wet etching process using a mixed solution of H ₂ O ₂ : H ₂ SO ₄ : deionized water or an isotropic dry etching method using the etching gas used in the etching process of FIG. 5. To remove it. (See Figure 8)

Next, a conductive layer 28a is formed over the entire surface. The conductive layer 28a is formed of a polycrystalline silicon layer or a tungsten layer including an optional tungsten layer or a Ti / TiN film or an optional epitaxially grown polycrystalline silicon layer. In this case, when the conductive layer 28a is formed of the selective epitaxially grown polysilicon layer, the planarization process may be omitted as a subsequent process. (See FIG. 9)

Thereafter, the conductive layer 28a is planarized by a chemical mechanical polishing process or an entire surface etching process to form a contact plug 28b connected to the semiconductor substrate 10. In this case, the mask insulating layer pattern 16 is used as an etch barrier. On the other hand, when the conductive layer 28a is removed by a full surface etching process, a gas containing fluorine composed of CF ₄ , NF ₃ , SF ₃ , C ₂ F ₄ , C ₂ F _6, etc., or Cl ₂ , BCl ₃ , HI And a halogen-containing gas composed of HBr and the like as the first etching gas, and a gas containing oxygen or N ₂ gas consisting of O ₂ , NO _, SO _2, CO, and CO ₂ is used as the second etching gas. In addition, by using an inert gas such as He, Ne, Ar, or Xe as the third etching gas, plasma stabilization and sputtering effects are increased to improve the etch stop phenomenon, thereby improving reproducibility. (See FIG. 10)

As described above, in the method of manufacturing a semiconductor device according to the present invention, a low dielectric material used as a sacrificial insulating film in a contact plug forming process of a highly integrated semiconductor device is etched on a device isolation insulating film and stacked on the sidewalls and the top of the gate electrode. Since the nitride film can be prevented from being damaged and the damage of the semiconductor substrate can be prevented, the contact resistance and leakage current characteristics can be improved. There is an advantage of improving the margin of the process by solving the securing problem.

Claims (11)

Forming a stacked structure of a gate insulating film, a gate electrode and a mask insulating film pattern on a semiconductor substrate; Forming an insulating film spacer on sidewalls of the stacked structure and forming a source / drain region on both semiconductor substrates of the insulating film spacer; Forming a laminate structure of a low dielectric sacrificial insulating film pattern and a hard mask on a semiconductor substrate of a portion intended as a bit line contact and a storage electrode contact; Forming a separation insulating film over the entire surface, and flattening etching the separation insulating film and the hard mask to expose the low dielectric sacrificial insulating film pattern; Removing the exposed low dielectric sacrificial insulating film pattern; And forming a contact plug to fill a portion of the bit line contact and the storage electrode contact. The method of claim 1, The mask insulating film pattern may be formed using one selected from the group consisting of a SiN film, a SiON film, a SiON film containing a large amount of Si, an Al ₂ O ₃ film, and a Ta ₂ O ₅ film. Manufacturing method. The method of claim 1, The mask insulating film pattern is a manufacturing method of a semiconductor device, characterized in that formed using the CF ₄ / O ₂ / Ar mixed gas or CHF ₃ / O ₂ / Ar mixed gas as an etching gas. The method of claim 1, The insulating film spacer is a semiconductor device manufacturing method, characterized in that formed by the SiN film. The method of claim 1, The low dielectric sacrificial insulating film is a semiconductor device manufacturing method characterized in that formed using one selected from the group consisting of SiLK, Flare, Velok, Cytop, Alcap, BCB and FlowFill organic material and SiC. The method of claim 1, The hard mask is a semiconductor device manufacturing method, characterized in that formed by the oxide film. The method of claim 1, The low-dielectric sacrificial insulating layer pattern uses a gas containing oxygen as a first etching gas, a gas containing hydrogen of N ₂ H ₂ and NH ₃ and C ₂ H ₄ as a second etching gas, and an inert gas. Or removing the N ₂ gas by using the third etching gas. The method of claim 1, The low dielectric sacrificial insulating film pattern is a semiconductor device manufacturing method characterized in that the removal by the wet etching process using a mixed solution of H ₂ O ₂ : H ₂ SO ₄ : deionized water. The method of claim 1, Wherein the contact plug is formed of a material selected from the group consisting of a polysilicon layer, a tungsten film, an optionally grown tungsten film, and an optional epitaxially grown silicon layer. delete The method of claim 9, When the contact plug is formed of a polysilicon layer, a selectively grown tungsten layer or a Ti / TiN layer, a fluorine-containing gas or a halogen-containing gas is used as the first etching gas, and a gas containing oxygen or an N ₂ gas is used. And forming a contact plug by using the second etching gas and planarizing the inert gas by a front surface etching process using the third etching gas.