KR20060114446A - Manufacturing method for semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent open fail of a cell region by forming a pad nitride layer at a lower portion of a hard mask layer. A first interlayer dielectric(12) having a contact plug(14) is formed on a substrate(10). A bit line is formed on the first interlayer dielectric to overlap a hard mask pattern. An insulating spacer is formed at both sidewalls of the bit line and the hard mask pattern. A second interlayer dielectric(22), a pad nitride layer(24) and a polysilicon hard mask layer(26) are sequentially formed on the resultant structure. The hard mask layer is selectively etched to expose the second interlayer dielectric, and the exposed second interlayer dielectric is firstly etched to form a storage node contact hole. The hard mask layer is eliminated. A contact hole(28) is then formed by secondly etching the storage node contact hole using the pad nitride layer as a mask. A contact plug is then formed in the contact hole.

Description

Manufacturing method for semiconductor device

1A to 1C are manufacturing process diagrams of a semiconductor device according to the present invention.

         <Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 12 first interlayer insulating film

14: contact plug 16: bit line

18: hard mask layer 20: spacer

22: second interlayer insulating film 22 and 24: buffer nitride film

26 hard mask layer 28 contact hole for charge storage electrode

30: contact hole spacer 32: contact plug for charge storage electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a charge storage electrode contact hole forming process performed after bit line formation, a buffer nitride film is used together with a polysilicon layer hard mask layer, and the charge storage electrode is subjected to two etching processes. The present invention relates to a method for manufacturing a semiconductor device that can prevent contact defects in the cell area by opening contact holes, thereby preventing deterioration of process yield and reliability of device operation.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A tri layer resister (hereinafter referred to as a TLR) in which a contrast enhancement layer (CEL) method or an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. A method or a silicide method for selectively injecting silicon on top of the photoresist film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the diameter of the contact hole is reduced. The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

Since the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current state of the art, there is a limit to high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

Although not shown, the process of forming the charge storage electrode contact hole of the semiconductor device according to the related art is as follows.

First, a lower structure such as a device isolation oxide film, a gate electrode, and a MOSFET such as a source / drain region is formed on a semiconductor substrate, and a first interlayer insulating film including a contact plug is formed on the entire surface of the structure. A bit line overlapping the hard mask of a nitride film material is formed on the interlayer insulating film, and a nitride film spacer is formed on the sidewall of the bit line pattern.

Then, a second interlayer insulating film is formed on the entire surface of the structure, and the top surface is planarized by chemical mechanical polishing, and then a hard mask layer of polycrystalline silicon layer is formed on the second interlayer insulating film. In this case, the hard mask layer is used because the ArF photoresist film used in the design rule of about 80 nm has poor etching resistance.

Thereafter, the hard mask layer is photo-etched with a photoresist pattern for forming a contact hole for a charge storage electrode to form a hard mask layer pattern, and the second interlayer insulating layer is removed using the hard mask layer pattern as a mask for charge storage electrode. A contact hole is formed.

Then, the hard mask layer is removed, a polysilicon layer which becomes a contact plug is applied to the entire surface of the structure to fill the contact hole, and the polysilicon layer on the contact hole is removed by chemical-mechanical polishing or the like. A contact plug having a polysilicon layer pattern is formed, and a capacitor is formed thereon.

In the method of manufacturing a semiconductor device according to the related art as described above, a polysilicon layer is used as a hard mask of a charge storage electrode contact hole etching process, but a considerable thickness of the polysilicon layer of a peripheral circuit region is removed during the contact hole forming process. In the cell region, many residues remain in the cell region, and dishing occurs in the cell region rather than the peripheral circuit region during the etching of the hard mask layer or chemical mechanical polishing. There is a problem of lowering yield and reliability of device operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use a buffer nitride film together with a polysilicon layer hard mask layer in a contact forming process for charge storage electrodes, and charge storage electrode contacts in two etching processes. The present invention provides a method of manufacturing a semiconductor device that can improve the process yield and the reliability of device operation by preventing the open defect in the cell area by opening the hole.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a first interlayer insulating film having a contact plug on the semiconductor substrate;

Forming a bit line overlapping the hard mask pattern on the first interlayer insulating film;

Forming an insulating film spacer on sidewalls of the bit line and the hard mask pattern;

Sequentially forming a second interlayer insulating film, a pad nitride film, and a hard mask layer made of polycrystalline silicon on the entire surface of the structure;

Etching the hard mask layer using a photolithography process using a charge storage electrode contact mask to expose the second interlayer insulating film, and first etching the exposed second interlayer insulating film to form a contact hole for a charge storage electrode. and,

Removing the hard mask layer;

Second etching the contact holes with the pad nitride layer as a mask to complete the contact holes;

And forming a contact plug to fill the contact hole.

In another aspect of the present invention, the second interlayer insulating film is formed to a thickness of 5000 to 10000 kPa, the buffer nitride film is formed to a thickness of 300 to 1000 kPa, and the primary etching process for forming the contact hole is C ₄ F ₈ / C ₅ Etch F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / O ₂ / CO / N ₂ using a mixed gas at a pressure of 10 to 100 mTorr and a power of 1000 to 2000 W, with the bottom of the bit line as a target. Before the hard mask layer is removed, the process of cleaning using a BOE in which H ₂ SO ₄ + H ₂ 0 ₂ is mixed at 300: 1 in a separate cleaning process, and C ₂ at the time of removing the hard mask layer. Using a F ₆ / HBr / Cl ₂ mixed gas at a pressure of 1 to 20mTorr, 10 to 1000W power, the secondary etching process is C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ Etching with 1000 to 2000W power at 10 to 100 mTorr pressure using / Ar / O ₂ / CO / N ₂ mixed gas Gong.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are manufacturing process diagrams of a semiconductor device according to the present invention.

First, a predetermined substructure, for example, a device isolation oxide film, a MOSFET including a gate electrode and a source / drain region, is formed on the semiconductor substrate 10, and an oxide film including contact plugs 14 for charge storage electrodes is formed. After forming the first interlayer insulating film 12 of a material, after forming the bit line 16 on the first interlayer insulating film 12 overlapping the hard mask layer 18 pattern of a nitride film material The nitride film is entirely coated on the entire surface of the structure, and the nitride film spacer 20 is formed on the sidewalls of the bit line 16 and the hard mask layer 18 by etching the entire surface.

Here, the bit line 16 is formed as a barrier layer with a Ti / TiN layer having a thickness of about 100 to 1000 mW, and when the bit line 16 is W, the bit line 16 has a thickness of about 300 mW to 1000 mW, and the hard mask layer 18 It is formed to a thickness of about 2000 to 4000 kPa. In addition, the hard mask layer 18 is etched at 300 to 1000W power at 10 to 100mTorr pressure using CF ₄ / CHF ₃ / O ₂ mixed gas, the W layer is SF ₆ / BCl ₃ / N ₂ / Cl ₂ The mixed gas is etched at 300 to 1000 W power at 20 to 70 mTorr pressure. In addition, the spacer 20 is formed by depositing a nitride film with a thickness of about 200 to 1000 kPa, and using a CF ₄ / CHF ₃ / O ₂ mixed gas to etch the entire surface at 300 to 1000 W power at a pressure of 20 to 70 mTorr.

Thereafter, the second interlayer insulating film 22, the buffer nitride film 24, and the polysilicon material hard mask layer 26 are sequentially formed on the entire surface of the structure. In this case, the second interlayer dielectric layer 22 is formed to a thickness of about 5000 to 10000 GPa, and the buffer nitride film 24 is formed to be about 300 to 1000 GPa thick. (See FIG. 1A).

Next, the hard mask layer 26 is patterned by a photolithography process using a photoresist pattern (not shown) for forming a contact hole for a charge storage electrode, thereby patterning the hard mask layer 26 and the buffer nitride layer 24 to form a second layer. The interlayer insulating layer 22 is exposed, and the second interlayer insulating layer 22 is first etched to form a contact hole 28 for a charge storage electrode, and the polysilicon hard remaining in the photoresist pattern, the peripheral circuit region, and the cell region. The mask layer 26 is removed.

Wherein the primary etching process using a mixed gas, such as C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / O ₂ / CO / N _{2 at a} pressure of 10 to 100mTorr, 1000 to Etching is performed at 2000W power, and the bottom surface of the bit line 16 is etched with a target. In addition, when the photoresist pattern is removed, the polymer generated in the pre-etching process is also removed. In this case, when the cleaning is performed using a BOE mixed with H ₂ SO ₄ + H ₂ 0 ₂ in a mixture of 300: 1, it occurs during etching. The removed polymer can be removed and the bottom area of the contact hole can be increased.

In addition, during the removal of the hard mask layer 26, the etching selectivity between the polysilicon layer and the buffer nitride layer is increased to 10: 1 or more to prevent damage to other layers, and the C ₂ F ₆ / HBr / Cl ₂ mixed gas is used. To 1 to 20mTorr pressure, 10 to 1000W power, and etch selectivity with the buffer film to increase to 10: 1 or more. (See FIG. 1B).

Thereafter, using the buffer nitride film pattern 24 as a mask, the second interlayer insulating film 22 remaining in the contact hole 28 is removed to expose the contact plug 14, and C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / O ₂ / CO / N ₂ using a mixed gas such as 10 to 100mTorr pressure, 1000 to 2000W power to open by etching.

Next, a contact hole spacer 30 made of a nitride film is formed on the sidewall of the contact hole 28, and a contact plug 32 for a charge storage electrode filling the contact hole 28 is formed of a polysilicon layer. Here, the spacer 30 is deposited on the entire surface of the nitride film with a thickness of about 100 to 400Å, and using the mixed gas such as C ₄ F ₈ / CHF ₃ / CF ₄ / Ar / O ₂ / CO / N ₂ to 10 to 100 mTorr The pressure is formed by etching at 300 to 2000 W power, and the polysilicon layer for the contact plug 32 is applied to the entire surface with a thickness of about 2000 to 4000 kPa, and the entire surface is etched. (See FIG. 1C).

As described above, in the method of manufacturing a semiconductor device according to the present invention, an etching process for forming a charge storage electrode contact hole on a semiconductor substrate formed up to a bit line is performed through a plurality of etching processes, thereby expanding the contact hole. Since the contact hole was first opened through the pad nitride film under the hard mask layer made of the polysilicon layer, the polysilicon layer was removed, the pad nitride film was etched again with the mask, and then the contact hole was formed. By preventing open defects in the cell area, there is an advantage to improve process yield and device operation reliability.

Claims (6)

Forming a first interlayer insulating film having a contact plug on the semiconductor substrate; Forming a bit line overlapping the hard mask pattern on the first interlayer insulating film; Forming an insulating film spacer on sidewalls of the bit line and the hard mask pattern; Sequentially forming a second interlayer insulating film, a pad nitride film, and a hard mask layer made of polycrystalline silicon on the entire surface of the structure; Etching the hard mask layer using a photolithography process using a charge storage electrode contact mask to expose the second interlayer insulating film, and first etching the exposed second interlayer insulating film to form a contact hole for a charge storage electrode. and, Removing the hard mask layer; Second etching the contact holes with the pad nitride layer as a mask to complete the contact holes; And forming a contact plug to fill the contact hole. The method of claim 1, wherein the second interlayer insulating film is formed to a thickness of 5000 to 10000 GPa, and the buffer nitride film is formed to be 300 to 1000 GPa thick. The method of claim 1, wherein the primary etching process for forming the contact hole is performed using a mixture of C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / O ₂ / CO / N _2. A method of manufacturing a semiconductor device, characterized in that the etching is performed at 1000 to 2000W power at a pressure of 10 to 100 mTorr, and the bottom surface of the bit line is targeted. The semiconductor device of claim 1, further comprising a step of cleaning using a BOE in which H ₂ SO ₄ + H ₂ O ₂ is mixed at 300: 1 by a separate cleaning step before removing the hard mask layer. Manufacturing method. The method of claim 1, wherein in the hard mask layer removing process, the C ₂ F ₆ / HBr / Cl ₂ mixed gas is etched at a power of 1 to 20 mTorr at 10 to 1000 W power. The method of claim 1, wherein the secondary etching process is performed at a pressure of 10 to 100 mTorr using a C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / O ₂ / CO / N ₂ mixed gas. And manufacturing the semiconductor device by etching with a power of 1000 to 2000W.

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