KR20000045358A - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
- Publication number
- KR20000045358A KR20000045358A KR1019980061916A KR19980061916A KR20000045358A KR 20000045358 A KR20000045358 A KR 20000045358A KR 1019980061916 A KR1019980061916 A KR 1019980061916A KR 19980061916 A KR19980061916 A KR 19980061916A KR 20000045358 A KR20000045358 A KR 20000045358A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- etching
- via contact
- gas
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 62
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 59
- 230000008569 process Effects 0.000 claims description 33
- 150000004767 nitrides Chemical class 0.000 claims description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- YPSXFMHXRZAGTG-UHFFFAOYSA-N 4-methoxy-2-[2-(5-methoxy-2-nitrosophenyl)ethyl]-1-nitrosobenzene Chemical compound COC1=CC=C(N=O)C(CCC=2C(=CC=C(OC)C=2)N=O)=C1 YPSXFMHXRZAGTG-UHFFFAOYSA-N 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 98
- 239000007789 gas Substances 0.000 description 19
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 102100025840 Coiled-coil domain-containing protein 86 Human genes 0.000 description 1
- 101000932708 Homo sapiens Coiled-coil domain-containing protein 86 Proteins 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- LELOWRISYMNNSU-UHFFFAOYSA-N hydrogen cyanide Chemical compound N#C LELOWRISYMNNSU-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010909 process residue Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 듀얼다마신공정에서 비아콘택홀을 형성하고, 상기 비아콘택홀을 도전층으로 매립한 다음, 전면식각한 후, 상부 금속배선으로 예정되는 부분의 절연막을 식각하여 트렌치를 형성할 때 상기 비아콘택홀에 매립되어 있는 도전층을 돌출시킴으로써 식각잔류물에 의해 소자의 특성 및 신뢰성이 저하되는 것을 방지하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a via contact hole is formed in a dual damascene process, the via contact hole is filled with a conductive layer, and the surface is etched, and then an insulating film of a portion intended as an upper metal wiring. The present invention relates to a method of fabricating a semiconductor device in which a conductive layer embedded in the via contact hole is protruded when etching to form a trench, thereby preventing deterioration of characteristics and reliability of the device due to etching residues.
최근의 반도체장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체장치의 제조공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture : NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.
[ R = k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet ; DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하거나, 공정상의 방법으로는 노광마스크(photo mask)를 위상 반전 마스크(phase shift mask)를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer, 이하 CEL이라 함)방법이나 두 층의 감광막 사이에 SOG 등의 중간층을 개재시킨 삼층레지스트(tri layer resist, TLR) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a light source of deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 193 nm, to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.
또한 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings has a high integration of the device, and the size of the contact holes decreases, and the distance between the peripheral wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격유지를 위하여 마스크 정렬시 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration) 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.
그리고, 콘택홀 형성시 리소그래피(lithography)공정의 한계를 극복하기 위하여 자기 정렬 방법으로 콘택홀을 형성하는 자기정렬콘택(self aligned contact, 이하 SAC 라 함)기술이 개발되었다.In order to overcome the limitations of the lithography process in forming the contact holes, a self aligned contact (SAC) technology for forming contact holes by a self alignment method has been developed.
상기 SAC 방법은 식각장벽층으로 사용하는 물질에 따라 다결정실리콘층이나 질화막 또는 산화질화막 등을 사용하는 것으로 나눌 수 있으며, 가장 유망한 것으로 질화막을 식각방어막으로 사용하는 방법이 있다.The SAC method may be divided into a polysilicon layer, a nitride film, or an oxynitride film according to the material used as the etch barrier layer, and the most promising method is to use a nitride film as an etch barrier.
도시되어 있지는 않으나, 종래 반도체소자의 SAC 제조방법에 관하여 살펴보면 다음과 같다.Although not shown, the SAC manufacturing method of the conventional semiconductor device will be described as follows.
먼저, 반도체기판 상에 소정의 하부구조물, 예를 들어 소자분리 절연막과 게이트 절연막, 마스크 산화막 패턴과 중첩되어 있는 게이트 전극 및 소오스/드레인영역 등의 모스 전계효과 트랜지스터(MOS field effect transistor : 이하 MOS FET 라 함) 등을 형성한 후, 상기 구조의 전표면에 식각방지막과 산화막 재질의 층간절연막을 순차적으로 형성한다.First, a MOS field effect transistor (MOS FET) such as a gate electrode and a source / drain region overlapping a predetermined substructure, for example, a device isolation insulating film, a gate insulating film, and a mask oxide film pattern on a semiconductor substrate. And the like, and then sequentially form an etch stop film and an interlayer insulating film made of an oxide film on the entire surface of the structure.
그 다음, 상기 반도체기판에서 저장전극이나 비트라인 등의 콘택으로 예정되어 있는 부분 상의 층간절연막을 노출시키는 감광막 패턴을 형성한 후, 상기 감광막 패턴에 의해 노출되어 있는 층간절연막을 건식식각하여 식각방지막을 노출시키고, 다시 식각방지막을 식각하여 콘택홀을 형성한다.Next, a photoresist pattern is formed on the semiconductor substrate to expose an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact such as a storage electrode or a bit line. Then, the interlayer insulating film exposed by the photosensitive film pattern is dry-etched to form an etching prevention film. It exposes and etches an etch stop layer again, and forms a contact hole.
상기에서 식각방지막을 다결정실리콘으로 사용하는 경우, 이는 다시 식각방지막을 전면에 형성하는 방법과 콘택홀이 형성될 지역에만 다결정실리콘층 패드를 형성하는 방법으로 나누어지는데, 이러한 다결정실리콘 SAC 방법은 산화막과는 다른 식각기구를 가지는 다결정실리콘을 식각방지막으로 사용하므로 산화막과는 높은 식각선택비차를 얻을 수 있으나, 전면 증착 방법은 콘택홀간의 절연 신뢰성이 떨어지고, 패드를 형성하는 방법은 콘택 패드와 실리콘기판간의 오정렬 발생시 기판에 손상이 발생되는데, 이를 방지하기 위하여 스페이서 또는 폴리머를 사용하여 콘택 패드를 확장시키는 방법이 제시되고 있으나, 이 역시 0.18㎛ 이하의 디자인룰을 실현할 수 없는 문제점이 있다.When the etch barrier is used as polysilicon, it is divided into a method of forming an etch barrier on the front surface and a method of forming a polysilicon layer pad only in a region where a contact hole is to be formed. Such a polysilicon SAC method is characterized in that Since polycrystalline silicon having different etching mechanisms is used as an etch stopper, it is possible to obtain a high etching selectivity difference from an oxide film. However, in the case of the front deposition method, the insulation reliability between contact holes is inferior, and the pad forming method is used between the contact pad and the silicon substrate. When misalignment occurs, damage occurs to the substrate. In order to prevent this, a method of expanding a contact pad using a spacer or a polymer has been proposed, but this also has a problem in that a design rule of 0.18 μm or less can not be realized.
상기와 같은 문제점을 해결하기 위하여 제시되고있는 것이 질화막을 식각방지막으로 사용하는 SAC방법이다. 이 방법은 층간절연막과 식각방지막간의 식각선택비차가 5 : 1 이상으로 큰 조건에서 건식식각하여 질화막을 제거하여 콘택홀을 형성하는데, 상기 식각공정은 식각선택비를 증가시키기 위하여 다량의 폴리머를 발생시키는 C-H-F계 가스나 수소를 포함하는 가스를 불활성 가스와 혼합하여 사용한다.In order to solve the above problems, the SAC method using a nitride film as an etch stop layer is proposed. In this method, dry etching is performed under the condition that the etching selectivity difference between the interlayer insulating film and the etching prevention film is greater than 5: 1 to remove the nitride film to form a contact hole, and the etching process generates a large amount of polymer to increase the etching selectivity. CHF-based gas or hydrogen-containing gas is mixed with an inert gas.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도로서, 듀얼 다마신공정의 예이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, which is an example of a dual damascene process.
먼저, 소정의 하부구조물, 예를들어 소자분리 절연막(도시안됨)과 MOS FET(도시안됨) 및 캐패시터(도시안됨) 등이 형성되어 있는 반도체기판(11) 상부에 제1절연막(12)을 형성하고, 상기 제1절연막(12) 상부에 제1금속배선(13)을 형성한 후, 상기 구조의 전표면에 제2절연막(14)과 식각방지용 제3절연막(15)을 형성하고, 상기 제3절연막(15) 상에 제4절연막(16)을 형성한다.First, a first insulating layer 12 is formed on a semiconductor substrate 11 on which a predetermined substructure, for example, an isolation layer (not shown), a MOS FET (not shown), and a capacitor (not shown) is formed. After the first metal wiring 13 is formed on the first insulating film 12, the second insulating film 14 and the third insulating film 15 for preventing etching are formed on the entire surface of the structure. The fourth insulating film 16 is formed on the third insulating film 15.
다음, 상기 제4절연막(16) 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막 패턴(17)을 형성한다. 여기서, 상기 제2 및 제4절연막(14, 16)은 산화막 재질이고 상기 제3절연막(15)은 질화막재질이다. (도 1a참조)Next, a first photoresist layer pattern 17 is formed on the fourth insulating layer 16 to expose a portion to be via contact. Here, the second and fourth insulating layers 14 and 16 are made of an oxide film and the third insulating layer 15 is made of a nitride film. (See FIG. 1A)
그 다음, 상기 제1감광막 패턴(17)을 식각마스크로 사용하여 상기 제4절연막(16), 제3절연막(15) 및 제2절연막(14)을 식각하여 비아콘택홀을 형성한 후, 상기 제1감광막 패턴(17)을 제거한다.Next, the via contact hole is formed by etching the fourth insulating layer 16, the third insulating layer 15, and the second insulating layer 14 using the first photoresist layer pattern 17 as an etching mask. The first photoresist pattern 17 is removed.
그리고, 전체표면 상부에 제2감광막(18)을 도포한 후, 제2금속배선 및 비아콘택으로 예정되는 부분을 선택적으로 노광 및 현상하여 제2감광막(18) 패턴을 형성한다. (도 1b, 도 1c참조)After the second photoresist film 18 is applied over the entire surface, the second photoresist film 18 pattern is formed by selectively exposing and developing a portion of the second metal wiring and via contact. (See FIG. 1B, FIG. 1C)
다음, 상기 제2감광막(18) 패턴을 식각마스크로 사용하여 상기 제4절연막(16)을 식각한다. 이때, 상기 비아콘택홀을 메우고 있는 막대형상의 제2감광막(18)의 측벽에 상기 제4절연막(16)의 식각공정시 발생한 식각잔류물(19)이 적층된다. (도 1d참조)Next, the fourth insulating layer 16 is etched using the second photoresist layer 18 as an etch mask. At this time, the etching residues 19 generated during the etching process of the fourth insulating layer 16 are stacked on the sidewalls of the rod-shaped second photosensitive layer 18 filling the via contact holes. (See FIG. 1D)
그 후, 도시되어 있지는 않지만 상기 제2감광막(18) 패턴을 제거하고 상기 금속층을 형성한 다음, 화학적 기계적 연마(chemical mechanical polishing, CMP) 또는 전면식각하여 상기 제1금속배선(13)과 접속되는 제2금속배선을 형성한다.Subsequently, although not shown, the second photoresist layer 18 is removed, the metal layer is formed, and then the first metal wiring 13 is connected by chemical mechanical polishing (CMP) or full surface etching. A second metal wiring is formed.
상기와 같은 종래기술에 따른 반도체소자의 제조방법은, 일차로 비아콘택홀을 형성하고, 이단계에서 상부 금속배선이 형성될 트렌치를 형성하기 위한 감광막 패터닝 및 절연막 식각공정시 상기 비아콘택홀을 메우는 기둥 형상의 감광막의 측벽에 산화막 잔류물이 남게 되어 후속 금속배선 공정에서 상기 트렌치를 금속물질이 원활하게 매립하지 못하여 배선이 단선되거나, 산화막 잔류물이 공정 상의 파티클 소오스가 되어 공정 수율 및 소자 동작의 신뢰성을 저하시키는 문제점이 있다.In the method of manufacturing a semiconductor device according to the related art as described above, first, the via contact hole is formed, and in this step, the via contact hole is filled in the photoresist patterning and insulating layer etching process for forming the trench in which the upper metal wiring is to be formed. Oxide residues remain on the sidewalls of the column-shaped photoresist, which leads to disconnection of the trench due to the inability to smoothly fill the trenches in the subsequent metallization process, or the oxide residues become the particle sources in the process resulting in process yield and device operation. There is a problem of lowering reliability.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 듀얼 다마신공정에서 비아콘택홀을 도전층으로 매립하고, 전면식각한 후 상부 금속배선으로 예정되는 부분 상의 절연막의 식각공정시 상기 도전층이 비아콘택홀에서 돌출되도록 형성하여 산화막 잔류물이 발생하여 식각잔류물에 의한 금속배선의 단선이나 저항의 증가를 방지하고, 잔류물이 파티클 소스가 되는 것을 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, in the dual damascene process to fill the via contact hole with a conductive layer, and after etching the entire surface of the insulating layer on the portion intended to be the upper metal wiring after etching the conductive layer via Formed to protrude from contact hole, oxide film residue is generated to prevent disconnection or increase of resistance of metal wiring by etch residue, and to prevent process residue from becoming particle source to improve process yield and device operation reliability. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2c 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 3 은 본 발명의 제1실시예에 따른 반도체소자의 제조방법에서 식각가스의 함유량에 따른 다결정실리콘층의 식각선택비 변화를 도시한 그래프도.3 is a graph showing the change in etching selectivity of the polysilicon layer according to the content of the etching gas in the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
도 4a 내지 도 4d 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도.4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11, 21, 31 : 반도체기판 12, 22, 32 : 제1절연막11, 21, 31: semiconductor substrate 12, 22, 32: first insulating film
13, 23, 33 : 제1금속배선 14, 24, 34 : 제2절연막13, 23, 33: first metal wiring 14, 24, 34: second insulating film
15, 25, 35 : 제3절연막 16, 26, 36 : 제4절연막15, 25, 35: third insulating film 16, 26, 36: fourth insulating film
17, 37 : 제1감광막 패턴 18, 40 : 제2감광막17, 37: First photosensitive film pattern 18, 40: Second photosensitive film
19 : 식각잔류물 27 : 다결정실리콘층19: etching residue 27: polycrystalline silicon layer
28 : 감광막 패턴 29, 41 : 트렌치28: photoresist pattern 29, 41: trench
38 : 비아콘택홀 39 : 금속층38: via contact hole 39: metal layer
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 제1절연막을 형성하는 공정과,Forming a first insulating film on the semiconductor substrate on which a predetermined lower structure is formed;
상기 제1절연막 상부에 제1금속배선을 형성하는 공정과,Forming a first metal wiring on the first insulating layer;
상기 구조의 전표면에 제2절연막, 식각방지막 및 제3절연막의 적층구조를 형성하는 공정과,Forming a laminated structure of a second insulating film, an etch stop film and a third insulating film on the entire surface of the structure;
상기 제3절연막 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막 패턴을 형성하는 공정과,Forming a first photoresist pattern on the third insulating layer, the first photoresist layer pattern exposing a portion intended to be a via contact;
상기 제1감광막 패턴을 식각마스크로 사용하여 상기 적층구조를 식각하여 비아콘택홀을 형성하고, 상기 제1감광막 패턴을 제거하는 공정과,Etching the layered structure using the first photoresist pattern as an etch mask to form via contact holes, and removing the first photoresist pattern;
전체표면 상부에 상기 비아콘택홀을 매립하는 도전층을 형성하는 공정과,Forming a conductive layer filling the via contact hole on the entire surface;
상기 도전층을 전면식각하는 공정과,Etching the entire conductive layer;
전체표면 상부에 비아콘택홀 및 제2금속배선으로 예정되는 부분을 노출시키는 제2감광막 패턴을 형성하는 공정과,Forming a second photoresist layer pattern on the entire surface to expose portions of the via contact hole and the second metal wiring;
상기 제2감광막 패턴을 식각마스크로 사용하여 상기 제3절연막을 식각하여 상기 도전층의 상부가 돌출되도록 형성하고, 제2금속배선이 형성될 트렌치를 형성하는 공정과,Etching the third insulating layer by using the second photoresist pattern as an etching mask to form an upper portion of the conductive layer, and forming a trench in which a second metal wiring is to be formed;
상기 제2감광막 패턴을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the second photoresist pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
먼저, 소정의 하부구조물, 예를들어 소자분리 절연막(도시안됨)과 MOS FET 및 캐패시터(도시안됨) 등이 형성되어 있는 반도체기판(21) 상부에 제1절연막(22)을 형성하고, 상기 제1절연막(22) 상부에 제1금속배선(23)을 형성한 후, 전체표면 상부에 산화막을 사용하여 제2절연막(24)을 형성한다.First, a first insulating layer 22 is formed on a semiconductor substrate 21 on which a predetermined substructure, for example, an isolation layer (not shown), a MOS FET, a capacitor (not shown), and the like are formed. After the first metal wiring 23 is formed on the first insulating film 22, the second insulating film 24 is formed on the entire surface by using an oxide film.
그 다음, 상기 제2절연막(24) 상부에 식각방지막으로 사용되는 제3절연막(25)을 형성한다. 상기 제3절연막(25)은 상기 제2절연막(24)과 식각선택비차이를 갖는 SiON, Si3N4등의 질화막 계열의 박막을 사용하여 형성한다.Next, a third insulating layer 25 used as an etch stop layer is formed on the second insulating layer 24. The third insulating layer 25 is formed using a nitride film-based thin film such as SiON or Si 3 N 4 having an etching selectivity difference from the second insulating layer 24.
다음, 상기 제3절연막(25) 상부에 제4절연막(26)을 형성하고, 비아콘택으로 예정되는 부분을 노출시키는 비아콘택 마스크를 식각마스크로 사용하여 상기 제4절연막(26), 제3절연막(25) 및 제2절연막(24)을 식각하여 비아콘택홀을 형성한다.Next, a fourth insulating layer 26 is formed on the third insulating layer 25, and a fourth contact layer 26 and a third insulating layer are formed by using a via contact mask that exposes a portion intended as a via contact as an etching mask. (25) and the second insulating layer 24 are etched to form via contact holes.
그 다음, 전체표면 상부에 상기 비아콘택홀이 매립되도록 다결정실리콘층(27)을 형성한다. 상기 다결정실리콘층(27)은 화학기상증착(chemical vapor deposition, 이하 CVD 라 함) 등을 사용하여 형성한다. (도 2a참조)Next, the polysilicon layer 27 is formed to fill the via contact hole on the entire surface. The polysilicon layer 27 is formed using chemical vapor deposition (hereinafter referred to as CVD) or the like. (See Figure 2A)
다음, 상기 다결정실리콘층(27)을 전면식각 또는 CMP공정으로 제거하여 막대형상의 비아콘택을 형성한다. 이때, 상기 전면식각공정은 건식식각방법으로 알.아이.이.(reactive ion etching, RIE), 엠.이.알.아이.이.(MERIE), 이.씨.알.(electron cyclon resonance, ECR) 또는 티.씨.피.(transformed coupling plasma, TCP) 등의 식각장비를 사용하여 실시한다. 그리고, 상기 TCP식각장비를 사용하는 경우 100 ∼ 500W의 탑파워(top power)와 5 ∼ 200W의 바텀파워(bottom power)를 인가하고, 10 ∼ 150sccm의 Cl2가스와 10 ∼ 100sccm의 BCl2가스를 포함하는 혼합가스를 사용하고, 그 이외에 Ar, N2또는 HBr 가스를 포함시켜 식각공정을 실시한다.Next, the polysilicon layer 27 is removed by an entire surface etching or CMP process to form a rod-shaped via contact. In this case, the front etching process is a method of dry etching by R. I. (reactive ion etching, RIE), M. R. I. E. (MERIE), E. C. (electron cyclon resonance, ECR) or etch equipment such as transformed coupling plasma (TCP). In the case of using the TCP etching equipment, a top power of 100 to 500 W and a bottom power of 5 to 200 W are applied, and a Cl 2 gas of 10 to 150 sccm and a BCl 2 gas of 10 to 100 sccm are applied. Using a mixed gas containing, in addition to the Ar, N 2 or HBr gas to perform the etching process.
그 다음, 전체표면 상부에 상기 비아콘택 및 제2금속배선으로 예정되는 부분을 노출시키는 감광막 패턴(28)을 형성한다. (도 2b참조)Next, a photoresist pattern 28 is formed on the entire surface to expose a portion of the via contact and the second metal wiring. (See Figure 2b)
그리고, 상기 감광막 패턴(28)을 식각마스크로 사용하여 상기 제4절연막(26)을 식각하여 상기 막대형상의 다결정실리콘(27)이 돌출되도록 형성하고, 제2금속배선이 형성될 트렌치(29)를 형성한다. 이때, 상기 식각공정은 불소가스를 주식각가스로 사용하되, O2가스를 전체 식각가스의 15 ∼ 40%를 첨가하여 실시한다. 상기 O2가스를 첨가하는 것은을 상기 제4절연막과 다결정실리콘층(27)의 식각선택비를 2 : 1 ∼ 2 : 0.1로 조절하기 위한 것이다. (도 2c참조)The fourth insulating layer 26 is etched using the photoresist pattern 28 as an etching mask to form the rod-shaped polysilicon 27 to protrude, and the trench 29 in which the second metal wiring is to be formed. To form. In this case, the etching process is carried out by using fluorine gas as the stock etching gas, adding 15 to 40% of the total etching gas O 2 gas. The addition of the O 2 gas is to adjust the etching selectivity of the fourth insulating film and the polysilicon layer 27 to 2: 1 to 2: 0.1. (See FIG. 2C)
참고로, 도 3 은 상기 O2가스의 함유량에 따른 식각선택비의 변화를 도시하는 그래프도로서, 상기 O2가스의 함유량이 증가할수록 다결정실리콘층(27)의 식각정도가 상기 제4절연막(26)보다 빨라져 식각선택비가 감소하는 것을 나타낸다.For reference, FIG. 3 is a graph showing a change in etching selectivity according to the content of the O 2 gas, and as the content of the O 2 gas increases, the degree of etching of the polysilicon layer 27 is increased by the fourth insulating film ( Faster than 26), indicating that the etching selectivity is reduced.
그 후, 상기 제2감광막 패턴(28)을 제거하고, 상기 트렌치(29)를 매립하는 동시에 상기 다결정실리콘층(27)과 접속되는 금속층을 형성한 다음, CMP공정을 실시하여 제2금속배선을 형성한다.Thereafter, the second photoresist layer pattern 28 is removed, the trench 29 is buried and a metal layer connected to the polysilicon layer 27 is formed. Then, a CMP process is performed to form the second metal wiring. Form.
한편, 본 발명의 제2실시예에 대하여 살펴보면 다음과 같다.Meanwhile, the second embodiment of the present invention will be described.
도 4a 내지 도 4d 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
먼저, 소정의 하부구조물, 예를들어 소자분리 절연막(도시안됨)과 MOS FET 및 캐패시터(도시안됨) 등이 형성되어 있는 반도체기판(31) 상부에 제1절연막(32)을 형성하고, 상기 제1절연막(32) 상부에 제1금속배선(33)을 형성한 후, 전체표면 상부에 산화막을 사용하여 제2절연막(34)을 형성한다.First, a first insulating layer 32 is formed on a semiconductor substrate 31 on which a predetermined substructure, for example, an isolation layer (not shown), a MOS FET, a capacitor (not shown), and the like are formed. After the first metal wiring 33 is formed on the first insulating film 32, the second insulating film 34 is formed on the entire surface by using an oxide film.
그 다음, 상기 제2절연막(34) 상부에 식각방지막으로 사용되는 제3절연막(35)을 형성한다. 상기 제3절연막(35)은 상기 제2절연막(34)과 식각선택비차이를 갖는 SiON, Si3N4등의 질화막 계열의 박막을 사용하여 형성한다.Next, a third insulating layer 35 used as an etch stop layer is formed on the second insulating layer 34. The third insulating layer 35 is formed using a nitride film-based thin film such as SiON or Si 3 N 4 having an etching selectivity difference from the second insulating layer 34.
다음, 상기 제3절연막(35) 상부에 제4절연막(36)을 형성하고, 상기 제4절연막(36) 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막 패턴(37)을 형성한 다음, 상기 제1감광막 패턴(37)을 식각마스크로 사용하여 상기 제4절연막(36), 제3절연막(35) 및 제2절연막(34)을 식각하여 비아콘택홀(38)을 형성한다. 이때, 상기 식각공정은 불소가스를 주식각가스로 사용하되 CF4또는 CHF3등의 가스로 MxP, TCP, DRM, ECR, RIE 등의 식각장비를 사용하여 실시한다. (도 4a참조)Next, a fourth insulating layer 36 is formed on the third insulating layer 35, and a first photoresist layer pattern 37 is formed on the fourth insulating layer 36 to expose a portion intended to be a via contact. The via contact hole 38 is formed by etching the fourth insulating layer 36, the third insulating layer 35, and the second insulating layer 34 by using the first photoresist layer pattern 37 as an etching mask. In this case, the etching process is performed using fluorine gas as a stock corner gas, but using etching equipment such as MxP, TCP, DRM, ECR, RIE as a gas such as CF 4 or CHF 3 . (See Figure 4a)
그 다음, 상기 제1감광막 패턴(37)을 제거하고, 전체표면 상부에 상기 비아콘택홀(38)이 매립되도록 금속층(39)을 형성한다. 상기 금속층(39)은 Al, W 또는 Cu등을 사용하여 형성하되, 상기 금속층(39)을 형성하기 전에 Ti, TiN 또는 Ti/TiN 적층구조의 접착층(도시안됨)을 형성하여 상기 비아콘택홀(38)에 금속층이 일정한 두께로 형성되게 한다.Next, the first photoresist pattern 37 is removed, and a metal layer 39 is formed to fill the via contact hole 38 over the entire surface. The metal layer 39 is formed using Al, W, or Cu, but before forming the metal layer 39, an adhesive layer (not shown) having a Ti, TiN, or Ti / TiN laminated structure is formed to form the via contact hole ( 38) allows the metal layer to be formed to a certain thickness.
다음, 상기 금속층(39)을 플라즈마를 이용한 건식전면식각 또는 CMP공정으로 제거하여 막대형상의 비아콘택을 형성한다. (도 4b참조)Next, the metal layer 39 is removed by dry front etching using a plasma or a CMP process to form a rod-shaped via contact. (See Figure 4b)
그 다음, 전체표면 상부에 상기 비아콘택 및 제2금속배선으로 예정되는 부분을 노출시키는 제2감광막 패턴(40)을 형성한다. (도 4c참조)Next, a second photoresist pattern 40 is formed on the entire surface to expose portions of the via contact and the second metal wiring. (See FIG. 4C)
그리고, 상기 제2감광막 패턴(40)을 식각마스크로 불소가스를 주식각가스로 사용하여 상기 제4절연막(36)을 식각하여 상기 금속층(39)이 돌출되도록 하고, 제2금속배선이 형성될 트렌치(41)를 형성한다. 이때, 상기 제4절연막(36)과 금속층(39)은 10 : 1 ∼ 10 : 0.1의 식각선택비를 갖기 때문에 상기 금속층(39)은 거의 식각되지 않는다. (도 4d참조)The fourth insulating layer 36 is etched by using the second photoresist pattern 40 as an etch mask, and fluorine gas is used as a stock angular gas, so that the metal layer 39 protrudes and a second metal wiring is formed. The trench 41 is formed. In this case, since the fourth insulating layer 36 and the metal layer 39 have an etching selectivity of 10: 1 to 10: 0.1, the metal layer 39 is hardly etched. (See FIG. 4D)
그 후, 상기 제2감광막 패턴(33)을 제거하고, 상기 비아콘택홀 및 트렌치(32)를 매립하여 상기 제1금속배선(23)과 접속되는 제2금속배선용 금속층을 형성한 후, CMP 공정을 실시하여 제2금속배선을 형성한다. 이때, 상기 제2금속배선용 금속층은 Al, Cu 등의 금속을 사용하여 형성하고, 상기 제2금속배선용 금속층을 형성하기 전에 Ti, TiN 또는 Ti/TiN 적층구조의 웨팅층을 형성하여 상기 제2금속배선용 금속층이 일정한 두께로 형성되도록 한다.Thereafter, the second photoresist layer pattern 33 is removed, the via contact hole and the trench 32 are buried to form a second metal wiring metal layer connected to the first metal wiring 23, and then a CMP process. To form a second metal wiring. In this case, the second metal wiring metal layer is formed using a metal such as Al, Cu, and before forming the second metal wiring metal layer, a wetting layer of Ti, TiN or Ti / TiN laminated structure is formed to form the second metal. The metal layer for wiring is formed to have a constant thickness.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 상부 금속배선을 산화막에 형성된 트렌치에 형성하는 듀얼 다마신 공정에서 하부 금속배선을 형성한 다음, 상기 하부 금속배선을 노출시키는 비아콘택홀을 형성하고, 상기 비아콘택홀을 매립하는 도전층을 형성한 후, 상부 금속배선 및 상기 비아콘택홀을 노출시키는 감광막 패턴을 형성한 다음, 상기 감광막 패턴을 식각마스크로 상기 도전층 및 절연막을 식각하여 상기 도전층을 상기 비아콘택홀로부터 소정 두께 돌출되도록 형성함으로써 별도로 상기 비아콘택홀 내부에 감광막을 제거하는 공정이 필요없고, 공정의 파티클 소오스가 발생하는 것을 방지하여 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, in the dual damascene process of forming an upper metal interconnection in a trench formed in an oxide layer, a via contact hole exposing the lower metal interconnection after forming a lower metal interconnection After forming a conductive layer for filling the via contact hole, and then forming a photosensitive film pattern for exposing the upper metal wiring and the via contact hole, and then etching the conductive layer and the insulating film using the photosensitive film pattern as an etching mask By forming the conductive layer so as to protrude a predetermined thickness from the via contact hole, there is no need to separately remove the photoresist film inside the via contact hole, and to prevent the occurrence of particle source in the process, thereby improving process yield and device operation reliability. There is an advantage that can be improved.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061916A KR20000045358A (en) | 1998-12-30 | 1998-12-30 | Fabrication method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061916A KR20000045358A (en) | 1998-12-30 | 1998-12-30 | Fabrication method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000045358A true KR20000045358A (en) | 2000-07-15 |
Family
ID=19568612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980061916A KR20000045358A (en) | 1998-12-30 | 1998-12-30 | Fabrication method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000045358A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100688760B1 (en) * | 2002-12-30 | 2007-02-28 | 동부일렉트로닉스 주식회사 | Method for manufacturing lines of semiconductor device |
| KR100815186B1 (en) * | 2006-09-11 | 2008-03-19 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device with protrusion type w plug |
-
1998
- 1998-12-30 KR KR1019980061916A patent/KR20000045358A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100688760B1 (en) * | 2002-12-30 | 2007-02-28 | 동부일렉트로닉스 주식회사 | Method for manufacturing lines of semiconductor device |
| KR100815186B1 (en) * | 2006-09-11 | 2008-03-19 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device with protrusion type w plug |
| US7615494B2 (en) | 2006-09-11 | 2009-11-10 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device including plug |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100474546B1 (en) | Fabricating method for semiconductor device | |
| US6372575B1 (en) | Method for fabricating capacitor of dram using self-aligned contact etching technology | |
| KR100535030B1 (en) | Fabricating method for semiconductor device | |
| US6528418B1 (en) | Manufacturing method for semiconductor device | |
| KR100696760B1 (en) | Manufacturing method for semiconductor device | |
| KR100350764B1 (en) | Manufacturing method of semiconductor device | |
| KR20060114431A (en) | Manufacturing method for semiconductor device | |
| KR100420413B1 (en) | Manufacturing method for semiconductor device | |
| KR100546144B1 (en) | Manufacturing method of semiconductor device | |
| KR100583103B1 (en) | Method for fabricating of semiconductor device | |
| KR100324023B1 (en) | Manufacturing method of semiconductor device | |
| KR20010063763A (en) | Manufacturing method for semiconductor device | |
| KR20000045358A (en) | Fabrication method of semiconductor device | |
| KR100307558B1 (en) | Manufacturing method of semiconductor device | |
| KR100307560B1 (en) | Manufacturing method of semiconductor device | |
| KR20060113282A (en) | Manufacturing method for semiconductor device | |
| KR20060114446A (en) | Manufacturing method for semiconductor device | |
| KR100333548B1 (en) | Fabricating method for semiconductor device | |
| KR100861188B1 (en) | Manufacturing method for semiconductor device | |
| KR100527568B1 (en) | Manufacturing method for semiconductor device | |
| KR100527531B1 (en) | Manufacturing method for semiconductor device | |
| KR100304440B1 (en) | Manufacturing method of semiconductor device | |
| KR20000043205A (en) | Method for forming contact hole of semiconductor device | |
| KR20000045357A (en) | Method for fabricating semiconductor device | |
| KR20010063856A (en) | Fabricating method for semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |