KR100696760B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, wherein the first metal wiring is formed in a dual damascene process and the first metal wiring is formed in an etching process for forming a via contact hole exposing the first metal wiring. After removing the etch stop layer formed on the metal wiring, the trench is formed to form the second metal wiring, thereby preventing deformation of the etch profile of the via contact hole and the trench, and improving throughput. It is a technique to improve the yield and reliability.

Description

Manufacturing method for semiconductor device

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

11, 101: lower insulating film 13, 103: first metal wiring

15, 105: first etching prevention film 17, 107: first interlayer insulating film

19, 109: Second etching prevention film 21, 111: Second interlayer insulating film

23, 113: third nitride film 25, 115: first oil-based prevention film

27, 117: first photoresist pattern 29, 119: via contact hole

31, 121: second oil-based anti-fogging film 33, 123: second photoresist film pattern

35, 125: trench

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, by forming a trench for forming a second metal interconnection after removing an etch barrier layer formed on an upper portion of a first metal interconnection during a via contact hole formation process in a dual damascene process. The present invention relates to a method for manufacturing a semiconductor device for improving the process yield and reliability of the device.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

R = k * λ / NA

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a light source of deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 193 nm, to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate injection methods have been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a high integration of the device, and the size of the contact holes decreases, and the distance between the peripheral wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes have misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.

In order to overcome the limitations of the lithography process in forming the contact holes, a self aligned contact (SAC) technology for forming contact holes by a self alignment method has been developed.

The SAC method may be classified into a polysilicon layer, a nitride film, an oxynitride film, or the like according to a material used as an etching prevention film, and the most promising method is a method using a nitride film.

Although not shown, the SAC manufacturing method of the conventional semiconductor device will be described as follows.

First, a MOS field effect transistor (MOS FET) such as a gate electrode and a source / drain region overlapping a predetermined substructure on a semiconductor substrate, for example, a device isolation insulating film, a gate insulating film, and a mask oxide film pattern. And the like, and then sequentially form an etch stop film and an interlayer insulating film made of an oxide film on the entire surface of the structure.

Next, a photoresist pattern is formed on the semiconductor substrate to expose an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact such as a storage electrode or a bit line. Then, the interlayer insulating film exposed by the photosensitive film pattern is dry-etched to form an etch stop layer. It exposes and etches an etch stop layer again, and forms a contact hole.

When the etch barrier is used as polysilicon, it is divided into a method of forming an etch barrier on the front surface and a method of forming a polysilicon layer pad only in a region where a contact hole is to be formed. Such a polysilicon SAC method is characterized in that Since polycrystalline silicon having different etching mechanisms is used as an etch stopper, it is possible to obtain a high etching selectivity difference from an oxide film. However, in the case of the front deposition method, the insulation reliability between contact holes is inferior, and the pad forming method is used between the contact pad and silicon substrate. When misalignment occurs, damage occurs to the substrate. In order to prevent this, a method of expanding a contact pad using a spacer or a polymer has been proposed, but this also has a problem in that a design rule of 0.18 μm or less can not be realized.

In order to solve the above problems, the SAC method using a nitride film as an etch stop layer is proposed. In this method, dry etching is performed under the condition that the etching selectivity difference between the interlayer insulating film and the etching prevention film is greater than 5: 1 to remove the nitride film to form a contact hole, and the etching process generates a large amount of polymer to increase the etching selectivity. CHF-based gas or hydrogen-containing gas is mixed with an inert gas.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

First, a lower insulating layer 11 is formed on a semiconductor substrate on which a predetermined lower structure, for example, an isolation layer (not shown), a MOS FET (not shown), a capacitor (not shown), and the like are formed.

Next, a first metal wiring 13 is formed on the lower insulating layer 11.

Next, the first etch stop layer 15, the first interlayer insulating layer 17, the second etch stop layer 19, the second interlayer insulating layer 21, the third etch stop layer 23, and the first organic layer on the entire surface. A laminated structure of the antireflection film 25 is formed. In this case, the first etch barrier 15, the second etch barrier 19 and the third etch barrier 23 is formed of a nitride film, the first etch barrier 15 and the third etch barrier 23 is 400 It is formed to a thickness of ~ 500 kPa, and the second etching prevention film 19 is formed to a thickness of 900 ~ 1100 kPa. The first interlayer insulating film 17 and the second interlayer insulating film 21 are formed to have a thickness of 4000 to 6000 GPa using an oxide film, and the first oil barrier film 25 is 500 to 700 GPa thick.

Next, a first photoresist layer pattern 27 is formed on the first oil barrier layer 25 to expose a portion of the via contact hole. The first photoresist pattern 27 is formed to a thickness of 7000 to 8000 Å using a DUV photosensitive film. (See Figure 1A)

Subsequently, the first photoresist layer 25, the third etch barrier 23, the second interlayer dielectric 21, the second etch barrier 19 and the first photoresist layer 27 are etched using the etch mask. The first interlayer insulating layer 17 is sequentially etched to form the first oil-based anti-sagging film 25 pattern having the via contact hole 29, the third etching preventing film 23 pattern, the second interlayer insulating film 21 pattern, and the second interlayer insulating film 17. An etch stop layer 19 pattern and a first interlayer insulating layer 17 pattern are formed.

Next, the first photoresist layer pattern 27 and the first oil barrier layer 25 pattern are removed. Next, a cleaning process is performed using wet chemical such as ACT935, ACT970, ST250 or EKC640. (See FIG. 1B)

Next, the second oil-based anti-film 31 is formed to a thickness of 500 ~ 700Å over the entire surface. The second oil barrier layer 31 is also formed on the first etch barrier layer 15 exposed to the bottom of the via contact hole 29.

Next, a second photoresist layer pattern 33 is formed on the upper portion of the structure to expose a predetermined portion of the second metal wiring, and the second photoresist layer pattern 33 remains in the via contact hole 29 to be subsequently etched. The first metal wiring 13 is prevented from being damaged in the process. (See Figure 1C)

Next, the second photoresist layer 31, the third etch barrier 23 pattern, and the second interlayer insulating layer 21 on the pattern of the third etch barrier 23 are formed using the second photoresist layer pattern 33 as an etch mask. The trench is etched to form the trench 35 exposing the portion where the second metal wiring is to be formed.

Next, the second photoresist layer pattern 33 and the second oil barrier layer 31 are removed.

Then, an O ₂ plasma treatment is performed to remove fluorine generated in all processes.

Next, a cleaning process is performed using wet chemical such as ACT935, ACT970, ST250 or EKC640. (See FIG. 1D)

Next, a first etching prevention layer 15 at the bottom of the via contact hole 29 is removed by performing a front surface etching process to expose the first metal wiring 13. In this case, the second etch stop layer 19 and the third etch stop layer 23 pattern is also etched. (See Figure 1E)

Thereafter, although not shown, after forming a metal layer over the entire surface, the second metal is connected to the first metal wiring 13 by planarizing the metal layer by chemical mechanical polishing (CMP) or an entire surface etching process. Form the wiring.

In the method of manufacturing a semiconductor device according to the prior art as described above, the first metal wiring is formed during an etching process for removing the etch stop layer formed on the first metal wiring after forming the trench in which the second metal wiring is to be formed. The etching profile of the via contact hole and the trench may be damaged during the etching process because the etching rate of the etch barrier is slow, and the throughput of the through-put may be reduced.

In order to solve the above problems of the prior art, the first metal is removed by removing the etch stop layer on the first metal wiring during the etching process for forming the via contact hole in the dual damascene process using the Al film as the wiring material. The present invention provides a method of manufacturing a semiconductor device that prevents deformation of an etch profile of the via contact hole and the trench by exposing a trench to form a second metal wiring after exposing wiring, thereby improving characteristics and reliability of the semiconductor device. Its purpose is to.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

Forming a lower insulating film on the semiconductor substrate on which a predetermined lower structure is formed;

Forming a first metal wiring on the lower insulating layer;

Forming a stacked structure of a first etch stop layer, a first interlayer dielectric layer, a second etch barrier layer, a second interlayer dielectric layer, a third etch barrier layer, and a first anti-base layer on the first metal wiring;

Forming a first photoresist layer pattern exposing a portion intended as a via contact on the first oil-based anti-fog layer;

Forming a via contact hole exposing the first metal wiring by etching the layered structure using the first photoresist pattern as an etch mask;

Removing the first photoresist pattern and the first oil barrier film;

Forming a second oil-based anti-film on the upper portion of the third etch stop layer and the bottom of the via contact hole;

Forming a second photoresist pattern on the entire surface of the second photoresist layer, the second photoresist pattern being formed inside the via contact hole;

Forming a trench by etching the second oil barrier layer, the third etch barrier layer, and the second interlayer dielectric layer using the second photoresist pattern as an etch mask;

And removing the second photoresist layer pattern and the second oil barrier layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.                     

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, a lower insulating layer 101 is formed on a semiconductor substrate on which a predetermined lower structure, for example, an isolation layer (not shown), a MOS FET (not shown), a capacitor (not shown), and the like are formed.

Next, a first metal wiring 103 is formed on the lower insulating film 101.

Next, the first etch stopper film 105, the first interlayer insulating film 107, the second etch stopper film 109, the second interlayer insulating film 111, the third etch stopper film 113 and the first organic layer on the entire surface. A stack structure of the antireflection film 115 is formed.

The first etch stop layer 105, the second etch stop layer 109, and the third etch stop layer 113 form a nitride film having a thickness of 400 to 500 μm.

The first interlayer insulating film 107 and the second interlayer insulating film 111 form an oxide film with a thickness of 4000 to 6000 kV. In addition, the first interlayer insulating film 107 and the second interlayer insulating film 111 are C _x H _y O _z organic low dielectric materials such as BCB, Flare, SiLK, or SiOC: H film, SiOC film, SiOF film, and siloxane SOG. It may be formed of an inorganic low dielectric material such as a film, a silicate SOG film, an HSQ film, an MSQ film, a HOSP film, a LOSP film, or an FSG film. The third etch stop layer 113 may also be formed of the inorganic low dielectric material.

The first oil barrier film 115 is formed to a thickness of 500 ~ 700Å.

Next, a first photoresist layer pattern 117 is formed on the first oil barrier layer 115 to expose a predetermined portion of the via contact hole. The first photoresist pattern 117 is formed to a thickness of 7000 to 8000 Å using a DUV photoresist. (See Figure 2A)

Next, the first photoresist layer 115, the third etch barrier layer 113, the second interlayer dielectric layer 111, the second etch barrier layer 109, and the first photoresist layer pattern 117 are used as an etch mask. The first interlayer insulating film 107 and the first etch stop layer 107 are sequentially etched to form the first oil barrier layer 115 pattern including the via contact hole 119, the third etch stop layer 113 pattern, and the second layer. The insulating layer 111 pattern, the second etch stop layer 109 pattern, the first interlayer insulating layer 107 pattern, and the first etch stop layer 105 pattern are formed.

At this time, when the first interlayer insulating film 107 and the second interlayer insulating film 111 are organic low dielectric materials, the substrate is etched using C _x H _y or N ₂ / H ₂ gas as the stock corner gas, and the inorganic low dielectric layer The material is etched by a plasma dry etching process using any one selected from C _x F _y , CO, N ₂ , Ar, and a combination thereof. In addition, the first etch barrier 105 is removed by a plasma dry etching method using any one selected from CF ₄ , CHF ₃ , Ar, and a combination thereof, the bias power by using a low voltage of 100 ~ 300W Minimize damage to the metal wiring 103. In addition, when the first etch stop layer 105 is formed of a SiC film, it is removed by a plasma dry etching method using any one selected from CF ₄ , CH ₃ F, CO, Ar, and a combination thereof. This prevents deterioration of the surface characteristics of the inorganic low dielectric material by using a CO 3 gas instead of adding O ₂ gas and using a CH ₃ F gas having a high H component.

Next, the first photoresist film pattern 117 and the first oil barrier film pattern 115 are removed. (See Figure 2b)

Next, a second oil-based anti-morning film 121 is formed on the entire surface to a thickness of 500 to 700 mm 3. The second oil barrier layer 121 is also formed on the first metal wire 103 exposed to the bottom of the via contact hole 119. The second oil barrier layer 121 is also formed at the bottom of the via contact hole 119 to be used as an etch barrier during the subsequent etching process to prevent the first metal wiring 105 from being damaged.

Next, a second photoresist layer pattern 123 is formed on the structure to expose a predetermined portion of the second metal wiring, and the second photoresist layer pattern 123 remains in the via contact hole 119 to be subsequently etched. The first metal wiring 103 is prevented from being damaged in the process. (See Figure 2c)

Then, the second photoresist layer 121, the third etch barrier pattern 113, and the second interlayer dielectric layer pattern 111 are etched using the second photoresist layer pattern 123 as an etch mask. A trench 125 is formed that exposes the portion to be formed.

Next, the first metal wiring 103 is exposed by removing the second photoresist layer pattern 123 and the second oil barrier layer 121.

Next, a cleaning process is performed using wet chemical such as ACT935, ACT970, ST250 or EKC640. (See FIG. 2D)

Thereafter, although not shown, after forming a metal layer on the entire surface, the second metal is connected to the first metal wiring 103 by planarizing the metal layer by chemical mechanical polishing (CMP) or an entire surface etching process. Form the wiring.

As described above, in the method of manufacturing a semiconductor device according to the present invention, an etching process for forming a first metal wiring in a dual damascene process and forming a via contact hole exposing the first metal wiring is performed. After removing the etch stop layer formed on the upper first metal interconnection to form a trench for forming the second metal interconnection to prevent the deformation of the etch profile of the via contact hole and the trench, and improve the throughput, the process yield of the device And there is an advantage to improve the reliability.

Claims (14)

Forming a lower insulating film on the semiconductor substrate on which a predetermined lower structure is formed; Forming a first metal wiring on the lower insulating layer; Forming a stacked structure of a first etch stop layer, a first interlayer dielectric layer, a second etch barrier layer, a second interlayer dielectric layer, a third etch barrier layer, and a first anti-base layer on the first metal wiring; Forming a first photoresist layer pattern exposing a portion intended as a via contact on the first oil-based anti-fog layer; Forming a via contact hole exposing the first metal wiring by etching the layered structure using the first photoresist pattern as an etch mask; Removing the first photoresist pattern and the first oil barrier film; Forming a second oil-based anti-film on the upper portion of the third etch stop layer and the bottom of the via contact hole; Forming a second photoresist pattern on the entire surface of the second photoresist layer, the second photoresist pattern being formed inside the via contact hole; Forming a trench by etching the second oil barrier layer, the third etch barrier layer, and the second interlayer dielectric layer using the second photoresist pattern as an etch mask; And removing the second photoresist pattern and the second oil barrier film. The method of claim 1, And the first interlayer insulating film and the second interlayer insulating film are formed to have a thickness of 4000 to 6000 mV using an oxide film. The method of claim 1, And the first interlayer insulating film and the second interlayer insulating film are formed of an organic low dielectric material or an inorganic low dielectric material. The method of claim 3, wherein The organic low dielectric material is a manufacturing method of a semiconductor device, characterized in that any one selected from BCB, Flare, SiLK and combinations thereof. The method of claim 3, wherein The inorganic low dielectric material is any one selected from SiOC: H film, SiOC film, SiOF film, siloxane SOG film, silicate SOG film, HSQ film, MSQ film, HOSP film, LOSP film, FSG film and combinations thereof A method of manufacturing a semiconductor device. The method of claim 1, The first etch stop layer, the second etch stop layer and the third etch stop layer is a semiconductor device manufacturing method, characterized in that formed of a nitride film. The method of claim 1, The first etch stop layer is a semiconductor device manufacturing method, characterized in that formed of an inorganic low dielectric material. The method of claim 1, The first oil-based anti-freeze film and the second oil-based anti-freeze film is a manufacturing method of a semiconductor device, characterized in that formed in the thickness of 500 ~ 700Å. The method of claim 1, When the first interlayer dielectric layer and the second interlayer dielectric layer are formed of an organic low dielectric material, the semiconductor device may be etched by an etching process using C _x H _y or N ₂ / H ₂ gas as a stock corner gas. Manufacturing method. The method of claim 1, When the first interlayer dielectric layer and the second interlayer dielectric layer are formed of an inorganic low dielectric material, the first interlayer dielectric layer and the second interlayer dielectric layer are etched by a plasma dry etching process using any one selected from C _x F _y , CO, N ₂ , Ar, and a combination thereof. A method of manufacturing a semiconductor device. The method of claim 1, The first etch barrier layer is formed using any one selected from CF ₄ , CHF ₃ , Ar, and a combination thereof, and is etched by a plasma dry etching method applying a bias power of 100 to 300W. Manufacturing method. The method of claim 1, When the first etch stop layer is formed of a SiC film is a semiconductor device manufacturing method characterized in that the etching by plasma dry etching method using any one selected from CF ₄ , CH ₃ F, CO, Ar and combinations thereof. The method of claim 1, And removing the second photoresist layer pattern and the second oil-based anti-fogging layer and performing a cleaning process using a wet chemical. The method of claim 13, The wet chemical is a method of manufacturing a semiconductor device, characterized in that any one selected from ACT935, ACT970, ST250, EKC640 and combinations thereof.

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