KR20000045357A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20000045357A KR20000045357A KR1019980061915A KR19980061915A KR20000045357A KR 20000045357 A KR20000045357 A KR 20000045357A KR 1019980061915 A KR1019980061915 A KR 1019980061915A KR 19980061915 A KR19980061915 A KR 19980061915A KR 20000045357 A KR20000045357 A KR 20000045357A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 금속배선간 콘택인 비아콘택(via contact) 식각시 상부 금속배선이 들어갈 부분을 식각하여 홈을 형성하는 듀얼다마신(dual damascene) 공정에서 콘택홀 상부의 절연막이 날카롭게 형성되는 것을 방지하여 후속 금속층 형성시 콘택홀 내에 보이드(void)가 발생하는 것을 방지하고 그에 따른 공정수율 및 소자동작의 신뢰성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, a contact hole in a dual damascene process of forming a groove by etching a portion to which an upper metal wiring enters during a via contact, which is a contact between metal wirings. The present invention relates to a method of preventing an upper insulating layer from being sharply formed to prevent voids from occurring in a contact hole during subsequent metal layer formation, thereby improving process yield and reliability of device operation.
최근의 반도체장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체장치의 제조공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture : NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.
[ R = k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet ; DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하거나, 공정상의 방법으로는 노광마스크(photo mask)를 위상 반전 마스크(phase shift mask)를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer, 이하 CEL이라 함)방법이나 두 층의 감광막 사이에 SOG 등의 중간층을 개재시킨 삼층레지스트(tri layer resist, TLR) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a light source of deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 193 nm, to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.
또한 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings has a high integration of the device, and the size of the contact holes decreases, and the distance between the peripheral wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격유지를 위하여 마스크 정렬시 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration) 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.
그리고, 콘택홀 형성시 리소그래피(lithography)공정의 한계를 극복하기 위하여 자기 정렬 방법으로 콘택홀을 형성하는 자기정렬콘택(self aligned contact, 이하 SAC 라 함)기술이 개발되었다.In order to overcome the limitations of the lithography process in forming the contact holes, a self aligned contact (SAC) technology for forming contact holes by a self alignment method has been developed.
상기 SAC 방법은 식각장벽층으로 사용하는 물질에 따라 다결정실리콘층이나 질화막 또는 산화질화막 등을 사용하는 것으로 나눌 수 있으며, 가장 유망한 것으로 질화막을 식각방어막으로 사용하는 방법이 있다.The SAC method may be divided into a polysilicon layer, a nitride film, or an oxynitride film according to the material used as the etch barrier layer, and the most promising method is to use a nitride film as an etch barrier.
도시되어 있지는 않으나, 종래 반도체소자의 SAC 제조방법에 관하여 살펴보면 다음과 같다.Although not shown, the SAC manufacturing method of the conventional semiconductor device will be described as follows.
먼저, 반도체기판 상에 소정의 하부구조물, 예를 들어 소자분리 절연막과 게이트 절연막, 마스크 산화막 패턴과 중첩되어 있는 게이트 전극 및 소오스/드레인영역 등의 모스 전계효과 트랜지스터(MOS field effect transistor : 이하 MOS FET 라 함) 등을 형성한 후, 상기 구조의 전표면에 식각방지막과 산화막 재질의 층간절연막을 순차적으로 형성한다.First, a MOS field effect transistor (MOS FET) such as a gate electrode and a source / drain region overlapping a predetermined substructure, for example, a device isolation insulating film, a gate insulating film, and a mask oxide film pattern on a semiconductor substrate. And the like, and then sequentially form an etch stop film and an interlayer insulating film made of an oxide film on the entire surface of the structure.
그 다음, 상기 반도체기판에서 저장전극이나 비트라인 등의 콘택으로 예정되어 있는 부분 상의 층간절연막을 노출시키는 감광막 패턴을 형성한 후, 상기 감광막 패턴에 의해 노출되어 있는 층간절연막을 건식식각하여 식각방지막을 노출시키고, 다시 식각방지막을 식각하여 콘택홀을 형성한다.Next, a photoresist pattern is formed on the semiconductor substrate to expose an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact such as a storage electrode or a bit line. Then, the interlayer insulating film exposed by the photosensitive film pattern is dry-etched to form an etching prevention film. It exposes and etches an etch stop layer again, and forms a contact hole.
상기에서 식각방지막을 다결정실리콘으로 사용하는 경우, 이는 다시 식각방지막을 전면에 형성하는 방법과 콘택홀이 형성될 지역에만 다결정실리콘층 패드를 형성하는 방법으로 나누어지는데, 이러한 다결정실리콘 SAC 방법은 산화막과는 다른 식각기구를 가지는 다결정실리콘을 식각방지막으로 사용하므로 산화막과는 높은 식각선택비차를 얻을 수 있으나, 전면 증착 방법은 콘택홀간의 절연 신뢰성이 떨어지고, 패드를 형성하는 방법은 콘택 패드와 실리콘기판간의 오정렬 발생시 기판에 손상이 발생되는데, 이를 방지하기 위하여 스페이서를 형성하거나 폴리머를 사용하여 콘택 패드를 확장시키는 방법이 제시되고 있으나, 이 역시 0.18㎛ 이하의 디자인룰을 실현할 수 없는 문제점이 있다.When the etch barrier is used as polysilicon, it is divided into a method of forming an etch barrier on the front surface and a method of forming a polysilicon layer pad only in a region where a contact hole is to be formed. Such a polysilicon SAC method is characterized in that Since polycrystalline silicon having different etching mechanisms is used as an etch stopper, it is possible to obtain a high etching selectivity difference from the oxide film. When misalignment occurs, damage is caused to the substrate. In order to prevent this, a method of forming a spacer or using a polymer to expand the contact pad has been proposed, but this also has a problem that a design rule of 0.18 μm or less can not be realized.
상기와 같은 문제점을 해결하기 위하여 제시되고있는 것이 질화막을 식각방지막으로 사용하는 SAC방법이다. 이 방법은 층간절연막과 식각방지막간의 식각선택비차가 5 : 1 이상으로 큰 조건에서 건식식각하여 질화막을 제거하여 콘택홀을 형성하는데, 상기 식각공정은 식각선택비를 증가시키기 위하여 다량의 폴리머를 발생시키는 C-H-F계 가스나 수소를 포함하는 가스를 불활성 가스와 혼합하여 사용한다.In order to solve the above problems, the SAC method using a nitride film as an etch stop layer is proposed. In this method, dry etching is performed under the condition that the etching selectivity difference between the interlayer insulating film and the etching prevention film is greater than 5: 1 to remove the nitride film to form a contact hole, and the etching process generates a large amount of polymer to increase the etching selectivity. CHF-based gas or hydrogen-containing gas is mixed with an inert gas.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도로서, 듀얼 다마신공정의 예이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, which is an example of a dual damascene process.
먼저, 소정의 하부구조물, 예를들어 소자분리 절연막과 MOSFET 및 캐패시터 등이 형성되어 있는 반도체기판(10) 상부에 제1절연막(11)을 형성하고, 상기 제1절연막(11) 상부에 제1금속배선 패턴(13)을 형성한 후, 상기 구조의 전표면에 제2절연막(15)을 형성하고, 상기 제2절연막(15) 상에 비아콘택홀을 정의하기 위한 제1감광막 패턴(17)을 형성한다. 여기서, 상기 제2절연막(15)은 산화막으로 형성한다.First, a first insulating layer 11 is formed on a semiconductor substrate 10 on which a predetermined substructure, for example, a device isolation insulating layer, a MOSFET, a capacitor, and the like are formed, and a first insulating layer 11 is formed on the first insulating layer 11. After forming the metallization pattern 13, a second insulating layer 15 is formed on the entire surface of the structure, and the first photoresist layer pattern 17 for defining a via contact hole on the second insulating layer 15. To form. Here, the second insulating film 15 is formed of an oxide film.
그 다음, 상기 제1감광막 패턴(17) 상부에 제2금속배선이 들어갈 트렌치로 예정되어 있는 부분 및 비아콘택으로 예정되는 부분을 노출시키는 제2감광막 패턴(19)을 형성한다. (도 1a참조)Next, a second photoresist pattern 19 is formed on the first photoresist pattern 17 to expose a portion intended as a trench into which the second metal wiring is to be inserted and a portion intended to be a via contact. (See FIG. 1A)
그 다음, 상기 제2감광막 패턴(19)을 식각마스크로 사용하여 상기 제1감광막 패턴(17) 및 소정 두께의 제2절연막(15)을 식각한다. 이때, 제2금속배선이 들어갈 트렌치로 예정되어 있는 부분을 노출시키는 제2감광막 패턴(19)에 의해 상기 제1감광막 패턴(17)이 식각된다. (도 1b, 도 1c참조)Next, the first photoresist layer pattern 17 and the second insulating layer 15 having a predetermined thickness are etched using the second photoresist layer pattern 19 as an etching mask. At this time, the first photoresist pattern 17 is etched by the second photoresist pattern 19 exposing a portion intended as a trench into which the second metal wiring is to be inserted. (See FIG. 1B, FIG. 1C)
그 후, 상기 제1감광막 패턴(17) 및 제2감광막 패턴(19)에 의해 노출되어 있는 제2절연막(15)을 식각하여 상기 제1금속배선 패턴(13)에서 비아 콘택으로 예정되어 있는 부분을 노출시키는 비아콘택홀(16) 및 제2금속배선이 들어갈 트렌치(18)를 형성한다.Thereafter, the second insulating layer 15 exposed by the first photoresist layer pattern 17 and the second photoresist layer pattern 19 is etched so as to be a via contact in the first metal wiring pattern 13. A trench 18 into which the via contact hole 16 and the second metal wiring are exposed is formed.
그 후, 상기 제2감광막 패턴(19)과 제1감광막 패턴(17)을 제거한다. (도 1d참조)Thereafter, the second photoresist pattern 19 and the first photoresist pattern 17 are removed. (See FIG. 1D)
상기와 같은 종래기술에 따른 반도체소자의 제조방법은, 상기 제2감광막 패턴으로 상기 제1감광막 패턴과 제2절연막의 식각정도를 조절하기 어렵고, 비아콘택홀과 제2금속배선이 들어갈 트렌치를 형성한 후에 상기 비아콘택홀 상부의 제2절연막이 ⓐ 부분과 같이 첨점을 이루어 후속공정으로 금속층을 형성했을 때 상기 비아콘택홀 내부에서 보이드가 발생하여 수분 침투에 의한 부식등 소자의 특성에 영향을 미치는 문제점이 있다.In the method of manufacturing a semiconductor device according to the related art as described above, it is difficult to control the etching degree of the first photoresist pattern and the second insulation layer as the second photoresist pattern, and a trench into which a via contact hole and a second metal wiring is formed is formed. Afterwards, when the second insulating layer on the upper portion of the via contact hole forms a sharp point like the ⓐ portion, a void is generated in the via contact hole when the metal layer is formed in a subsequent process, thereby affecting the characteristics of the device such as corrosion due to moisture penetration. There is a problem.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 듀얼 다마신공정에서 마스크 공정을 독립적으로 두번에 걸쳐 실시하여 비아콘택홀을 형성하되, 절연막 스페이서를 형성하기 위한 전면식각공정을 과도하게 실시하여 상기 절연막 스페이서의 식각면과 같이 비아콘택홀의 상부를 라운드하게 형성하여 후속 상부 금속배선 형성시 상기 비아콘택홀 내에서 보이드가 발생하는 것을 방지하여 공정수율 및 소자의 동작특성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In the present invention, in order to solve the problems of the prior art, the via process is independently performed twice in a dual damascene process to form a via contact hole, but the surface etching process is excessively performed to form an insulation spacer. A method of fabricating a semiconductor device that improves process yield and device operation characteristics by forming round upper portions of the via contact holes, such as an etching surface of the insulating film spacer, to prevent voids from occurring in the via contact holes when forming a subsequent upper metal wiring. The purpose is to provide.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
10, 20 : 반도체기판 11, 21 : 제1절연막10, 20: semiconductor substrate 11, 21: first insulating film
13, 23 : 제1금속배선 패턴 15, 25 : 제2절연막13 and 23: first metal wiring pattern 15, 25: second insulating film
16, 30 : 비아콘택홀 17, 29 : 제1감광막 패턴16, 30: via contact hole 17, 29: first photosensitive film pattern
18, 32 : 트렌치 19, 33 : 제2감광막 패턴18, 32: trench 19, 33: second photosensitive film pattern
27 : 제3절연막 31 : 제4절연막27: third insulating film 31: fourth insulating film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 제1절연막을 형성하는 공정과,Forming a first insulating film on the semiconductor substrate on which a predetermined lower structure is formed;
상기 제1절연막 상부에 제1금속배선 패턴을 형성하는 공정과,Forming a first metal wiring pattern on the first insulating layer;
상기 구조의 전표면에 제2절연막을 형성하는 공정과,Forming a second insulating film on the entire surface of the structure;
상기 제2절연막 상부에 비아콘택으로 예정되는 부분이 노출되도록 패터닝된 제3절연막을 형성하는 공정과,Forming a third insulating film patterned on the second insulating film to expose a portion intended to be a via contact;
상기 제3절연막 상부에 제4절연막을 형성하는 공정과,Forming a fourth insulating film on the third insulating film;
상기 제4절연막을 전면식각하여 상기 제3절연막의 측벽에 제4절연막 스페이서를 형성하되, 과도식각공정을 실시하여 상기 제3절연막 및 제4절연막 스페이서를 모두 제거하고, 상기 제2절연막에 소정 두께 형성된 비아콘택홀의 상부가 라운드지게 하는 공정과,The fourth insulating layer is etched entirely to form a fourth insulating layer spacer on the sidewall of the third insulating layer, and the etching process is performed to remove all of the third insulating layer and the fourth insulating layer spacer, and a predetermined thickness is applied to the second insulating layer. Rounding the upper portion of the formed via contact hole,
상기 제2절연막 상부에 비아콘택 및 제2금속배선으로 예정되는 부분을 노출시키는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the second insulating layer to expose portions of the via contact and the second metal wiring;
상기 감광막 패턴을 식각마스크로 사용하여 상기 제2절연막을 식각하여 비아콘택홀 및 트렌치를 형성하되, 상기 비아콘택홀의 상부를 라운드지게 형성하는 것을 특징으로 한다.By using the photoresist pattern as an etching mask, the second insulating layer is etched to form via contact holes and trenches, but the upper portions of the via contact holes are rounded.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 소정의 하부구조물, 예를들어 소자분리 절연막(도시안됨)과 MOS FET 및 캐패시터(도시안됨) 등이 형성되어 있는 반도체기판(20) 상부에 제1절연막(21)을 형성하고, 상기 제1절연막(21) 상부에 제1금속배선 패턴(23)을 형성한 후, 전체표면 상부에 산화막을 사용하여 제2절연막(25)을 형성한다.First, a first insulating layer 21 is formed on a semiconductor substrate 20 on which a predetermined substructure, for example, an isolation layer (not shown), a MOS FET, a capacitor (not shown), and the like are formed. After the first metal wiring pattern 23 is formed on the first insulating film 21, the second insulating film 25 is formed on the entire surface by using an oxide film.
그 다음, 상기 제2절연막(25) 상부에 제3절연막(27)을 형성한다. 상기 제3절연막(27)은 상기 제2절연막(25)과 동일한 재질 또는 상기 제2절연막(25)보다 식각선택비가 낮은 재질의 물질을 사용하여 3000 ∼ 5000Å 두께로 형성한다.Next, a third insulating layer 27 is formed on the second insulating layer 25. The third insulating layer 27 is formed to have a thickness of 3000 to 5000 kV using the same material as the second insulating layer 25 or a material having a lower etching selectivity than the second insulating layer 25.
다음, 상기 제3절연막(27) 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막 패턴(29)을 형성한다.Next, a first photoresist layer pattern 29 is formed on the third insulating layer 27 to expose a portion to be via contact.
그 다음, 상기 제1감광막 패턴(29)을 식각마스크로 사용하여 상기 제3절연막(27)을 식각한다. (도 2a참조)Next, the third insulating layer 27 is etched using the first photoresist pattern 29 as an etching mask. (See Figure 2A)
그리고, 상기 제1감광막 패턴(29)을 제거한 다음, 전체표면 상부에 제4절연막(31)을 형성한다. 상기 제4절연막(31)은 산화막을 사용하여 1500 ∼ 4000Å 두께로 형성한다. (도 2b참조)After removing the first photoresist layer pattern 29, a fourth insulating layer 31 is formed on the entire surface. The fourth insulating film 31 is formed to a thickness of 1500 to 4000 kV using an oxide film. (See Figure 2b)
다음, 상기 제4절연막(31)을 불소가스를 주식각가스로 사용한 전면식각공정으로 상기 제3절연막(27)의 측벽에 제4절연막 스페이서를 형성하고, 과도식각을 실시하여 상기 제4절연막 스페이서와 제3절연막(27)을 모두 제거한다. 이때, 상기 제2절연막(25)은 상기 과도식각공정시 제거된 제3절연막(27)의 두께 만큼 식각되고, 상기 제2절연막(25)의 식각면은 상기 제4절연막 스페이서의 식각면처럼 라운딩된다. (도 2c참조)Next, a fourth insulating layer spacer is formed on sidewalls of the third insulating layer 27 by a full surface etching process using the fourth insulating layer 31 as fluorine gas as a stock corner gas, and the fourth insulating layer spacer is transiently etched. And all of the third insulating film 27 are removed. In this case, the second insulating layer 25 is etched by the thickness of the third insulating layer 27 removed during the transient etching process, and the etching surface of the second insulating layer 25 is rounded like the etching surface of the fourth insulating layer spacer. do. (See FIG. 2C)
그 다음, 상기 제2절연막(25) 상부에 제2금속배선으로 예정되는 부분을 노출시키는 제2감광막 패턴(33)을 형성한다.Next, a second photoresist layer pattern 33 is formed on the second insulation layer 25 to expose a portion of the second insulation layer 25.
그리고, 상기 제2감광막 패턴(33)을 식각마스크로 사용하여 상기 제2절연막(25)을 식각함으로써 식각면이 ⓧ 부분과 같이 라운드한 비아콘택홀(30) 및 트렌치(32)를 형성한다. 상기 식각공정은 불소가스를 주식각가스로 사용한 건식식각공정으로 실시한다. (도 2d참조)The second insulating layer 25 is etched using the second photoresist pattern 33 as an etch mask to form a via contact hole 30 and a trench 32 in which an etch surface is rounded like a ridge. The etching process is performed by a dry etching process using fluorine gas as a stock etch gas. (See FIG. 2D)
그 후, 상기 제2감광막 패턴(33)을 제거하고, 상기 비아콘택홀 및 트렌치(32)를 매립하여 상기 제1금속배선 패턴(23)과 접속되는 금속층을 형성한 다음, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정을 실시하여 제2금속배선을 형성한다.Thereafter, the second photoresist layer pattern 33 is removed, and the via contact hole and the trench 32 are filled to form a metal layer connected to the first metal interconnection pattern 23. mechanical polishing, hereinafter referred to as CMP), to form a second metal wiring.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 상부 금속배선을 산화막에 형성된 트렌치에 형성하는 듀얼 다마신 공정에서 하부 금속배선을 형성한 다음, 전표면 상부를 평탄화시키는 층간절연막을 형성한 다음, 상기 층간절연막 상부에 비아콘택으로 예정되는 부분을 노출시키는 식각방지막을 형성하고, 상기 식각방지막의 식각면에 절연막 스페이서를 형성하되, 상기 절연막 스페이서를 형성하기 위한 전면식각공정시 과도식각공정을 실시하여 상기 절연막 스페이서와 식각방지막을 모두 제거한 후, 상부전극 및 비아콘택으로 예정되는 부분을 노출시키는 감광막 패턴을 식각마스크로 사용하여 식각함으로써 비아콘택홀 상부를 라운드지게 형성하여 비아콘택홀 내부에서 보이드가 발생하는 것을 방지하고, 그에 따른 소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, in the dual damascene process in which the upper metal wiring is formed in the trench formed in the oxide film, the lower metal wiring is formed, and then an interlayer insulating film is formed to planarize the upper surface of the entire surface. Next, an etch stop layer is formed on the interlayer insulating layer to expose a predetermined portion as a via contact, and an insulating layer spacer is formed on an etched surface of the etch stop layer, and a transient etching process is performed during the entire surface etching process to form the insulating layer spacer. After the removal of both the insulating film spacer and the etch stop layer by etching, using the photoresist pattern to expose the upper electrode and the predetermined portion as the via contact as an etching mask to form a round upper portion of the via contact hole in the via contact hole To prevent voids from occurring and thereby There is an advantage of improving characteristics and reliability.
Claims (7)
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