KR100334534B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, wherein an interlayer during an etching process for forming a primary contact hole in an EM SAC process using a nitride film as an etch barrier layer and using an etch mask exposing the entire active region in a contact etching process. The dry etching is performed to dry the just layer corresponding to the thickness of the insulating film, so that the interlayer insulating film remains in the contact portion to some extent, and the second etching is performed to remove the remaining interlayer insulating film by wetness. In the case of using an APL oxide film, the etch stop generated in the void portion during dry etching can be removed in a subsequent wet etching process even in a fine pattern such that voids are formed between the gate electrodes, thereby preventing loss of nitride film and Process yield because the degree is increased and contact failure can be prevented It is possible to improve the reliability of the device operation.

Description

Manufacturing method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a nitride film is used as an etch barrier layer in a self align contact (hereinafter referred to as SAC) using an etch barrier layer, and the contact is widely spread over the active region. In the case of the open margin margin SAC (hereinafter referred to as EMSAC) process, the removal of the interlayer insulating layer of oxide material is carried out dry without over-etching first, and the interlayer insulating layer of the remaining thickness is removed by the wet method. The present invention relates to a method for manufacturing a semiconductor device capable of minimizing the loss of metal, removing the polymer component formed in the contact portion, preventing etch stop caused by voids, and increasing process margin to improve reproducibility and stability.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology. For the formation of fine patterns, photoresist patterns of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are used in the manufacturing process of semiconductor devices. Micronization is a must.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate, but is primarily proportional to the light source wavelength (λ) and the process variable (k) of the reduction exposure apparatus used. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device. [R = k * λ / NA, ~ R = resolution, ~ λ = wavelength of light source, NA = opening number ~]

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, a process method may be used as a phase shift mask instead of a conventional photo mask, or a separate thin film may be formed on the wafer to improve image contrast. A tri-layer resister (hereinafter referred to as TLR) is formed by interpolating a CEL method or an intermediate layer such as spin on glass (SOG) between two photoresist layers. Method or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced. As the aspect ratio, which is a ratio of depth, increases, highly integrated semiconductor devices having multilayer conductive wirings require accurate and strict alignment between masks in a manufacturing process to form contacts, thereby reducing process margin. .

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, Since the mask must be formed in consideration of factors such as registration between the masks, the process margin is further reduced to prevent high integration of the device.

Such contact holes may have misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

1A and 1B are a manufacturing process diagram of a semiconductor device according to a first embodiment of the prior art, which relates to an EMSAC method.

First, a MOS field effect transistor such as a predetermined structure, for example, an element isolation oxide film 11, a gate oxide film 12, a gate electrode 13, and a source / drain region 15, may be formed on the semiconductor substrate 10. Metal Oxide Semiconductor Field Effect Transister (hereinafter referred to as MOS FET). In this case, a mask oxide layer 14 and a mask nitride layer 16 pattern overlap each other on the gate electrode 13.

After that, a nitride spacer 17 is formed on sidewalls of the gate electrode 13, the mask oxide layer 14, and the mask nitride layer 16. Then, an interlayer dielectric layer 18 is formed, and the first interlayer dielectric layer 18 is formed. The upper portion of the interlayer insulating film 18 is planarized by chemical-mechanical polishing (hereinafter referred to as CMP) method, and is arranged in contact with the charge storage electrode and the bit line in the semiconductor substrate 10. ) Is formed a photosensitive film pattern 19. The photoresist pattern 19 may be formed using a device isolation mask because the photoresist pattern 19 is formed to expose a T-shaped active region. (See FIG. 1A).

Thereafter, the interlayer insulating film 18 exposed by the photosensitive film pattern 19 is dry etched to expose the upper portion of the mask nitride film 16, and the etching is performed continuously to expose a portion of the semiconductor substrate 10 that is intended to be in contact with the semiconductor substrate 10. A contact hole 20 is formed. (See FIG. 1B).

Thereafter, although not shown, a process of forming a separate interlayer insulating film, a bit line contact and a bit line, a charge storage electrode contact, and a charge storage electrode is performed.

The contact formation method in the EMSAC process according to the prior art is that when the device is highly integrated and there is not enough space between the gate electrodes, it is difficult to secure the contact open area, so that the thickness of the nitride film, which is an etch barrier, should be thinned. When the loss is reduced, it is possible to prevent the occurrence of defects such as short circuits. When the nitride film spacer is thinly formed, the margin of overetching process is reduced, so that device fabrication is difficult and reproducibility is inferior.

2A to 2B are manufacturing process diagrams of a semiconductor device according to another exemplary embodiment of the related art, which is an example in which voids are formed when an interlayer insulating film is formed.

The same process as in FIG. 1A is sequentially performed, but when the gap between the gate electrodes 13 is reduced to 0.05 μm or less, the interlayer insulating film is referred to as ordinary B. P. S. glass (hereinafter referred to as BPSG). The use of high density plasma oxide film or chemical vapor deposition (CVD) oxide film, which is not available, makes it possible to use APL (advanced planerization layer) oxide film. Although having a void 30 may be formed (see FIG. 2A), in this case, when the etching process is performed, an etch stop 32 made of a material such as a polymer is generated at the portion having the void 30. Interfere with contact open. (See FIG. 2B).

The semiconductor device manufacturing method according to the prior art using the EM SAC process using the nitride film as an etching barrier as described above can not form the thickness of the nitride film spacer thick in the case of a fine pattern with a small gate gap for contact opening Minimize the loss of the nitride film during the overetching process of the interlayer insulating film to prevent the occurrence of defects such as short circuit, but it is difficult to control such process, the process stability and reproducibility is lowered, and the gap filling characteristics are excellent when forming a finer pattern High density plasma oxide film or APL oxide film is used, but when voids are generated between the gates due to the gap gap filling, a large amount of polymer is generated in the part where the voids are formed so that the contact stop is not formed properly, so the process yield And doors that reduce the reliability of device operation There is a problem.

The present invention is to solve the above problems, an object of the present invention is to perform the dry etching to the extent to expose the nitride film during the contact hole etching process in the EM SAC process using the nitride film as an etching barrier, the second wet By removing the remaining oxide film, the loss of nitride film is minimized to increase the process margin in the etching process, and the etch stop formed in the void part is removed during wet etching, and the oxide film is also removed together to prevent contact defects. And to provide a method for manufacturing a semiconductor device that can improve the reproducibility.

1A and 1B are a manufacturing process diagram of a semiconductor device according to a first embodiment of the prior art.

2A and 2B are manufacturing process diagrams of a semiconductor device according to a second embodiment of the prior art.

3a to 3c is a manufacturing process diagram of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 11: device isolation oxide film

12 gate oxide film 13 gate electrode

14 mask oxide film 15 source / drain region

16: mask nitride film 17 nitride film spacer

18: interlayer insulating film 19: photosensitive film pattern

20: contact hole 30: void

32: etch stop

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

In the EMSAC process using a nitride film as an etch barrier layer,

Forming a predetermined lower structure on the semiconductor substrate;

Forming a nitride film pattern surrounding the lower structure and exposing a portion of the semiconductor substrate to be contacted with the semiconductor substrate;

Forming an interlayer insulating film of an oxide film material having a flattened upper surface on the entire surface of the structure;

Forming a photosensitive film pattern exposing an active region on the interlayer insulating film;

A first etching process of removing the interlayer insulating film exposed by the photosensitive film pattern by a dry etching method, but leaving the interlayer insulating film on the semiconductor substrate scheduled as a contact without overetching;

A secondary etching process of removing the remaining interlayer insulating film exposed by the photosensitive film pattern by a wet etching method.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C illustrate an example of an EM SAC process using a nitride film as an etch barrier layer.

First, as shown in FIG. 1A, the MOS FETs of the device isolation oxide film 11, the gate oxide film 12, the gate electrode 13, and the source / drain regions 15 are sequentially formed on the semiconductor substrate 10. A nitride film 14 pattern and a mask nitride film pattern 16 overlapping the gate electrode 13 and a nitride film on sidewalls of the gate electrode 13, mask oxide film 14 pattern and mask nitride film 16 pattern. The spacer 17 is formed.

Then, after forming the interlayer insulating film 18 of BPSG, high density plasma or APL oxide material on the entire surface of the structure, planarizing the upper portion by the CMP method, defining an active region on the interlayer insulating film 18 To form the photosensitive film pattern 19. At this time, if the pattern is a fine pattern of 0.13 μm or less, the void 30 is formed inside the interlayer insulating film 18 as a current oxide film material, and the photosensitive film pattern 19 is charged on the semiconductor substrate 10. The interlayer insulating film 18, which is intended to be in contact with the storage electrode and the bit line, is exposed in the shape of an active region such as T, I or Z, and is located between the four gate electrodes 13. Three semiconductor substrates 10 are exposed. (See FIG. 3A).

Thereafter, the interlayer insulating film 18 exposed by the photosensitive film pattern 18 is dry etched, but no over etching of about 30 to 50% is performed. Therefore, a part of the interlayer insulating film 18 remains on the portion scheduled as the contact, and the etch stop 32 is formed in the portion where the void 30 is formed. (See Figure 3b).

Then, the remaining interlayer insulating film 18 is removed by a wet etching method, whereby the etch stop is also removed to form the contact hole 20. In the wet etching method, preferably, the use of HF base chemical increases the etching selectivity between the oxide series and the nitride layer, thereby further increasing the process margin, and more preferably, 300: 1 dilution BOE or 50: as the existing HF base chemical. Use 1 dilute HF. (See FIG. 3C).

In order to prevent the sidewalls of the interlayer dielectric layer from being removed by wet etching, thereby reducing the wiring gap between the bit line and the charge storage electrode, the interlayer dielectric layers are stacked in two layers, the upper layer having a strong resistance to wet etching. It can also be formed.

As described above, the method of manufacturing a semiconductor device according to the present invention includes forming a first contact hole in an EM SAC process using a nitride film as an etch barrier layer and using an etch mask that exposes the entire active region in a contact etching process. During the etching process, just etching corresponding to the thickness of the interlayer insulating film is carried out dryly so that the interlayer insulating film remains in the contact portion, and the second etching is performed to remove the remaining interlayer insulating film by wetness, and the step coverage is superior to the BPSG. In the case of using a high density plasma oxide film or an APL oxide film, the etch stop generated in the void portion during dry etching can be removed in a subsequent wet etching process even in a fine pattern such that voids are formed between the gate electrodes, thereby preventing loss of the nitride film. Process margins are increased, and contact failures can be prevented. It has the advantage to improve the reliability of the process yield and device operation.

Claims (3)

In the EMSAC process using a nitride film as an etch barrier layer, Forming a predetermined lower structure on the semiconductor substrate; Forming a nitride film pattern surrounding the lower structure and exposing a portion of the semiconductor substrate to be contacted with the semiconductor substrate; Forming an interlayer insulating film of an oxide film material having a flattened upper surface on the entire surface of the structure; Forming a photosensitive film pattern exposing an active region on the interlayer insulating film; A first etching process of removing the interlayer insulating film exposed by the photosensitive film pattern by a dry etching method, but leaving the interlayer insulating film on the semiconductor substrate scheduled as a contact without overetching; And a second etching process for removing the remaining interlayer insulating film exposed by the photosensitive film pattern by a wet etching method. The method of claim 1, The interlayer insulating film is formed of any one of BPSG, high density plasma oxide film or APL oxide film. The method of claim 1, The interlayer insulating layer is formed of two layers, and the upper layer is formed of a material having a stronger wet etching resistance than the lower layer.