KR20040061857A - Method for fabricating of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent short and to improve topology of a gate electrode by using a dual hard mask. CONSTITUTION: A gate oxide layer(12) and a conductive layer(14) are formed on a substrate(10). By sequentially depositing and patterning the first nitride layer(30-1) and the second nitride layer(30-2), a dual hard mask is formed on the gate conductive layer. At this time, the first nitride layer is formed by PECVD(Plasma Enhanced CVD) and the second nitride layer is formed by LPCVD(Low Pressure CVD). The first insulating spacer(32) is formed at both sidewalls of the patterns. Landing plug contact holes are formed by etching an interlayer dielectric. The second insulating spacer is formed at both sidewalls of the first insulating spacer.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a hard mask layer for protecting a gate electrode of a metal oxide semi-conductor field effect transistor (hereinafter, referred to as a MOS FET) is formed of a multilayer insulating film of various materials. A semiconductor device capable of improving process yield and device operation reliability by minimizing loss of hard mask layer during subsequent self align contact (SAC) process to prevent short circuit caused by exposure of gate electrode. It relates to a manufacturing method.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, ~ R = resolution, ~ λ = wavelength of light source, NA = opening number ~]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

First, a gate oxide film 12, a conductive layer 14 such as polysilicon or W, and a hard mask layer 16 made of a nitride film are sequentially formed on the semiconductor substrate 10. (See FIG. 1A).

Next, a gate patterning photoresist pattern (not shown) is formed on the hard mask layer 16, and the hard mask layer 16, the conductive layer 14, and the gate oxide layer 12 exposed by the photoresist pattern are formed. Are sequentially removed to form the gate electrode 18 overlapping the mask insulating film 16 pattern. At this time, some thickness of the hard mask layer 16 remains. (See FIG. 1B).

Thereafter, an insulating spacer 20 is formed on sidewalls of the gate electrode 18 and the hard mask layer 16 pattern. In this case, the insulating spacer includes a sealing nitride film 20-1 and a spacer nitride film 20-2. (See FIG. 1C).

Although not shown, an interlayer insulating film (not shown) is formed on the entire surface of the structure to form a landing plug contact, a landing plug contact hole is formed, and a landing plug that fills the contact hole is formed.

In the method of manufacturing a semiconductor device according to the related art as described above, the hard mask layer is removed from the fixing of the landing plug and the mask insulating film pattern under the damaged portion is damaged. This is again performed at the subsequent formation of the bit line, the charge storage electrode, or the metal contact. If the hard mask layer pattern is damaged, the gate electrode beneath it may be exposed and a short circuit may occur between the wirings. Thus, a mask insulating film should be formed to a sufficient thickness. In this case, the step height is increased during the gate electrode patterning process to make the subsequent process more difficult. Due to the high integration of the device, the gap between gate electrodes is reduced and voids may occur because the insulating film for forming the landing plug does not fill the gate electrodes properly. Process yield and device copper This reliability has lowered.

The present invention is to solve the above problems, an object of the present invention is to form a hard mask layer used in the gate electrode patterning in a multi-layer laminated structure of a different material so that a portion remains after the gate electrode patterning gate electrode The upper part of the substrate is stably protected by a mask insulating film pattern to prevent short circuits between wirings in a subsequent process, to reduce the step difference during the gate electrode patterning, to facilitate the etching process, to prevent the occurrence of voids in the insulating film, and to contact plugs. The semiconductor device can improve the pattern uniformity during the CMP process, and the second layer of the insulating spacer material is applied after the contact hole is formed to favor the gap fill of the interlayer insulating film, thereby improving process yield and reliability of device operation. To provide a method of manufacturing.

1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

2a to 2d is a manufacturing process diagram of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10 semiconductor substrate 12 gate oxide film

14 conductive layer 16 hard mask layer

18 gate electrode 20 insulating spacer

20-1: sealing nitride film 20-2: spacer nitride film

30-1: First nitride film 30-2: Second nitride film

32: first spacer insulating film 34: contact hole

36 second spacer insulating film 38 contact plug

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

A gate insulating film, a conductive layer, and a hard mask layer are sequentially formed on the semiconductor substrate, and the hard mask layer is formed of a three-layer nitride film, and a low pressure chemical vapor deposition nitride film is interposed between the upper and lower plasma induced chemical vapor deposition nitride films. Forming process,

Forming a gate electrode having a conductive layer pattern overlapping with the hard mask layer pattern by etching the conductive layer below the hard mask layer by a photolithography process using a gate electrode patterning mask;

Forming a first spacer insulating film serving as an insulating spacer on the entire surface of the structure;

Forming an interlayer insulating film on the entire surface of the structure;

Forming a landing plug contact hole by patterning a photolithography process using a landing plug contact etching mask on the interlayer insulating film;

And forming a second spacer insulating film on the entire surface of the structure.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.

First, a gate oxide film 12 is formed on the semiconductor substrate 10, and a conductive layer 14 serving as a gate electrode, a mask insulating film 16 and a hard mask layer 30 made of nitride are sequentially formed thereon. do. The hard mask layer 30 may include a first nitride film 30-1, a second nitride film 30-2, and a third nitride film 30-3, and the first nitride film 30-1 may be a landing plug. The thickness that should remain after the etching process is formed by the plasma induced chemical vapor deposition method, and the second nitride film 30-2 is formed by the low pressure chemical vapor deposition method to have a thickness greater than or equal to the thickness of the second gate sidewall material. The third nitride film 30-2 is formed by a plasma induced chemical vapor deposition method by a height lost during gate patterning. The third nitride layer 30-3 becomes a barrier during the SAC etching process for gate patterning and landing plug contact hole formation. (See FIG. 2A).

Next, a gate patterning photoresist pattern (not shown) is formed on the hard mask layer 30, and the hard mask layer 30, the conductive layer 14, and the gate oxide layer 12 exposed by the photoresist pattern are formed. Are sequentially removed to form the gate electrode 18 overlapping with the hard mask layer 16 pattern. In this case, a part of the thickness of the second nitride film 30-2 of the hard mask layer 30 is removed. (See FIG. 2B).

An interlayer insulating film (not shown) is then formed on the entire surface of the structure to form a first spacer insulating film 32, which is part of the insulating spacer, and to form a landing plug contact on the entire surface of the structure, using an oxide film or a nitride film. Is applied, and the landing plug contact hole 34 is formed by the SAC method. (See FIG. 2C).

Then, the second spacer insulating film 36 is coated on the entire surface of the structure, and the spacers are etched to form the first and second spacer insulating films 32 and (2) on the sidewalls of the gate electrode 18 and the hard mask layer 30 pattern. 36) A spacer in a pattern is formed. (See FIG. 2D).

As described above, in the method of manufacturing the semiconductor device according to the present invention, since the hard mask layer for forming the gate electrode is formed as a double layer, and one of the two layers of the gate electrode sidewall insulating film is formed after the contact hole is formed, it is difficult to harden even after the gate electrode patterning. The masking layer is sufficiently left to protect the lower layers such as the mask insulating layer pattern and the gate electrode in the subsequent landing plug process as well as the process of forming the bit line or the charge storage electrode contact, and the step difference of the gate electrode can be reduced. It is easy to increase the halo ion implantation slope, to prevent the generation of voids during the coating of the insulating film, and to prevent the fall due to the exposure of the gate door door yield and the reliability of the device operation has the advantage.

Claims (1)

A gate insulating film, a conductive layer, and a hard mask layer are sequentially formed on the semiconductor substrate, and the hard mask layer is formed of a three-layer nitride film, and a low pressure chemical vapor deposition nitride film is interposed between the upper and lower plasma induced chemical vapor deposition nitride films. Forming process, Forming a gate electrode having a conductive layer pattern overlapping with the hard mask layer pattern by etching the conductive layer below the hard mask layer by a photolithography process using a gate electrode patterning mask; Forming a first spacer insulating film serving as an insulating spacer on the entire surface of the structure; Forming an interlayer insulating film on the entire surface of the structure; Forming a landing plug contact hole by patterning a photolithography process using a landing plug contact etching mask on the interlayer insulating film; A method of manufacturing a semiconductor device, comprising the step of forming a second spacer insulating film on the entire surface of the structure.