KR100419752B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In the method of forming a bit line by a damascene process, a dummy bit line is formed by a low dielectric layer pattern, and an insulating layer spacer is formed on sidewalls of the dummy bit line. Next, the bit line contact hole and the bit line trench may be removed by removing the dummy bit line, and the bit line contact hole and the bit line trench may be simultaneously buried to form the bit line contact and the bit line at the same time. Simplify and form the bit line by the deposition process rather than the etching process to improve the interfacial properties between the bit line and other materials, thereby preventing the bit line from lifting in subsequent high temperature processes. The material can also be formed as a bit line to improve the operating characteristics of the device, The gap fill property is excellent, and short-circuit between contacts due to voids can be prevented.

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a bit line contact bit and a bit line contact plug which simultaneously form a bit line contact hole and a bit line trench in a damascene process and then fill the bit line contact hole and a bit line trench. It relates to a method of forming.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.5 and 0.3 µm, respectively. Exposure is limited using a deep ultra violet (DUV) light source, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source to form a fine pattern of 0.3 μm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a high integration of the device, and the size of the contact holes decreases, and the distance between the peripheral wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes have misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.

In order to overcome the limitations of the lithography process in forming the contact holes, a self aligned contact (SAC) technology for forming contact holes by a self alignment method has been developed.

The SAC method may be divided into a polysilicon layer, a nitride film, or an oxynitride film according to the material used as the etch barrier layer, and the most promising method is to use a nitride film as an etch barrier.

When the conductive wiring is formed by the SAC method as described above, the contact hole is formed, the contact plug is formed, the conductive layer is formed, and then the conductive layer is etched using the conductive wiring mask to form the conductive wiring. The bit line is lifted due to the subsequent process temperature due to the stress caused by the etching process, and the wiring etching becomes difficult as the thickness of the photoresist pattern decreases.

In order to solve the above problems, a conductive wiring was formed by a damascene process.

The bit line is formed by the damascene process, and the bit line contact and the bit line trench etching are simultaneously performed by the dual damascene process to simultaneously form the bit line and the bit line contact plug.

However, since the method requires a high etching selectivity for the mask insulating film and the insulating film spacer to prevent the short-line between the bit line etch stop layer and the gate electrode and the contact in the self-aligned contact process during the etching process of the insulating film, the pattern size of the device As it becomes smaller and the height of the photoresist pattern is lowered, the etching process is very difficult and the process margin is narrow.

On the other hand, the single damascene process which first forms the contact plug and then forms the bit line by the damascene process is easier to etch than the dual damascene process, but the contact plug formation process and the bit line formation process must be performed separately. This has the disadvantage of becoming complicated.

In addition, when forming the bit line, an insulating film surrounding the bit line should be formed to prevent a short circuit with the bit line when forming the storage electrode contact, which is a subsequent process. There is a disadvantage that is difficult to form.

In the dual damascene process, after the bit line trench and the bit line contact etching are performed by the insulating film etching process, an insulating film spacer surrounding the bit line is formed. As a result, contact opening to the semiconductor substrate is almost impossible. In the single damascene process, a mask insulating film is exposed at the bottom after the bit line trench etching. An insulating film surrounding the subsequent bit line has a problem that a high etching selectivity must be secured for the lower mask insulating film or the interlayer insulating film under the spacer etching process. have.

In order to solve the above problems of the prior art, a dummy bit line is formed using a low dielectric film in a process of forming a bit line by a damascene process, and a nitride film spacer surrounding the dummy bit line is formed. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which a bit line contact plug and a bit line are formed after removing the dummy bit line.

1 to 7 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention.

<Description of Signs of Major Parts of Drawings>

11 semiconductor substrate 13 gate electrode

15: first mask insulating film pattern 17: insulating film spacer

19: first interlayer insulating film 21: bit line contact hole

23: low dielectric film 25: second mask insulating film

27: photosensitive film pattern 29: first barrier insulating film

31: second interlayer insulating film 32: first barrier insulating film pattern

33: bit line 35: second barrier insulating film pattern

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a gate electrode and a source / drain region having a first mask insulating film pattern on an upper side of a semiconductor substrate and a first insulating film spacer on a sidewall of the semiconductor device. Forming a MOS field effect transistor; forming a first interlayer insulating film having a bit line contact hole exposing a portion of the semiconductor substrate to be a bit line contact on an entire surface of the semiconductor substrate; Forming a dummy bit line having a stacked structure of a low dielectric layer pattern formed over the first interlayer dielectric layer and a second mask insulating layer pattern superimposed thereon, filling the hole; Forming a barrier insulating film to a predetermined thickness, and then forming and planarizing a second interlayer insulating film; and the second interlayer insulating film, Sequentially etching a wall insulating film and a second mask insulating film to expose the low dielectric film and to form a first barrier insulating film pattern surrounding the low dielectric film; and removing the low dielectric film to form bit line contact holes and trenches. And forming a bit line filling a portion of the bit line contact hole and a trench;

And forming a second barrier insulating film pattern on an unfilled portion of the bit line trench. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, a device isolation insulating film (not shown) is formed on a portion of the semiconductor substrate 11, which is intended as an isolation region, and a gate insulating film (not shown) is formed on the entire surface, and then the gate electrode is electrically conductive on the entire surface. A layer and a first mask insulating film are formed sequentially.

Next, the first mask insulating layer and the conductive layer for the gate electrode are etched using the gate electrode mask as an etch mask to form a stacked structure of the gate electrode 13 and the first mask insulating layer pattern 15.

Next, a first insulating film spacer 17 is formed on sidewalls of the stacked structure.

Next, a first interlayer insulating film 19 is formed on the entire surface of the first interlayer insulating film 19 to planarize, and a bit line contact mask that exposes a portion of the semiconductor substrate 11 to be a bit line contact is used as an etching mask. The insulating film 19 is etched to form the bit line contact hole 21. (See Figure 1)

Subsequently, the low dielectric layer 23 and the second mask insulating layer 25 are sequentially formed on the entire surface, and the photoresist layer pattern 27 which protects a portion intended as a bit line on the second mask insulating layer 25 is sequentially formed. ).

The low dielectric film 23 is a material having a low dielectric constant k of 0 to 4, and includes flare, silk, DVS-BCB, PAE-2, Lo-K2000, Paryene AF4, and PFCB (Perfluoro-cyclobuten). ), Teflon AF, Fluorineted polyimide, FSG, nanoglass and aC: F are used at random. In addition to the above materials, one selected from the group consisting of Si-OC-based, Si-OF-based, -Si-O-based, polymer-based, and CF _x- based materials may be used, and a photoresist or easily removable ductile material may be used. It can form using the substance which has.

The second mask insulating layer 25 is used as a hard mask and an etching barrier to prevent the etching selectivity with the photosensitive layer pattern 27 from being lowered during the etching process of the low dielectric layer 23 in a subsequent process. . The second mask insulating layer 25 is formed of one or more materials arbitrarily selected from the group consisting of a nitride film, SiO ₂ , Al ₂ O _3, and Ta ₂ O ₅ . (See Figure 2)

The second mask insulating layer 25 and the low dielectric layer 23 are etched using the photoresist pattern 27 as an etch mask to form dummy bit lines, and the photoresist pattern 27 is removed.

First, the second mask insulating film 25 is _{CF 4, SF 6, NF 3} , C 2 F 6, CHF 3, C 3 F 6, C 3 F 8, C 4 F 6, C 4 F 8 Mitch C ₅ One selected arbitrarily from the group consisting of F ₁₀ is used as the stock angular gas, and the etching surface is formed vertically by using a gas containing oxygen and a mixed gas of an inert gas as the etch gas.

The low dielectric layer 23 may be removed by a plasma etching process using O ₂ or N ₂ or Ar, which is a method of removing the photoresist film, or a plasma etching process using a mixed gas of the gas. In this case, in order to prevent the side wall portion from being damaged during the etching process of the low dielectric layer 23, a gas of SF ₆ or SO _x system is added to generate a polymer of SC and SCH to passivate the side wall portion. A vertical etch section is formed.

During the etching process of the low dielectric layer 23, the etching ratio of the photosensitive layer pattern 27 may be higher than that of the low dielectric layer 23 to remove the photosensitive layer pattern 27 at the same time. (See Figure 3)

Next, a first thickness of the first barrier insulating film 29 is formed on the entire surface, and a second interlayer insulating film 31 is formed on the first barrier insulating film 29 and planarized. The first barrier insulating film 29 may be formed of one selected from the group consisting of a SiON film, a SiON film containing a large amount of Si, a TiO ₂ film, an Al ₂ O ₃ film, and a Ta ₂ O ₅ film. (See Figure 4)

Next, the second interlayer insulating film 31, the first barrier insulating film 29 and the second mask insulating film 25 are chemical mechanical polishing (CMP) or chemically enhanced polishing (CEP) or front surface. The low dielectric layer 23 is exposed by an etch back process.

In the process, a first barrier insulating layer pattern 32 is formed on the sidewall of the low dielectric layer 23. The first barrier insulating layer pattern 32 prevents the storage electrode and the bit line from being shorted to each other in a subsequent process. (See Figure 5)

Next, the low-k dielectric layer 23 is removed to simultaneously form a bit line contact hole and a bit line trench. The low dielectric layer 23 is removed by a plasma etching process using one gas arbitrarily selected from the group consisting of O ₂ , N ₂ , Ar, SO _x, and SF ₆ , or ACT, CLEAN-D, BOE, and solvent-based systems. Removal is carried out using one arbitrarily selected from the group consisting of wet chemicals.

Then, a plurality of randomly selected from the group consisting of polycrystalline silicon layer, Ti, TiN, WSi _x and W are deposited on the entire surface, and then etched to the inner part of the bit line trench by front etching or CMP process or CEP process. The bit line 33 is formed. (See Figure 6)

Next, a second barrier insulating layer (not shown) is formed on the entire surface, and the second barrier insulating layer pattern 35 is formed on the bit line 33 by planarization or planarization by CMP or CEP. The second barrier insulating film pattern 35 may be formed of one selected from the group consisting of a SiON film, a SiON film containing a large amount of Si, a TiO ₂ film, an Al ₂ O ₃ film, and a Ta ₂ O ₅ film. In the process, together with the first barrier insulating layer pattern 32, a short circuit may be prevented between the storage electrode and the bit line 33. (See Figure 7)

As described above, in the method of manufacturing a semiconductor device according to the present invention, in the method of forming a bit line by a damascene process, a dummy bit line is formed by a low dielectric film pattern, and an insulating film spacer is formed on the sidewall of the dummy bit line. Next, the bit line contact hole and the bit line trench may be removed by removing the dummy bit line, and the bit line contact hole and the bit line trench may be simultaneously buried to form the bit line contact and the bit line at the same time. Simplify and form the bit line by the deposition process rather than the etching process to improve the interfacial properties between the bit line and other materials, thereby preventing the bit line from lifting in subsequent high temperature processes. The material can also be formed into bit lines, which improves the operating characteristics of the device. It is possible to prevent the short circuit between contacts due to voids due to excellent gap fill characteristics.

Claims (10)

Forming a MOS field effect transistor including a gate electrode and a source / drain region having a first mask insulating film pattern on an upper side of the semiconductor substrate and a first insulating film spacer on a sidewall thereof; Forming a first interlayer insulating film having a bit line contact hole exposing a portion of the semiconductor substrate to be a bit line contact on an entire surface thereof; Forming a dummy bit line filling the bart contact hole and having a stack structure of a low dielectric film pattern formed higher than the first interlayer insulating film and a second mask insulating film pattern superimposed thereon; Forming a first barrier insulating film a predetermined thickness over the entire surface, and then forming and planarizing a second interlayer insulating film; Sequentially etching the second interlayer insulating film, the first barrier insulating film, and the second mask insulating film to expose the low dielectric film and to form a first barrier insulating film pattern surrounding the low dielectric film; Removing the low dielectric layer to form bit line contact holes and trenches, and then forming bit lines filling a portion of the bit line contact holes and trenches; And forming a second barrier insulating film pattern on an unfilled portion of the bit line trench. The method of claim 1, And the low dielectric film is formed of a material having a dielectric constant k of 0 to 4. The method of claim 2, The low dielectric film is flare, silk, DVS-BCB, PAE-2, Lo-K2000, Paryene AF4, PFCB (Perfluoro-cyclobuten), Teflon AF, fluorineted polyimide, FSG And formed using one selected from the group consisting of nanoglass, aC: F, Si-OC, Si-OF, -Si-O-, polymer and CF _x materials. A method of manufacturing a semiconductor device. The method of claim 2, The low dielectric film is a method of manufacturing a semiconductor device, characterized in that formed using a photosensitive film or a flexible material. The method of claim 1, The second mask insulating film pattern is a method of manufacturing a semiconductor device, characterized in that formed of at least one material selected from the group consisting of a nitride film, SiO ₂ , Al ₂ O ₃ and Ta ₂ O ₅ . The method of claim 1, The second interlayer insulating film, the first barrier insulating film and the second mask insulating film are removed by a chemical mechanical polishing process, a chemically enhanced polishing (CEP) process or an entire surface etching process. The method of claim 1, The low dielectric film may be removed by a plasma etching process using one gas arbitrarily selected from the group consisting of O ₂ , N ₂ , Ar, SO _x, and SF ₆ , or made of ACT, CLEAN-D, BOE, and solvent-based wet chemicals. Method for manufacturing a semiconductor device, characterized in that the removal using one selected from the group. The method of claim 1, The bit line may be formed by forming a conductive layer on the entire surface and then performing a CMP process, a CEP process, or an entire surface etching process. The method of claim 1, The second barrier insulating film pattern is formed by forming a second barrier insulating film on the entire surface, and then performing a CMP process, a CEP process or an entire surface etching process. The method of claim 1, The first barrier insulating pattern and the second barrier insulating pattern are formed of one selected from the group consisting of a nitride film, a SiON film, a SiON film containing a large amount of Si, a TiO ₂ film, an Al ₂ O ₃ film, and a Ta ₂ O ₅ film. Method for manufacturing a semiconductor device, characterized in that.