KR100685595B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

The present invention relates to a method for fabricating a semiconductor device, wherein in a dual damascene process using a low dielectric thin film, a groove is formed by etching a low thickness of the low dielectric thin film by a predetermined thickness during a via contact hole forming process, and the mask process for forming a trench is performed. After removing the photoresist poison formed in the groove, the trench is formed and the low dielectric thin film having the remaining thickness is removed to form the via contact hole, thereby improving the pattern reproducibility and preventing the lower metal wiring from being damaged. It is a technology to improve reliability.

Description

Manufacturing method for semiconductor device

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the prior art.

2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the prior art;

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

11, 31: lower insulating film 12, 32: first metal wiring

13, 33: nitride film 14, 34: first low dielectric film

15, 35: first oxide film 16, 36: second low dielectric film

17, 37: the second oxide film 18, 38: the first oil-based prevention film

19 and 39: first photoresist pattern 20: via contact hole

21, 41: second oil-based anti-film 22, 42: second photosensitive film pattern

23, 43: photoresist poison 25, 46: residual photoresist                 

40: home 44: trench

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly, to remove metal poisoning occurring in a via contact hole in a damascene process using an organic low dielectric material, thereby damaging a metal wiring exposed to the via contact hole. The present invention relates to a method for manufacturing a semiconductor device which prevents the product from becoming volatile.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a light source of deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 193 nm, to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. It has been developed, such as silico-migration method for implanting cone lowering the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a high integration of the device, and the size of the contact holes decreases, and the distance between the peripheral wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes provide misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the prior art, and illustrate a problem depending on the size of a via contact hole.

First, a lower insulating film 11 is formed on a semiconductor substrate (not shown) provided with a predetermined lower structure, and a first metal wiring 12 is formed on the lower insulating film 11.

Next, the nitride film 13, the first low dielectric thin film 14, the first oxide film 15, the second low dielectric thin film 16, the second oxide film 17, and the first oil barrier film 18 over the entire surface. ) Are formed sequentially. In this case, the nitride film 13 is 200-300 kPa, the first low dielectric film 14 is 5000-7000 kPa, the first oxide film 15 is 400-600 kPa, and the second low dielectric film 16 is 5000-500 kPa. At 7000 kPa, the second oxide film 17 is formed at 500 to 700 kPa, and the first oil-based anti-film 18 is formed to be 500 to 700 kPa.

Next, a first photoresist layer pattern 19 is formed on the first oil-based anti-foaming layer 18 to expose a portion to be via contact. The first photosensitive film pattern 19 is formed to a thickness of 7000 ~ 8000 Å. (See Figure 1A)

Next, the first oil-based anti-fogging film 18, the second oxide film 17, the second low dielectric film 16, the first oxide film 15, and the first bottom are etched using the first photoresist pattern 19 as an etch mask. The dielectric thin film 14 is etched to form the via contact hole 20.

Next, the first photoresist layer pattern 19 and the first oil barrier layer 18 are removed. (See FIG. 1B)

Next, a lamination structure of the second oil barrier film 21 and the second photoresist film pattern 22 exposing a portion intended as the second metal wiring on the entire surface is formed. In this case, the second oil barrier layer 21 and the second photoresist layer pattern 22 are also formed in the via contact hole 20. The second photoresist pattern 22 reacts with the first low dielectric thin film 14 and the second low dielectric thin film 16 to form a photoresist poison 23 on the via contact hole 20. (See Figure 1C)                         

Next, the second oxide film 17 and the second low dielectric thin film 16 are etched using the second photoresist pattern 22 as an etching mask to form a trench.

Next, the second photoresist layer pattern 22 and the second oil barrier layer 21 are removed. In the etching process for forming the trench, a fence is generated by the photoresist poison 23 as in the recess portion. (See FIG. 1D)

Thereafter, the nitride film 13 exposed to the bottom of the via contact hole 20 is etched to expose the first metal wiring 12. At this time, during the etching process, the second oxide layer 17 and the first oxide layer 15 are also removed to a predetermined thickness. (See Figure 1E)

2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the prior art, illustrating problems in accordance with the position of a pattern.

First, a via contact hole is formed by performing the process up to FIG. 1B, and a second oil barrier film 21 is formed on the entire surface.

Next, a second photoresist layer pattern 22 is formed on the second oil-based anti-foaming layer 21 to expose a portion intended to be a second metal wiring. In this case, the residual photoresist layer 25 may be formed at the bottom of the via contact hole. (See Figure 2A)

Next, a trench is formed by etching the second oil barrier film 21, the second oxide film 17, and the second low dielectric film 16 using the second photoresist pattern 22 as an etch mask. At this time, the residual photoresist film 25 and the second oil barrier film 21 at the bottom of the via contact hole are removed before the second oil barrier film 21 and the second oxide film 17 are etched. The metal wiring 12 may be damaged. (See Figure 2b)                         

In the method of manufacturing a semiconductor device according to the related art as described above, in the case of performing a dual damascene process using a low dielectric thin film, after the via contact hole is formed, the via contact hole is formed small so that the photosensitive film applied to form a subsequent trench is formed. After the etching process to generate a photoresist poison in the via contact hole by reacting with the low dielectric thin film to form a subsequent trench, a fence as shown in FIG. 1D is formed, and formed at the edge of the test pattern in the via contact hole as shown in FIG. 2A. When a small amount of the photoresist film is left in the via contact hole, the photoresist film and the organic anti-reflection film in the via contact hole are removed when the trench is etched to damage the lower wiring.

The present invention, in order to solve the above problems of the prior art, after removing the low dielectric thin film of a predetermined thickness when forming the via contact hole, and then removing the photoresist poison before the etching process for forming a trench, the low dielectric thin film of the remaining thickness The present invention provides a method of manufacturing a semiconductor device, which removes the via contact hole and simultaneously forms a trench to prevent damage to the first metal wiring of the bottom of the via contact hole, thereby improving operating characteristics and reliability of the device. There is this.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
Forming a first metal wiring on the semiconductor substrate on which a predetermined lower structure is formed;
Sequentially forming a nitride film, a first low dielectric thin film, a first oxide film, a second low dielectric thin film and a second oxide film on the entire surface thereof;
Forming a first photoresist pattern on the second oxide layer, the first photoresist layer pattern exposing a portion intended as a via contact;
Etching the second oxide film, the second low dielectric film, the first oxide film, and the first low dielectric film of a predetermined thickness by using the first photoresist pattern as an etching mask;
Removing the first photoresist pattern;
Forming a second photoresist pattern on the second oxide layer, the second photoresist pattern forming a second photoresist pattern, the second photoresist pattern being formed on the second oxide film and forming at least the groove;
Etching the photoresist poison and the second oxide layer using the second photoresist pattern as an etching mask to form a photoresist poison plug;
Forming a trench by etching the second low dielectric thin film using the second photoresist pattern as an etch mask, and removing the photoresist poison plug and the first low dielectric thin film together to form a via contact hole exposing the nitride film. and,
Removing the second photoresist pattern;
And removing the nitride film from the bottom of the via contact hole to expose the first metal wiring.

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Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

First, a lower insulating layer 31 is formed on a semiconductor substrate (not shown) provided with a predetermined lower structure, and a first metal wiring 32 is formed on the lower insulating layer 31.

Next, the nitride film 33, the first low dielectric film 34, the first oxide film 35, the second low dielectric film 36, the second oxide film 37, and the first oil-based anti-film film 38 are formed on the entire surface. ) Are formed sequentially. In this case, the nitride film 33 is 200-300 GPa, the first low dielectric thin film 34 is 5000-7000 GPa, the first oxide film 35 is 400-600 GPa, and the second low dielectric thin film 36 is 5000-300 GPa. At 7000 kPa, the second oxide film 37 is formed to be 500 to 700 mW, and the first oil-based anti-film 38 is formed to be 500 to 700 mW. Meanwhile, the first low dielectric thin film 34 and the second low dielectric thin film 36 may be used as an organic or inorganic low dielectric thin film. Here, when the first low dielectric thin film 34 and the second low dielectric thin film 36 are organic low dielectric thin films, SiLK or flare is used, and the first low dielectric thin film 34 and the second low dielectric dielectric film 34 are used. When the thin film 36 is an inorganic low dielectric thin film, HOSP, Coral, 3MS, 4MS or Black diamond may be used. In addition, the first low dielectric thin film 34 and the second low dielectric thin film 36 may be porous low dielectric materials.

The nitride film 33, the first oxide film 35, and the second oxide film 37 may be formed of a low dielectric film having a low dielectric constant like the SiC film.

Next, a first photoresist pattern 39 is formed on the first oil-based anti-fog film 38 to expose a portion of the via contact. The first photoresist pattern 39 is formed to a thickness of 7000 to 8000 Å. (See Figure 3A)

Next, the first photoresist layer 39, the second oxide layer 37, the second low dielectric layer 36, the first oxide layer 35 and a predetermined thickness are formed using the first photoresist layer pattern 39 as an etch mask. The first low dielectric thin film 34 is etched to form grooves 40. In this case, the reason for removing only the predetermined thickness of the first low dielectric thin film 34 is to remove fluorine remaining in the via contact hole when the oxide film is etched using the C _x F _y gas series.

Next, the first photoresist layer pattern 39 and the first oil barrier layer 38 are removed. (See Figure 3b)

Next, a stacked structure of the second oil barrier film 41 and the second photoresist film pattern 42 exposing a portion intended as the second metal wiring on the entire surface is formed. At this time, the second photoresist pattern 42 formed in the groove 40 reacts with the first low dielectric thin film 34 and the second low dielectric thin film 36 to fill the groove 20. 43). In this case, since the second oil-based anti-foaming film 41 is not formed in the groove 40, the step difference of the photoresist poison 43 may be reduced, and the first oil-based anti-fogging film 38 and the second oil-based yarn may be reduced. The prevention film 41 can also be omitted. (See Figure 3c)

Next, the second low dielectric thin film 36 is exposed by removing the second oxide film 37 and the photoresist poison 43 by using the second photoresist pattern 42 as an etching mask. At this time, the etching process is a second photosensitive film inside the groove 40 using a recipe for the etching selectivity of the second photosensitive film pattern 42 and the second oxide film 37 to form a photosensitive film poison plug type Will exist. The second oxide film 37 is etched using CF ₄ , O ₂ and Ar mixed gas. Here, the first oil-based anti-fogging film 38 and the second oil-based anti-fogging film 41 may be etched using the mixed gas.

Next, the second low dielectric thin film 36 is etched using the second photoresist pattern 42 as an etch mask to form a trench, and the second photoresist pattern inside the groove 40 and the first low dielectric of the remaining thickness. The thin film 34 is removed to form a via contact hole. In this case, the first oxide layer 35 and the nitride layer 33 are used as an etching barrier.

Next, the second photoresist layer pattern 42 and the second oil barrier layer 41 are removed. (See Figure 3E)

Next, the nitride metal layer 33 exposed to the via contact hole is removed to expose the first metal wire 32. At this time, the first oxide film 35 and the second oxide film 37 are also removed to a predetermined thickness. (See Figure 3f)

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second exemplary embodiment of the present invention, which illustrates a form in which a pattern is formed and a via contact hole may be formed according to size.

First, the process to FIG. 3B is performed.

Next, the second photoresist layer pattern 42 is formed. In this case, a residual photoresist layer 46 may be formed at the bottom of the groove 40. (See Figure 4A)

Next, the second oxide layer 37 is etched using the second photoresist pattern 42 as an etch mask. In the etching process, the remaining photoresist layer 46 at the bottom of the groove 40 is formed by using a recipe for the etching selectivity of the second oxide layer 37 to be 0.5 to 1.5 with respect to the second photoresist layer pattern 42. Can be removed. (See Figure 4b)

As described above, in the method of manufacturing a semiconductor device according to the present invention, in a dual damascene process using a low dielectric thin film, a groove is formed by etching a low thickness of the low dielectric thin film by a predetermined thickness during a via contact hole forming process. By removing the photoresist poison formed in the groove during the mask process, the trench is formed, and the low dielectric thin film having the remaining thickness is removed to form the via contact hole, thereby improving the pattern reproducibility and preventing the lower metal wiring from being damaged. There is an advantage of improving the process yield and reliability of the.

Claims (9)

Forming a first metal wiring on the semiconductor substrate on which a predetermined lower structure is formed; Sequentially forming a nitride film, a first low dielectric thin film, a first oxide film, a second low dielectric thin film and a second oxide film on the entire surface thereof; Forming a first photoresist pattern on the second oxide layer, the first photoresist layer pattern exposing a portion intended as a via contact; Etching the second oxide film, the second low dielectric film, the first oxide film, and the first low dielectric film of a predetermined thickness by using the first photoresist pattern as an etching mask; Removing the first photoresist pattern; Forming a second photoresist pattern on the second oxide layer, the second photoresist pattern forming a second photoresist pattern, the second photoresist pattern being formed on the second oxide film and forming at least the groove; Etching the photoresist poison and the second oxide layer using the second photoresist pattern as an etching mask to form a photoresist poison plug; Forming a trench by etching the second low dielectric thin film using the second photoresist pattern as an etch mask, and removing the photoresist poison plug and the first low dielectric thin film together to form a via contact hole exposing the nitride film. and, Removing the second photoresist pattern; And removing the nitride film of the bottom portion of the via contact hole to expose the first metal wiring. The method of claim 1, Wherein the first low dielectric thin film and the second low dielectric thin film are organic or inorganic low dielectric materials. The method of claim 2, The organic low dielectric material manufacturing method of a semiconductor device, characterized in that the SiLK or Flare is used. The method of claim 2, The inorganic low dielectric material is a manufacturing method of a semiconductor device, characterized in that selected from the group consisting of HOSP, Coral, 3MS, 4MS and Black diamond. The method of claim 1, The first low dielectric thin film and the second low dielectric thin film is a method of manufacturing a semiconductor device, characterized in that the porous low dielectric material. The method of claim 1, And the second oxide film is etched using any one selected from CF ₄ , O ₂ , Ar, and a mixed gas thereof. Forming a first metal wiring on the semiconductor substrate on which a predetermined lower structure is formed; Sequentially forming a nitride film, a first low dielectric film, a first oxide film, a second low dielectric film, a second oxide film, and a first dielectric prevention film on the entire surface; Forming a first photoresist layer pattern exposing a portion intended as a via contact on the first oil-based anti-fog layer; Etching the first oil-based anti-fogging film, the second oxide film, the second low dielectric film, the first oxide film, and the first low dielectric film of a predetermined thickness by using the first photoresist pattern as an etching mask; Removing the first photoresist pattern and the first oil barrier film; A second oil barrier layer pattern and a second photoresist pattern are formed on the second oxide layer, the second photoresist layer pattern exposing a predetermined portion of the second metal wiring, and the photoresist poison is formed as the second photoresist layer pattern and fills at least the groove. Process to make it possible, Etching the photoresist poison and the second oxide layer using the second photoresist pattern as an etching mask to form a photoresist poison plug; Forming a trench by etching the second low dielectric thin film using the second photoresist pattern as an etch mask, and removing the photoresist poison plug and the first low dielectric thin film together to form a via contact hole exposing the nitride film. and, Removing the second photoresist layer pattern and the second oil barrier layer pattern; And removing the nitride film of the bottom portion of the via contact hole to expose the first metal wiring. The method of claim 7, wherein The process of removing the _first oil barrier film and the second oil barrier film pattern is etched using any one selected from CF ₄ , O ₂ , Ar, and a mixture thereof. . The method of claim 1, The nitride film, the first oxide film and the second oxide film is a method of manufacturing a semiconductor device, characterized in that formed by a low dielectric film containing SiC.

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