KR20050000002A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20050000002A KR20050000002A KR1020030040532A KR20030040532A KR20050000002A KR 20050000002 A KR20050000002 A KR 20050000002A KR 1020030040532 A KR1020030040532 A KR 1020030040532A KR 20030040532 A KR20030040532 A KR 20030040532A KR 20050000002 A KR20050000002 A KR 20050000002A
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- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 게이트전극 사이를 메우는 층간절연막의 갭필을 효과적으로 실시하여 게이트전극간에 보이드 생성을 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a method of manufacturing a semiconductor device capable of effectively forming a gap fill between an interlayer insulating film filling a gate electrode to prevent voids between the gate electrodes to improve process yield and device reliability. It is about.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
이러한 감광막 패턴의 분해능(R)은 감광막 자체의 재질이나 기판과의 접착력등과도 밀접한 연관이 있으나, 일차적으로는 사용되는 축소노광장치의 광원 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture; NA, 개구수)에 반비례한다.The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.
[R=k*λ/NA, R=해상도, λ= 광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 라인/스페이스 패턴의 경우 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해서는 이보다 파장이 더 작은 원자외선(deep ultra violet; DUV), 예를들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하여야 한다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.
또한 축소노광장치와는 별도로 공정 상의 방법으로는 노광마스크(photo mask)로서 위상반전마스크(phase shift mask)를 사용하는 방법이나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법이나, 두층의 감광막 사이에 에스.오.지(spin on glass; SOG)등의 중간층을 개재시킨 삼층레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.
또한 상하의 도전배선을 연결하는 콘택홀은 상기에서의 라인/스페이스 패턴에 비해 디자인룰이 더 크게 나타나는데, 소자가 고집적화 되어감에 따라 자체의크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택 형성 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소돠거나, 여유가 전혀없이 공정을 진행하여야하는 어려움이 있다.In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above-described line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wiring are reduced. The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.
이러한 콘택홀은 홀간의 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.
종래 기술에 따른 반도체소자는 하드마스크층과 중첩되어 있는 게이트전극을 형성한 후에 BPSG 등으로 층간절연막을 도포한 후, 열처리하여 리플로우시켜 게이트전극 사이의 공간을 메우게 된다.In the semiconductor device according to the related art, after forming a gate electrode overlapping with a hard mask layer, an interlayer insulating layer is coated with BPSG or the like, and then heat-treated to reflow to fill the space between the gate electrodes.
여기서 소자의 고집적화 경향에 따라 게이트 선폭과 간격이 감소되고, 게이트전극 물질의 저저항화를 위하여 게이트전극으로 실리사이드나 텅스텐등의 난식각성 물질을 사용하게 되어 하드마스크층의 두께가 증가되어 더욱 종횡비가 증가하게되었다.Here, the gate line width and spacing are reduced according to the high integration tendency of the device, and an egg etching material such as silicide or tungsten is used as the gate electrode in order to reduce the resistance of the gate electrode material. Increased.
상기와 같은 종래 기술에 따른 반도체소자는 층간절연막이 리플로우 공정 만으로는 게이트전극 사이 공간을 원활하게 메우지 못하고 오버행에 의해 보이드가 발생되기 쉬우며, 이렇게 발생된 보이드는 후속 콘택 공정에서 기판을 손상시키는 원인이 되어 불량이 발생되거나, 소자의 신뢰성을 떨어뜨리는 문제점이 있다.In the semiconductor device according to the prior art as described above, the interlayer insulating film does not fill the space between the gate electrodes smoothly only by the reflow process, but is easily caused by overhang, and the generated voids damage the substrate in the subsequent contact process. There is a problem that a defect is caused as a cause, or the reliability of the device is degraded.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 일차로 일부 두께만 형성한 층간절연막을 리플로우 시켜 게이트전극 사이의 간격을 일부 메우고 후속으로 이차 층간절연막을 형성하여 원활하게 게이트전극 사이 공간을 메워 보이드 형성을 방지함으로써, 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to first smoothly reflow an interlayer insulating film having only a partial thickness to fill a gap between the gate electrodes, and subsequently form a secondary interlayer insulating film to smoothly gate the interlayer insulating film. The present invention provides a method of manufacturing a semiconductor device that can fill a space between electrodes and prevent void formation, thereby improving process yield and device reliability.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 제조공정도.1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 반도체기판 12 : 소자분리 산화막10: semiconductor substrate 12: device isolation oxide film
14 : 게이트 절연막 16 : 게이트전극14 gate insulating film 16 gate electrode
18 : 하드마스크층 20 : 절연막 스페이서18 hard mask layer 20 insulating film spacer
22 : 제1층간절연막 24 : 제2층간절연막22: first interlayer insulating film 24: second interlayer insulating film
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
반도체기판상에 게이트절연막을 형성하는 공정과,Forming a gate insulating film on the semiconductor substrate;
상기 게이트절연막상에 하드마스크층 패턴과 중첩되어있는 게이트전극을 형성하는 공정과,Forming a gate electrode overlapping the hard mask layer pattern on the gate insulating film;
상기 게이트전극과 하드마스크층 패턴의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the gate electrode and the hard mask layer pattern;
상기 구조의 전표면에 열처리에 유동성을 가지는 물질로 제1층간절연막을 형성하되, 게이트전극 사이 거리를 메우지 않는 두께로 형성하는 공정과,Forming a first interlayer insulating film of a material having fluidity for heat treatment on the entire surface of the structure, but having a thickness not filling the distance between the gate electrodes;
상기 제1층간절연막을 열처리로 리플로우시켜 게이트전극 사이의 공간을 메우는 공정과,Reflowing the first interlayer insulating film by a heat treatment to fill the space between the gate electrodes;
상기 구조의 전표면에 제2층간절연막을 형성하여 게이트전극 사이의 공간을 메우는 공정을 구비함에 있다.A second interlayer insulating film is formed on the entire surface of the structure to fill the space between the gate electrodes.
또한 본 발명의 다른 특징은, 상기 제1층간절연막은 게이트전극 사이 거리의 5∼30% 두께로서, BPSG, PSG, TEOS 또는 USG로 형성하고, 상기 열처리 공정전에 상기 하드마스크층 상부의 제1층간절연막을 CMP 방법으로 제거하여 게이트전극들의 사이에만 제1층간절연막이 남도록하는 공정을 구비하며, 상기 CMP 공정은 슬러리를 산화막과 질화막간에 선택비가 있는 CeO2계열의 고선택비 슬러리로 연마하여 질화막에서 식각이 중단되도록하고, 상기 열처리 공정은 스팀 분위기에서 600∼900℃, 10∼30분간 실시하며, 상기 열처리 공정전에 HF를 이용한 스크러빙 방식을 세정공정을 실시하고, 상기 제2층간절연막은 4000∼7000Å 두께로 형성하는 것을 특징으로한다.In another aspect of the present invention, the first interlayer insulating film is formed of BPSG, PSG, TEOS, or USG, having a thickness of 5 to 30% of the distance between gate electrodes, and is formed between the first layers on the hard mask layer before the heat treatment process. insulating film is removed by CMP method, and a step of a first interlayer insulating film to remain only between their gate electrode, the CMP process is in the nitride film is polished by the slurry at a high selectivity slurry of CeO 2 based on selection ratio between the oxide film and the nitride film Etching is stopped, and the heat treatment step is performed at 600 to 900 ° C. for 10 to 30 minutes in a steam atmosphere. It is characterized by forming in thickness.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 제조공정도이다.1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 반도체기판(10)상에 소자분리 산화막(12)을 형성하여 활성영역을 정의하고, 게이트절연막(14)을 형성한 후, 질화막 재질의 하드마스크층(18) 패턴과 중첩되어있는 게이트전극(16)을 형성하고, 상기 게이트전극(16)과 하드마스크층(18) 패턴의 측벽에 절연막 스페이서(20)를 형성한다. 여기서 상기 게이트전극(16)은 다결정실리콘층과 중첩된 텅스텐이나 텅스텐실리사이드의 적층구조로 형성한다. (도 1a 참조).First, an isolation region 12 is formed on the semiconductor substrate 10 to define an active region, a gate insulating layer 14 is formed, and a gate electrode overlapped with a pattern of a hard mask layer 18 made of nitride. An insulating layer spacer 20 is formed on sidewalls of the pattern of the gate electrode 16 and the hard mask layer 18. The gate electrode 16 may be formed of a stacked structure of tungsten or tungsten silicide that overlaps the polysilicon layer. (See FIG. 1A).
그후, 상기 구조의 전포면에 제1층간절연막(22)을 형성하되, 게이트전극(16)간격의 30% 이하, 바람직하게는 5∼30% 정도 두께로 형성하여 오버행에 의한 보이드 생성을 방지하며, 열처리에 유동성을 가지는 물질, 예를 들어 BPSG, PSG, TEOS 또는 USG등으로 형성한다. (도 1b참조).Thereafter, the first interlayer insulating film 22 is formed on the entire fabric surface of the structure, and the thickness of the gate electrode 16 is less than 30%, preferably about 5 to 30%, to prevent void formation due to overhang. It is formed of a material having fluidity in heat treatment, for example, BPSG, PSG, TEOS or USG. (See FIG. 1B).
그다음 상기 하드마스크층(18) 상부의 제1층간절연막(22)을 CMP 방법으로 제거하여 게이트전극(16)들의 사이에만 제1층간절연막(22)이 남도록한다. 여기서 상기 CMP 공정은 슬러리를 산화막과 질화막간에 선택비가 있는 CeO2계열의 고선택비 슬러리로 연마하여 질화막에서 식각이 중단되도록한다. (도 1c 참조).Then, the first interlayer insulating film 22 on the hard mask layer 18 is removed by the CMP method so that the first interlayer insulating film 22 remains only between the gate electrodes 16. Here, the CMP process grinds the slurry into a CeO 2 series high selectivity slurry having a selectivity between the oxide film and the nitride film so that the etching is stopped in the nitride film. (See FIG. 1C).
그후, 상기 제1층간절연막(22)을 열처리하여 리플로우시켜 게이트전극(16) 사이 공간의 하부를 채우게한다. 여기서 상기 열처리 공정은 층간절연막이 BPSG막인 경우 600∼900℃에서 10∼30분간 실시하며, 열처리 방식은 스팀을 이용한 방식으로 실시하며, 열처리 전에 HF를 이용한 스크러빙 방식을 세정을 실시할 수도 있다. (도 1d 참조).Thereafter, the first interlayer insulating film 22 is heat-treated to reflow to fill the lower portion of the space between the gate electrodes 16. Here, the heat treatment process is performed for 10 to 30 minutes at 600 ~ 900 ℃ when the interlayer insulating film is a BPSG film, the heat treatment method is performed by the method using steam, scrubbing method using HF may be washed before the heat treatment. (See FIG. 1D).
그다음 상기 구조의 전표면에 제2층간절연막(24)을 4000∼7000Å 정도 두께로 형성하여 게이트전극(16) 사이 공간을 완전히 메우되, 제2층간절연막(24)은 고밀도 플라즈마 산화막이나 BPSG로 형성한다. (도 1e 참조).Then, the second interlayer insulating film 24 is formed to a thickness of 4000 to 7000 에 on the entire surface of the structure to completely fill the space between the gate electrodes 16, and the second interlayer insulating film 24 is formed of high density plasma oxide film or BPSG. do. (See FIG. 1E).
그후 상기 제2층간절연막(24)의 상부를 CMP 방법으로 식각하여 평탄화시킨다. 이때 CMP 공정은 SiO2계 연마입자를 가지는 pH 7 이상의 슬러리를 사용하며, 제2층간절연막(24)이 BPSG 막인 경우 평탄화를 열처리 리플로우 방법으로 실시할수도 있으며, 이 공정은 스팀 분위기에서 600∼900℃에서 10∼30분간 실시하며, 열처리후 황산과 과산화수소수를 이용한 크리닝 공정을 실시할 수도 있다. (도 1f 참조).Thereafter, the upper portion of the second interlayer insulating film 24 is etched and planarized by a CMP method. In this case, the CMP process uses a slurry having a pH of 7 or more having SiO 2 -based abrasive particles, and when the second interlayer insulating film 24 is a BPSG film, planarization may be performed by a heat treatment reflow method. 10 to 30 minutes at 900 ℃, after the heat treatment may be performed using a sulfuric acid and hydrogen peroxide cleaning process. (See FIG. 1F).
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은 게이트전극 사이의 공간을 메우는 층간절연막을 이중층으로 형성하되, 하부의 층간절연막을 형성한 후에 이를 리플로우시켜 종횡비를 감소시킨후, 이차로 층간절연막을 형성하여 게이트전극들 사이에 보이드 생성을 방지하였으므로, 보이드에 의한 후속 공정 불량이 방지되어 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing the semiconductor device according to the present invention, the interlayer insulating film filling the space between the gate electrodes is formed as a double layer, and after forming the lower interlayer insulating film, the aspect ratio is reduced by reflowing the second insulating layer. Since an interlayer insulating film is formed to prevent voids between gate electrodes, subsequent process defects caused by voids can be prevented, thereby improving process yield and device reliability.
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