KR20050041551A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20050041551A KR20050041551A KR1020030076760A KR20030076760A KR20050041551A KR 20050041551 A KR20050041551 A KR 20050041551A KR 1020030076760 A KR1020030076760 A KR 1020030076760A KR 20030076760 A KR20030076760 A KR 20030076760A KR 20050041551 A KR20050041551 A KR 20050041551A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 36
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 description 52
- 238000005530 etching Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 랜딩플러그 형성 공정에서 층간절연막상에 상기 층간절연막 보다 습식식각율이 낮은 희생절연막을 도포하고, 후속 공정을 진행하여 게이트전극상의 하드마스크층이 손상되는 것을 방지하였으므로, 하드마스크층의 두께를 감소시킬 수 있어 갭필에 유리하고, 콘택 바닥 CD 확보가 용이하여 공정여유도 및 콘택 저항 특성이 향상되고, 하드마스크층 손상에 따른 배선 단락도 방지되어 공정수율 및 소자의 신뢰성을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the landing plug forming process, a sacrificial insulating film having a lower wet etching rate than that of the interlayer insulating film is coated on the interlayer insulating film, and a subsequent process is performed to damage the hard mask layer on the gate electrode. Since the thickness of the hard mask layer can be reduced, the thickness of the hard mask layer can be reduced, which is advantageous for the gap fill, and the contact bottom CD can be easily secured, so that the process margin and contact resistance characteristics are improved, and the wiring short circuit due to the damage of the hard mask layer is also prevented. Yield and reliability of the device can be improved.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 랜딩플러그 형성 공정시 하드마스크층의 손상을 방지하고, 랜딩플러그 사이의 절연막을 효과적으로 보호하여 공정여유도를 증가시킬 수 있는 반도체소자의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device which can increase the process margin by preventing damage to the hard mask layer during the landing plug forming process and effectively protecting the insulating film between the landing plugs. It is about.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 미세 패턴 형성을 위하여는 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다. The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology. For the formation of fine patterns, photoresist patterns of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are used in the manufacturing process of semiconductor devices. Micronization is a must.
이러한 감광막 패턴의 분해능(R)은 감광막 자체의 재질이나 기판과의 접착력 등과도 밀접한 연관이 있으나, 일차적으로는 사용되는 축소노광장치의 광원 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture; NA, 개구수)에 반비례한다. [R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수]The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device. [R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되는데, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 라인/스페이스 패턴의 경우 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해서는 이보다 파장이 더 작은 원자외선(deep ultra violet; DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하여야 한다. Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV) wavelengths, for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.
또한 축소노광장치와는 별도로 공정 상의 방법으로는 통상의 노광마스크(photo mask) 대신에 위상반전마스크(phase shift mask)로 사용하는 방법이나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법이나, 두층의 감광막 사이에 에스.오.지(spin on glass; SOG)등의 중간층을 개재시킨 삼층레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다. In addition to the reduction exposure apparatus, a process method may be used as a phase shift mask instead of a conventional photo mask, or a separate thin film may be formed on the wafer to improve image contrast. A tri-layer resister (hereinafter referred to as TLR) is formed by interpolating a CEL method or an intermediate layer such as spin on glass (SOG) between two photoresist layers. Method or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.
더욱이 상하의 도전배선을 연결하는 콘택홀은 상기에서의 라인/스페이스 패턴에 비해 디자인 룰이 더 크게 나타나는데, 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가됨에 따라 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다. In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced. As the aspect ratio, which is a ratio of depth, increases, highly integrated semiconductor devices having multilayer conductive wirings require accurate and strict alignment between masks in a manufacturing process to form contacts, thereby reducing process margin. .
이러한 콘택홀은 홀간의 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성하여야하므로 더욱 공정마진이 감소되어 소자의 고집적화를 방해한다. These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, Since the mask must be formed in consideration of factors such as registration between the masks, the process margin is further reduced to prevent high integration of the device.
이와 같이 콘택을 효과적으로 형성하기 위하여 자기정렬 콘택 공정을 사용하게 되며, 자기정렬 콘택의 발전된 형태인 랜딩플러그를 사용하게 되며, 초기 단계에서는 홀형의 랜딩플러그를 형성하였으나, 집적도가 향상됨에 따라 패턴닝과 오버랩 난이도가 증가하여 섬형 랜딩플러그를 사용하게 된다. In order to form a contact effectively, a self-aligned contact process is used, and a landing plug, which is an advanced form of self-aligned contact, is used.In the initial stage, a hole-type landing plug was formed, The overlap difficulty is increased to use the island landing plug.
그러나 섬형 랜딩플러그는 랜딩플러그의 분리가 층간절연막 뿐 아니라 게이트전극도 이용하게 되는데, 이 공정에서 게이트전극 상부의 하드마스크층 패턴이 손상되게 되어 하드마스크층의 두께가 증가되어 갭필이 어려워지고, 하드마스크층 손실을 보상하기 위한 다른 공정을 진행하영야하는 등 다른 문제점을 일으키고 있다. However, in the island-type landing plug, the landing plug is separated from the interlayer insulating layer as well as the gate electrode. In this process, the hard mask layer pattern on the gate electrode is damaged and the thickness of the hard mask layer is increased, making the gap fill difficult. Other problems arise, such as the need to proceed with other processes to compensate for mask layer losses.
최근에는 포토 기술의 발전에 따라 패턴닝 이나 오버랩 공정에서 여유가 생기게 되어 다시 홀형 랜딩플러그를 형성하게 되었다. Recently, with advances in photo technology, there is room for patterning or overlapping processes to form hole landing plugs again.
도 1a 내지 도 1e는 종래 기술에 따른 반도체소자의 제조 공정도로서 홀형 랜딩플러그의 예이다. 1A to 1E are examples of a hole type landing plug as a manufacturing process diagram of a semiconductor device according to the prior art.
먼저, 실리콘 웨이퍼 등의 반도체기판(10)상에 얕은 트랜치의 소자분리산화막(도시되지 않음)과 게이트산화막(12)을 형성하고, 그 상부에 질화막 재질의 하드마스크층(16) 패턴과 중첩되어있는 게이트전극(14)을 형성하고, 상기 구조의 전표면에 콘택홀 형성시의 식각장벽층(18)을 질화막등의 재질로 형성한다. 여기서 상기 하드마스크층(16)은 게이트 패턴닝 공정에서 상부가 일부 제거되어 진다. (도 1a 참조). First, a shallow isolation device isolation oxide film (not shown) and a gate oxide film 12 are formed on a semiconductor substrate 10 such as a silicon wafer, and overlap with the hard mask layer 16 pattern made of a nitride film thereon. The gate electrode 14 is formed, and the etch barrier layer 18 at the time of forming the contact hole is formed on the entire surface of the structure by using a material such as a nitride film. The hard mask layer 16 may be partially removed from the gate patterning process. (See FIG. 1A).
그다음 상기 구조의 전표면에 층간절연막(20)을 형성하여 평탄화한 후, (도 1b 참조), 홀형 랜딩플러그 마스크를 이용하여 상기 층간절연막(20)을 사진식각하여 랜딩플러그용 콘택홀(22)을 형성한다. 여기서 상기 식각 공정은 경사가 심한 콘택 식각이므로 바닥 CD를 확보하기 위해서는 층간절연막(20)의 두께가 적을수록 유리하며, 이는 게이트전극(14)과 하드마스크층(16)의 두께가 작아야 가능하고, 게이트전극의 두께는 소자의 특성에 중요한 용인이므로 이를 줄이기는 어려우므로 하드마스크층(16)의 두께를 감소시킬 필요가 있다. (도 1c 참조). Then, the interlayer insulating film 20 is formed on the entire surface of the structure and planarized (see FIG. 1B). Then, the interlayer insulating film 20 is etched by using a hole-type landing plug mask to photograph the landing plug contact hole 22. To form. Here, the etching process is an inclined contact etching, so that the smaller the thickness of the interlayer insulating film 20 to secure the bottom CD, the smaller the thickness of the gate electrode 14 and the hard mask layer 16, Since the thickness of the gate electrode is an important factor in the characteristics of the device, it is difficult to reduce the thickness, so it is necessary to reduce the thickness of the hard mask layer 16. (See FIG. 1C).
그후, 상기 콘택을 위하여 반도체기판(10)상의 식각장벽층(18)을 제거하여 반도체기판(10)을 노출시킨다. 여기서 랜딩플러그의 바닥 CD 확보와 접촉 저항 개선을 위하여 상기 콘택홀(22) 형성후 세정, 상기 식각장벽층(18) 식각후 세정, 랜딩플러그 다결정실리콘층 증착전 세정등의 습식세정 공정을 거치게 되어 상기 층간절연막(20)이 상당 부분 손상된다. (도 1d 참조).Thereafter, the etch barrier layer 18 on the semiconductor substrate 10 is removed for the contact to expose the semiconductor substrate 10. In order to secure the bottom CD of the landing plug and improve the contact resistance, the contact hole 22 is cleaned after the formation of the contact hole 22, the etching barrier layer 18 is cleaned after the etching, and the landing plug polycrystalline silicon layer is cleaned before the deposition. The interlayer insulating film 20 is substantially damaged. (See FIG. 1D).
그다음 상기 구조의 전표면에 랜딩플러그용 다결정실리콘층(24)을 도포하여 상기 콘택홀(22)을 메우고, 랜딩플러그 분리를 위하여 에치백 공정을 진행하여 다결정실리콘층(24) 패턴으로된 랜딩플러그를 형성한다. 여기서 상기 다결정실리콘층(24)의 에치백 공정시 하드마스크층(16)도 상당 부분 손상되게 된다. Then, the landing plug polycrystalline silicon layer 24 is applied to the entire surface of the structure to fill the contact hole 22, and the etch back process is performed to separate the landing plug, and the landing plug formed of the polycrystalline silicon layer 24 pattern. To form. In this case, the hard mask layer 16 is also substantially damaged during the etch back process of the polysilicon layer 24.
상기와 같이 종래 기술에 따른 반도체소자의 제조방법은 랜딩플러그 형성 공정에서 게이트전극 상부의 하드마스크층이 상당 부분 손상되므로 이를 보상하기 위하여 그 두께를 증가시켜야하나, 이는 공정 전체의 요구에 부합하지 않아, 실행하기 어렵고, 콘택홀 형성을 위한 식각 및 세정 공정시 층간절연막의 다른 부분들도 손상되어 절연 특성이 저하되며, 랜딩플러그 분리 공정에서 하드마스크층이 손상되어 다른 배선과의 단락 불량 발생이 우려되는 등의 문제점이 있다. As described above, in the method of manufacturing a semiconductor device according to the related art, since the hard mask layer on the gate electrode is substantially damaged in the landing plug forming process, the thickness thereof must be increased to compensate for this, but this does not meet the requirements of the entire process. , It is difficult to carry out, and other parts of the interlayer insulating film are damaged during the etching and cleaning process for forming the contact hole, and the insulating property is deteriorated, and the hard mask layer is damaged during the landing plug separation process, which may cause short circuit defects with other wirings. There is a problem such as being.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 랜딩플러그 형성시 층간절연막의 손상을 방지하고, 하드마스크층을 얇게 형성하여도 소자의 절연 특성이 우수하며, 다른 배선들간의 단락도 방지할 수 있는 반도체소자의 제조방법 제공함에 있다. The present invention has been made to solve the above problems, and an object of the present invention is to prevent damage to the interlayer insulating film when forming the landing plug, and even if a hard mask layer is formed thin, the insulating property of the device is excellent, and between different wirings. The present invention provides a method for manufacturing a semiconductor device that can also prevent a short circuit.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 콘택 제조방법의 특징은, Features of the contact manufacturing method of the semiconductor device according to the present invention for achieving the above object,
반도체기판 상에 게이트산화막을 형성하는 공정과, Forming a gate oxide film on the semiconductor substrate;
상기 게이트산화막상에 하드마스크층 패턴과 중첩되어있는 게이트전극을 형성하는 공정과, Forming a gate electrode overlapping the hard mask layer pattern on the gate oxide film;
상기 구조의 전표면에 층간절연막을 형성하는 공정과, Forming an interlayer insulating film on the entire surface of the structure;
상기 층간절연막상에 희생절연막을 형성하되, 상기 층간절연막 보다 습식식각율이 낮은 물질로 형성하는 공정과, Forming a sacrificial insulating film on the interlayer insulating film and forming a material having a lower wet etching rate than the interlayer insulating film;
상기 희생절연막과 층간절연막을 랜딩플러그 콘택 마스크를 사용하느 사진식각오정으로 패턴닝하여 반도체기판을 노출시키는 콘택홀을 형성하는 공정과, Forming a contact hole exposing the semiconductor substrate by patterning the sacrificial insulating film and the interlayer insulating film with photolithographic misalignment using a landing plug contact mask;
상기 콘택홀을 메우는 랜딩플러그를 형성하는 공정을 구비함에 있다. And forming a landing plug filling the contact hole.
또한 본 발명의 다른 특징은, 상기 층간절연막 형성전에 전표면에 식각장벽층을 형성하는 공정을 구비하거나, 상기 층간절연막은 BPSG, PSG, APL 또는 SOD 로 형성하고, 상기 층간절연막은 500∼10000Å 두께로 형성하며, 상기 희생절연막은 HDP 산화막, HTO 또는 열산화막으로 형성하고, 상기 희생절연막은 500∼2000Å 두께로 형성하는 것을 특징으로 한다. In another aspect, the present invention provides a step of forming an etch barrier layer on the entire surface of the interlayer insulating film before the interlayer insulating film is formed, or the interlayer insulating film is formed of BPSG, PSG, APL, or SOD, and the interlayer insulating film is 500 to 10000 Å thick. Wherein the sacrificial insulating film is formed of an HDP oxide film, an HTO or a thermal oxide film, and the sacrificial insulating film is formed to have a thickness of 500 to 2000 GPa.
이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 제조공정도이다. 2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 실리콘 웨이퍼 등의 반도체기판(30)상에 게이트산화막(32)과 게이트전극(34) 및 하드마스크층(36) 패턴을 형성한 후, 상기 구조의 전표면에 식각장벽층(38)을 형성한다. 여기서 상기 하드마스크층(36)과 식각장벽층(38)은 질화막 재질로 형성한다. First, the gate oxide layer 32, the gate electrode 34 and the hard mask layer 36 pattern are formed on a semiconductor substrate 30 such as a silicon wafer, and then the etch barrier layer 38 is formed on the entire surface of the structure. Form. Here, the hard mask layer 36 and the etching barrier layer 38 are formed of a nitride film material.
그다음 상기 구조의 전표면에 층간절연막(40)을 도포하여 평탄화시킨 후, 상기 층간절연막(40)의 상부를 CMP 식각하여 층간절연막(40)의 높이를 하드마스크층(36)에 맞추고, 그 상부에 희생절연막(41)을 형성한다. 여기서 상기 층간절연막(40)은 BPSG, PSG, APL 또는 SOD 등으로, 500∼10000Å 정도 두께이며, 상기 희생절연막(41)은 상기 층간절연막(40)에 비해 습식 식각 속도가 느린 물질, 예를 들어 HDP 산화막이나 HTO 또는 열산화막 등으로 500∼2000Å 정도 두께이다. (도 2a 참조). Then, the interlayer insulating film 40 is coated and planarized on the entire surface of the structure, and the upper portion of the interlayer insulating film 40 is etched by CMP to adjust the height of the interlayer insulating film 40 to the hard mask layer 36. A sacrificial insulating film 41 is formed on the substrate. Here, the interlayer insulating film 40 is made of BPSG, PSG, APL, or SOD. The interlayer insulating film 40 has a thickness of about 500 to 10000 μs, and the sacrificial insulating film 41 has a wet etching rate that is slower than that of the interlayer insulating film 40, for example. It is about 500-2000 mm thick with HDP oxide film, HTO or thermal oxide film. (See FIG. 2A).
그후, 홀형 랜딩플러그 콘택 마스크를 사용하는 사진식각공정으로 상기 희생절연막(41)과 층간절연막(40)을 순차적으로 패턴닝하여 콘택홀(42)을 형성한다. 여기서 식각후 세정을 바닥 CD를 충분히 확보할 수 있을 정도로 충분히 실시하여도 식각율이 낮은 희생절연막(41)은 거의 손상되지 않으며, 콘택홀(42) 부분의 희생산화막(36)의 일부가 손상된다. (도 2b 참조). Thereafter, the sacrificial insulating film 41 and the interlayer insulating film 40 are sequentially patterned in a photolithography process using a hole landing plug contact mask to form a contact hole 42. Here, even after the etching is sufficiently performed to sufficiently secure the bottom CD, the sacrificial insulating film 41 having a low etching rate is hardly damaged, and a part of the sacrificial oxide film 36 in the contact hole 42 is damaged. . (See FIG. 2B).
그다음 상기 반도체기판(10)상의 식각장벽층(38)을 제거한다. 이때 상기 희생절연막(41)의 일부 또는 전부가 제거되며, 콘택홀(42)간 층간절연막(40)은 손상되지 않는다. (도 2c 참조). Then, the etch barrier layer 38 on the semiconductor substrate 10 is removed. At this time, part or all of the sacrificial insulating film 41 is removed, and the interlayer insulating film 40 between the contact holes 42 is not damaged. (See FIG. 2C).
그후, 상기 구조의 전표면에 랜딩플러그용 다결정실리콘층(44)을 도포하여 상기 콘택홀(42)을 메운 후, 이를 에치백하여 콘택홀(42) 별로 분리시켜 다결정실리콘층(44) 패턴으로된 랜딩플러그를 형성한다. 여기서 상기 층간절연막(40)이 하드마스크층(36) 보다 어느정도 , 예를 들어 100∼2000Å 정도 두껍게 남아 있어 하드마스크층(36)의 손상이 적어진다. (도 2d 참조). Thereafter, the landing plug polycrystalline silicon layer 44 is applied to the entire surface of the structure to fill the contact hole 42, and then etched back to separate the contact holes 42 to form the polysilicon layer 44 pattern. Form a landing plug. Here, the interlayer insulating film 40 remains somewhat thicker than the hard mask layer 36, for example, about 100 to 2000 micrometers, so that the damage of the hard mask layer 36 is reduced. (See FIG. 2D).
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 랜딩플러그 형성 공정에서 층간절연막상에 상기 층간절연막 보다 습식식각율이 낮은 희생절연막을 도포하고, 후속 공정을 진행하여 게이트전극상의 하드마스크층이 손상되는 것을 방지하였으므로, 하드마스크층의 두께를 감소시킬 수 있어 갭필에 유리하고, 콘택 바닥 CD 확보가 용이하여 공정여유도 및 콘택 저항 특성이 향상되고, 하드마스크층 손상에 따른 배선 단락도 방지되어 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다. As described above, in the method of manufacturing a semiconductor device according to the present invention, a sacrificial insulating film having a wet etching rate lower than that of the interlayer insulating film is coated on the interlayer insulating film in a landing plug forming process, and a subsequent process is performed to perform a hard mask on the gate electrode. Since the layer is prevented from being damaged, the thickness of the hard mask layer can be reduced, which is advantageous for the gap fill, and it is easy to secure the contact bottom CD, thereby improving the process margin and contact resistance characteristics, and the wiring short circuit caused by the damage of the hard mask layer. There is an advantage that can be prevented to improve the process yield and the reliability of the device.
도 1a 내지 도 1e는 종래 기술에 따른 반도체소자의 제조공정도. 1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 제조공정도. 2a to 2d is a manufacturing process diagram of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10, 30 : 반도체기판 12, 32 : 게이트산화막10, 30: semiconductor substrate 12, 32: gate oxide film
14, 34 : 게이트전극 16, 36 : 하드마스크층14, 34: gate electrode 16, 36: hard mask layer
18, 38 : 식각장벽층 20, 40 : 층간절연막18, 38: etching barrier layer 20, 40: interlayer insulating film
22, 42 : 콘택홀 24, 44 : 다결정실리콘층22, 42: contact hole 24, 44: polysilicon layer
41 : 희생절연막 41: sacrificial insulating film
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