KR20050052586A - Manufacturing method for semicondutor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in order to smoothly form a bit line contact hole in a cell region and a peripheral circuit region, a hard mask layer on the peripheral circuit region is formed and a gate electrode is formed thereon. Since the landing plug is formed in the cell region and the bit line contact hole is formed, the difference in etching depth between the cell region and the peripheral circuit region is reduced during the bit line contact hole etching process, and the heterogeneity of the etch material is removed to remove the peripheral circuit. The damage of the semiconductor substrate in contact with the bit line in the region is reduced, the etching process conditions are easily controlled, and the possibility of defective pattern is reduced, thereby improving process yield and device reliability.

Description

Manufacturing method for semiconductor device {Manufacturing method for semicondutor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the bit line contact hole is smoothly formed in the cell region and the peripheral circuit region, thereby reducing the difference in etching depth between the cell region and the peripheral circuit region during the etching process. The present invention relates to a method for manufacturing a semiconductor device in which the damage of the semiconductor substrate in contact with the bit line is reduced and the etching process conditions are easily controlled.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

1 is a cross-sectional view of a semiconductor device according to the prior art, which will be described below with reference to the manufacturing method.

First, a gate oxide film 12 is formed on the semiconductor substrate 10 including the cell region I and the peripheral circuit region II, and overlaps the hard mask 16 layer pattern on the gate oxide layer 12. After the gate electrode 14 is formed, an insulating spacer 18 made of nitride film is formed on the sidewalls of the hard mask layer 16 pattern and the gate electrode 14, and then the first surface is formed on the entire surface of the structure. The interlayer insulating film 20 is applied and then planarized.

The gate electrode is a low-resistance structure in which W or tungsten silicide is stacked on polycrystalline silicon, and in order to pattern the gate electrode, the thickness of the hard mask layer pattern is increased to increase the aspect ratio.

Then, the first interlayer insulating film 20 is patterned by a photolithography process using an etching mask for contact plugs to form contact holes, and the contact plugs 22 filling the contact holes are formed, and then the entire surface of the structure. A second interlayer insulating film 24 is formed on the semiconductor substrate 10 and the gate electrode 14 to be connected to the bit line contact plug 22 of the cell region I and the bit line of the peripheral circuit region II. The insulating films on the semiconductor layer are removed with a bit line contact mask to form bit line contact holes 26.

In the method of manufacturing a semiconductor device according to the related art as described above, in the cell region during the bit line contact hole forming process, the contact hole may be formed by removing only the second interlayer insulating layer on the upper portion of the bit line contact plug. In order to form a contact hole exposing a semiconductor substrate or an upper portion of the gate electrode, not only the second interlayer insulating layer but also the first interlayer insulating layer and the hard mask layer must be removed. It is not easy to control the time, and excessive over etching in the cell area may damage the contact plug or break the insulation.In the peripheral circuit area, the exposed semiconductor substrate or gate electrode surface may be damaged or the contact open may be incomplete. This can cause disconnection, which reduces the process yield and device reliability. The.

The present invention is to solve the above problems, the object of the present invention is

The present invention provides a method of manufacturing a semiconductor device that can form a bit line contact smoothly in a cell region and a peripheral circuit region by one etching process, thereby improving process yield and improving operation characteristics and reliability of the device.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Sequentially forming a gate oxide film, a gate conductive layer, and a hard mask layer on a semiconductor substrate having a cell region and a peripheral circuit region;

Removing a hard mask layer on a portion of the semiconductor substrate which is intended to be a peripheral circuit region;

The gate electrode having the conductive layer pattern overlapping the hard mask layer pattern in the cell region by patterning the hard mask layer, the conductive layer of the cell region, and the conductive layer of the peripheral circuit region by a photolithography process using a gate patterning mask. Forming a gate electrode having a conductive layer pattern in the peripheral circuit region;

Applying a spacer insulating film to the entire surface of the structure, and forming a spacer on the sidewall of the gate electrode of the peripheral circuit region;

Forming a first interlayer insulating film on the entire surface of the structure;

Forming a contact hole by removing the first interlayer insulating film on the portion of the cell region, which is intended as a landing plug;

Forming a contact plug filling the contact hole;

Forming a second interlayer insulating film on the entire surface of the structure;

A second interlayer insulating film on a portion of the contact plug of the cell region, which is intended for a bit line contact, a second and first interlayer insulating film on a semiconductor substrate, which is scheduled of a bit line contact, of the peripheral circuit region, and the peripheral circuit region And forming a bit line contact hole by photo-etching the second and first interlayer insulating films on the predetermined gate electrode of the bit line contact with a bit line contact mask.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are manufacturing process diagrams of a semiconductor device according to the present invention.

First, an element isolation oxide film (not shown) is formed on a semiconductor substrate 30 such as a silicon wafer having a cell region I and a peripheral circuit region II, and a gate oxide film 32 is formed on the entire surface of the structure. ), The gate conductive layer 34 and the gate hard mask layer 36 made of a nitride film are sequentially formed, and are formed on the hard mask layer 36 which is intended as the cell region I of the semiconductor substrate 30. The photosensitive film pattern 37 is formed. (See FIG. 2A).

Thereafter, the hard mask layer 36 exposed by the photoresist pattern 37 is removed so that no hard mask remains on the gate electrode on the peripheral circuit region II, and then the photoresist pattern 37 is removed. A sacrificial oxide film 38 is formed on the entire surface of the structure. (See FIG. 2B).

Thereafter, a gate patterning mask (not shown) is formed on the sacrificial oxide film 38, and the sacrificial oxide film 38, the hard mask layer 36, and the conductive layer 34 are sequentially etched using the mask to conduct the conductive pattern. After the gate electrode having the pattern of the layer 34 is formed, the rest of the sacrificial oxide film 38 is removed. At this time, the hard mask layer 36 pattern remains on the gate electrode of the cell region I. (See FIG. 2C).

Then, an insulating film for spacers 40 is applied to the entire surface of the structure, spacers are formed on the sidewalls of the conductive layer 34 pattern of the peripheral circuit region (II), and then the first interlayer insulating film 42 is formed on the entire surface of the structure. ) And patterning the first interlayer insulating film 42 on the portion of the cell region (I), which is supposed to be a contact, by using a contact mask to form a landing plug contact hole, and then filling the contact hole as a landing plug. Form 44. (See FIG. 2D).

Thereafter, a second interlayer insulating film 46 is formed on the entire surface of the structure, and a photosensitive film pattern 48 as a bit line contact mask is formed on the second interlayer insulating film 46. (See FIG. 2E).

Thereafter, the second interlayer insulating film 46 and the first interlayer insulating film 42 exposed by the photosensitive film pattern 48 are sequentially removed to form a bit line contact hole 50, and the photosensitive film pattern 48 is removed. Remove In the etching process, only the second interlayer insulating film 46 may be etched in the cell region I, and the second and first interlayer insulating films 46 and 42 may be etched in the peripheral circuit region II. Damage to the semiconductor substrate 30 in the peripheral circuit region II can be reduced, and the etching process can be easily adjusted. (See FIG. 2F).

As described above, the method of manufacturing a semiconductor device according to the present invention removes the hard mask layer on the peripheral circuit region and forms the gate electrode to smoothly form the bit line contact holes in the cell region and the peripheral circuit region. In the subsequent process, the landing plug was formed in the cell region and the bit line contact hole was formed. Therefore, the difference in etching depth between the cell region and the peripheral circuit region is reduced during the bit line contact hole etching process, and the heterogeneity of the etching material is removed. Therefore, damage to the semiconductor substrate in contact with the bit line in the peripheral circuit area is reduced, the etching process conditions are easily controlled, and the possibility of defective pattern is reduced, thereby improving process yield and device reliability.

1 is a cross-sectional view of a semiconductor device according to the prior art.

2A to 2F are manufacturing process diagrams of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 30: semiconductor substrate 12, 32: gate oxide film

14 gate electrode 16, 36 hard mask layer

18: insulating spacer 20, 42: first interlayer insulating film

22, 44: contact plug 24, 46: second interlayer insulating film

26 bit line contact hole 34 gate conductive layer

37, 48: photosensitive film pattern 38: sacrificial oxide film

40 insulating film for spacer 50 bit line contact hole

Claims (2)

Sequentially forming a gate oxide film, a gate conductive layer, and a hard mask layer on a semiconductor substrate having a cell region and a peripheral circuit region; Removing a hard mask layer on a portion of the semiconductor substrate which is intended to be a peripheral circuit region; The gate electrode having the conductive layer pattern overlapping the hard mask layer pattern in the cell region by patterning the hard mask layer, the conductive layer of the cell region, and the conductive layer of the peripheral circuit region by a photolithography process using a gate patterning mask. Forming a gate electrode having a conductive layer pattern in the peripheral circuit region; Applying a spacer insulating film to the entire surface of the structure, and forming a spacer on the sidewall of the gate electrode of the peripheral circuit region; Forming a first interlayer insulating film on the entire surface of the structure; Forming a contact hole by removing the first interlayer insulating film on the portion of the cell region, which is intended as a landing plug; Forming a contact plug filling the contact hole; Forming a second interlayer insulating film on the entire surface of the structure; A second interlayer insulating film on a portion of the contact plug of the cell region, which is intended for a bit line contact, a second and first interlayer insulating film on a semiconductor substrate, which is scheduled of a bit line contact, of the peripheral circuit region, and the peripheral circuit region And forming a bit line contact hole by photo-etching the second and first interlayer insulating films on the predetermined gate electrode of the bit line contact with a bit line contact mask. The method of claim 1, And forming a sacrificial oxide film on the entire surface before the gate electrode forming process.