KR100333542B1 - Contact plug formation method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a contact plug of a semiconductor device, comprising: a bit line contact plug and a storage electrode contact plug connected to a portion intended as a bit line contact and a storage electrode contact on an upper portion of a semiconductor substrate having a predetermined substructure; And selectively grow hemispherical metastable polysilicon grains (MPS) on the etched surfaces of the bit line contact plugs and the storage electrode contact plugs, and then form the bit line contact plugs and the storage electrode contact plugs. Overlap margin is secured by forming the connected bit line and the storage electrode to prevent misalignment during the subsequent photolithography process, thereby preventing the underlying layer from being damaged, thereby improving the characteristics and reliability of the semiconductor device. It is a technique to improve.

Description

Method of forming contact plug of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact plug of a semiconductor device. In particular, a semispherical semi-stable polysilicon layer is selectively formed on an etch surface of a bit line contact plug and a storage electrode contact plug to increase surface area, thereby increasing overlap margin in a subsequent photographic process. The present invention relates to a technology for improving and thus improving the characteristics and reliability of semiconductor devices.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a short wavelength deep ultra violet (DUV), for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, as a light source to form a fine pattern of 0.5 μm or less As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes provide misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.

In the method of forming a contact plug of a semiconductor device according to the related art, an overlap margin is set to 0.15 μm or less on the layout between a bit line contact plug and a storage electrode contact plug and a bit line and a mask for a storage electrode. If a line or a storage electrode contact hole is formed larger than a design or a misalignment occurs when patterning a storage electrode connected to the storage electrode contact plug, the storage electrode contact plug is also etched during the storage electrode patterning process to form an abnormal element. As a result, a large amount of random bit fail occurs, and if a misalignment is severe, short circuits between the bit line and the storage electrode are generated, and the storage electrode is formed to be connected to the semiconductor substrate. Loss of semiconductor substrate results in random fail and refresh soft random fail In the case of causing a soft random fail, the final yield after the package is reduced, and when the contact plug is large, there is a problem of causing a bridge between the contact plugs.

The present invention, in order to solve the above problems of the prior art, by forming a semi-spherical semi-stable polysilicon layer selectively on the etching surface of the contact plug to increase the area of the contact plug to improve the overlap margin in the subsequent process, increase the surface area The purpose of the present invention is to provide a method for forming a contact plug of a semiconductor device which increases capacitance and thereby improves characteristics and reliability of the semiconductor device.

1 to 4 are cross-sectional views showing a method for forming a contact plug of a semiconductor device according to the present invention.

<Description of Signs of Major Parts of Drawings>

11 semiconductor substrate 15 device isolation insulating film

17 gate insulating film 19 gate electrode

21 mask insulating film 23 insulating film spacer

25a: storage electrode contact plug 25b: bit line contact plug

27 antireflection film 29 hemispherical metastable polysilicon layer

31: bit line 33: storage electrode

In order to achieve the above object, the method for forming a contact plug of a semiconductor device according to the present invention includes

Forming a contact plug conductive layer on the semiconductor substrate, on which the MOS field effect transistor including a gate electrode and a source / drain electrode overlapping the mask oxide film and the insulating film spacer is formed;

Forming an antireflection film on the contact plug conductive layer;

Forming a photoresist pattern on the anti-reflection film to protect portions of the bit line contact and the storage electrode contact plug;

Forming a bit line contact plug and a storage electrode contact plug in which the antireflection film pattern is laminated by etching the antireflection film and the contact plug conductive layer by using the photoresist pattern as an etching mask;

Removing the photoresist pattern;

Forming a hemispherical metastable polysilicon layer on sidewalls of the bit line contact plug and the storage electrode contact plug;

Forming a bit line connected to the bit line contact plug;

It is a 1st characteristic that the process includes forming the storage electrode connected with the said storage electrode contact plug.

In addition, the contact plug forming method of the semiconductor device according to the present invention in order to achieve the above object,

Forming a contact plug conductive layer over the semiconductor substrate, on which the MOS field effect transistor including a gate electrode and a source / drain electrode overlapping the mask oxide film and the insulating film spacer is formed;

Forming an antireflection film on the contact plug conductive layer;

Forming a photoresist pattern on the anti-reflection film to protect portions of the bit line contact and the storage electrode contact;

Forming a bit line contact plug and a storage electrode contact plug in which the antireflection film pattern is laminated by etching the antireflection film and the contact plug conductive layer by using the photoresist pattern as an etching mask;

Forming an insulating film spacer on sidewalls of the bit line contact plug and the storage electrode contact plug, and then removing the anti-reflection film by a front etching process;

A second feature is to form a metastable polycrystalline silicon layer on top of the bit line contact plug and the storage electrode contact plug.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the present invention.

First, an isolation layer 15 and a gate oxide layer 17 are formed on the semiconductor substrate 11, and a MOS field effect transistor including a gate electrode 19 and a source / drain electrode (not shown) is formed. In this case, a mask insulating film 21 is stacked on the gate electrode 19, and an insulating film spacer 23 is formed on the sidewall of the gate electrode 19. (See Fig. 1)

Next, an insulating film is formed over the entire surface, and the insulating film is removed in the cell region of the semiconductor substrate 11 by an etching process using an etching mask exposing the cell region.

Thereafter, a polysilicon layer is formed to a thickness of 1500 to 2500 kPa over the entire surface, and then etched by a sputtering method using argon (Ar) to alleviate the step.

Next, an anti-reflection film 27 is formed on the polysilicon layer, and a photoresist pattern (not shown) is formed on the anti-reflection film 27 to protect portions intended as bit line contacts and storage electrode contacts. At this time, the anti-reflection film 27 is formed to a thickness of 500 ~ 1000Å by using an oxynitride film.

Next, the anti-reflection film 27 and the polysilicon layer are etched using the photoresist pattern as an etching mask to form a bit line contact plug 25a and a storage electrode contact plug 25b.

Thereafter, the photosensitive film pattern is removed. In this case, the etching process is performed while forming a polymer on the sidewalls of the photoresist pattern by an in-situ method to form 1.0 to 1.4 μm larger than the contact plug on the reticle.

The bit line contact plug 25a and the storage electrode contact plug 25b may be formed by an entire surface etching process. (See Fig. 2)

Next, a hemispherical metastable polysilicon layer 29 is selectively grown on an etching surface of the bit line contact plug 25a and the storage electrode contact plug 25b. The hemispherical metastable polysilicon layer 29 is not formed in the portion where the anti-reflection film 27 is formed, and the bit line contact plug 25a and the storage electrode contact plug 25b formed of the polysilicon layer are formed. The surface area is increased to ensure overlap margin with the subsequently formed bit lines and storage electrodes.

Meanwhile, an insulating film spacer (not shown) is formed on sidewalls of the bit line contact plug 25a and the storage electrode contact plug 25b, and then the entire surface etching process is performed to remove the antireflection film 27, and then the bit A hemispherical metastable polycrystalline silicon layer may be formed on the line contact plug 25a and the storage electrode contact plug 25b. In this case, the insulating film spacer is formed of an oxide film or a nitride film-based material. (See Fig. 3)

Subsequently, a subsequent process is performed to form the bit line 31 connected to the bit line contact plug 25a, and then to the cylindrical storage electrode 33 connected to the storage electrode contact plug 25b. . In this case, as shown in FIG. 4, a hemispherical metastable polysilicon layer may be formed on the surface of the storage electrode 33. (See Fig. 4)

As described above, the method for forming a contact plug of a semiconductor device according to the present invention includes a bit line contact plug and a storage connected to a portion intended as a bit line contact and a storage electrode contact on a semiconductor substrate on which a predetermined substructure is formed. Forming an electrode contact plug, selectively growing a hemispherical metastable polysilicon layer on an etching surface of the bit line contact plug and the storage electrode contact plug, and then connecting the bit line contact plug and the storage electrode contact plug By forming a line and a storage electrode, an overlap margin is secured to prevent misalignment during the subsequent photolithography process, thereby preventing the underlying layer from being damaged, thereby improving the characteristics and reliability of the semiconductor device. There is this.

Claims (5)

Forming a contact plug conductive layer on the semiconductor substrate, on which the MOS field effect transistor including a gate electrode and a source / drain electrode overlapping the mask oxide film and the insulating film spacer is formed; Forming an antireflection film on the contact plug conductive layer; Forming a photoresist pattern on the anti-reflection film to protect portions of the bit line contact and the storage electrode contact; Forming a bit line contact plug and a storage electrode contact plug in which the antireflection film pattern is laminated by etching the antireflection film and the contact plug conductive layer by using the photoresist pattern as an etching mask; Removing the photoresist pattern; Forming a hemispherical metastable polysilicon layer on the sidewalls of the bit line contact plug and the storage electrode contact plug; Forming a bit line connected to the bit line contact plug; And forming a storage electrode connected to the storage electrode contact plug. The method of claim 1, And wherein said contact plug conductive layer is a polycrystalline silicon layer. The method of claim 1, The anti-reflection film is a contact plug forming method of a semiconductor device, characterized in that formed to a thickness of 500 ~ 1000Å. Forming a contact plug conductive layer on the semiconductor substrate, on which the MOS field effect transistor including a gate electrode and a source / drain electrode overlapping the mask oxide film and the insulating film spacer is formed; Forming an antireflection film on the contact plug conductive layer; Forming a photoresist pattern on the anti-reflection film to protect portions of the bit line contact and the storage electrode contact; Forming a bit line contact plug and a storage electrode contact plug in which the antireflection film pattern is laminated by etching the antireflection film and the contact plug conductive layer by using the photoresist pattern as an etching mask; Forming an insulating film spacer on sidewalls of the bit line contact plug and the storage electrode contact plug, and then removing the anti-reflection film by a front etching process; And forming a metastable polycrystalline silicon layer on the bit line contact plug and the storage electrode contact plug. The method of claim 4, wherein And the insulating film spacer is formed of an oxide film or a nitride film-based material.