KR20020013069A - Capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A capacitor of a semiconductor device is provided to increase capacitance and improve characteristic and yield regarding a refresh of a dynamic random access memory(DRAM), by forming a capacitor of a trench structure and a capacitor of a cylinder structure in one cell. CONSTITUTION: A trench-type capacitor is formed in one side of an active region of a semiconductor substrate. After a metal-oxide-semiconductor field-effect-transistor(MOSFET) and a bit line are formed, the cylindrical capacitor is formed in the other side of the active region. The cylindrical capacitor is formed to a portion where the trench-type capacitor is formed, so that the surface area of a storage electrode is increased.

Description

Capacitor of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device, and more particularly, to a technique of increasing a capacitance of a capacitor by forming a trench in a semiconductor substrate and forming stacked and cylindrical storage electrodes on the trench.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure is limited using a deep ultra violet (DUV) light, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. It has been developed, such as silico-migration method for implanting lowering the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a high integration of the device, and the size of the contact holes decreases, and the distance between the peripheral wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes provide misalignment tolerance during mask alignment, lens distortion during exposure process, critical dimension variation during mask fabrication and photolithography process, and mask-to-mask The mask is formed by considering factors such as registration.

1 is a cross-sectional view of a memory cell including a capacitor of a semiconductor device according to the prior art.

First, a device isolation insulating film 15 and a gate insulating film are formed on the semiconductor substrate 11, and a MOS field effect transistor including a gate electrode 19 and a source / drain electrode (not shown) is formed. In this case, a gate insulating film pattern 17 is stacked below the gate electrode 19, and a mask insulating film 21 is stacked on the gate electrode 19, and an insulating film spacer 23 is formed on the sidewall of the gate electrode 19. .

Next, a first polycrystalline silicon layer is formed on the entire surface, and an etch stop layer (not shown) is formed on the first polycrystalline silicon layer.

Next, the first polycrystalline silicon layer formed in the peripheral circuit region of the semiconductor substrate 11 is removed using a mask that protects the cell region of the semiconductor substrate 11.

Next, the etch stop layer on the first polysilicon layer is removed using a cell mask that exposes the cell region of the semiconductor substrate 11 as an etch mask.

A photoresist pattern (not shown) is formed on the second polysilicon layer to protect portions of the bit line contact and the storage electrode contact.

The bit line contact plug 25b and the storage electrode contact plug 25a are formed by etching the first and second polysilicon layers using the photoresist pattern as an etching mask, and then removing the photoresist pattern.

Next, a first interlayer insulating layer 27 having a bit line contact hole for exposing a portion of the bit line contact plug 25b to be a bit line contact is formed on the entire surface.

Subsequently, a subsequent step is performed to form the bit line 31 connected to the bit line contact plug 25b.

Next, a second interlayer dielectric layer 31 is formed over the entire surface, and the second interlayer dielectric layer 31 and the first interlayer dielectric layer 27 are etched using a storage electrode contact mask as an etch mask. A storage electrode contact hole exposing the plug 25a is formed.

Next, a cylindrical storage electrode 33 connected to the storage electrode contact plug 25b is formed. In this case, the MPS layer 35 may be grown on the surface of the cylindrical storage electrode 33 to increase the surface area of the storage electrode.

A dielectric film (not shown) and plate electrode 35 are then formed to complete the capacitor. (See Figure 1)

In the method of forming a capacitor of a semiconductor device according to the prior art as described above, since the storage electrode is formed to increase the surface area of the storage electrode as the semiconductor device is highly integrated, the thickness of the photoresist film formed for patterning the storage electrode is formed. In addition, since it is necessary to form a thick, it is difficult to align with the storage electrode contact, it is difficult to form the photosensitive film vertically, and there is a problem that the storage electrode collapses in a subsequent process, bridges between the storage electrodes.

The present invention to solve the above problems of the prior art, by forming a capacitor of the trench structure and a capacitor of the cylinder structure at the same time to increase the capacitance of the capacitor, thereby resulting in a semiconductor device capacitor that enables high integration of the semiconductor device The purpose is to provide.

1 is a cross-sectional view of a memory cell having a capacitor of a semiconductor device according to the prior art.

2 is a cross-sectional view of a memory cell including a capacitor of a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: buried nwell 11: semiconductor substrate

12: Pwell 13, 23: insulating film spacer

14: trench type storage electrode 15, 18: device isolation insulating film

16 dielectric film 17, 20 gate insulating film pattern

19, 22: gate electrode 21, 24: mask insulating film pattern

25a, 28a: storage electrode contact plug 25b, 28b: bit line contact plug

26: source / drain electrodes 27, 30: first interlayer insulating film

29, 32: bit lines 31, 34: second interlayer insulating film

33, 36: cylindrical storage electrodes 33, 38: MPS film

35, 40: plate electrode

In order to achieve the above object, a capacitor of a semiconductor device according to the present invention,

A trench capacitor is provided on one side of the active region of the semiconductor substrate, and a cylindrical capacitor is provided on the other side of the active region after forming the MOS field effect transistor and the bit line.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a cross-sectional view of a memory cell including a capacitor of a semiconductor device according to the present invention.

First, the buried n well 10 is formed on an p-type semiconductor substrate by an ion implantation process using an n well mask (not shown) as an implant mask.

Next, the p well 12 is formed on the semiconductor substrate by an ion implantation process using a p well mask (not shown) as an implant mask.

Thereafter, a portion of the semiconductor substrate, which is intended to be a storage electrode having a trench structure, is etched to form a trench.

A dielectric film 16 is then formed on the surface of the trench.

Next, a conductive layer for a storage electrode filling the trench is formed.

Next, the trench-type storage electrode 14 is formed by etching the conductive layer for the storage electrode to form a capacitor having a trench structure. In this case, the buried n well 10 is used as a plate electrode.

Next, a device isolation insulating film 18 is formed on a portion of the semiconductor substrate, which is intended as a device isolation region.

Next, a gate insulating film is formed on the semiconductor substrate, and a MOS field effect transistor including a gate electrode 22 and a source / drain electrode 26 is formed. In this case, a gate insulating film pattern 20 is stacked below the gate electrode 22, and a mask insulating film 24 is stacked on the gate electrode 22, and an insulating film spacer 13 is formed on the sidewall of the gate electrode 22. .

Here, the source / drain electrode 26 is connected to the trench type storage electrode 14.

Next, a first polycrystalline silicon layer is formed on the entire surface, and an etch stop layer (not shown) is formed on the first polycrystalline silicon layer.

Then, the first polycrystalline silicon layer formed in the peripheral circuit region of the semiconductor substrate is removed using a mask that protects the cell region of the semiconductor substrate.

Next, the etch stop layer on the first polysilicon layer is removed using a cell mask exposing the cell region of the semiconductor substrate as an etch mask.

A photoresist pattern is formed on the second polysilicon layer to protect portions of the bit line contact and the storage electrode contact.

The bit line contact plug 28b and the storage electrode contact plug 28 are formed by etching the first and second polysilicon layers using the photoresist pattern as an etching mask, and then removing the photoresist pattern.

Next, a first interlayer insulating layer 30 having a bit line contact hole for exposing a portion of the bit line contact plug 28b to be a bit line contact is formed on the entire surface.

Subsequently, a subsequent step is performed to form the bit line 32 connected to the bit line contact plug 28b.

Next, a second interlayer dielectric layer 34 is formed on the entire surface, and the second interlayer dielectric layer 34 and the first interlayer dielectric layer 30 are etched using a storage electrode contact mask as an etch mask. A storage electrode contact hole exposing the plug 28a is formed. In this case, the storage electrode contact hole is formed at the other side where the trench capacitor is formed.

Next, a cylindrical storage electrode 36 connected to the storage electrode contact plug 28b is formed. In this case, the MPS film 38 may be grown on the surface of the cylindrical storage electrode 33 to increase the surface area of the storage electrode. Here, the cylindrical storage electrode 33 may be formed up to an upper portion where the trench capacitor is formed to increase the surface area.

A dielectric film (not shown) and plate electrode 40 are then formed to complete the capacitor. (See Figure 2)

As described above, in the capacitor of the semiconductor device according to the present invention, by forming the capacitor of the trench structure and the capacitor of the cylinder structure in one cell, the capacitance of the capacitor can be increased without increasing the step, thereby securing a process margin. Increasing the capacitance has the advantage of improving the refresh-related characteristics and yield of the DRAM, thereby enabling high integration of the semiconductor device.

Claims (2)

A trench capacitor is provided at one side of the active region of the semiconductor substrate, and a cylindrical capacitor is provided at the other side of the active region after forming the MOS field effect transistor and the bit line. The method of claim 1, The cylindrical capacitor may be formed up to a portion where the trench capacitor is formed to increase the surface area of the storage electrode, the capacitor of the semiconductor device.