KR20060113283A - Manufacturing method for semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to increase misalign tolerance of a charge storage node contact hole by forming a plug pad of a wineglass type on a landing plug for a charge storage node before the charge storage node contact hole is formed on a semiconductor substrate having a landing plug. A gate insulation layer(12) is formed on a semiconductor substrate(10). A gate electrode(14) is formed on the gate insulation layer, overlapping a hard mask layer pattern. An insulation spacer is formed on the sidewall of the hard mask layer pattern and the gate electrode. A first interlayer dielectric(20) including a landing plug is formed on the resultant structure. A second interlayer dielectric(24) is formed on the resultant structure. The second interlayer dielectric on a portion of the landing plug reserved for a charge storage node contact is removed to form a contact hole of a wineglass type. The contact hole is filled with a plug pad(26). The second interlayer dielectric is made of BPSG(boron phosphorous silicate glass) or an LPCVD(low pressure plasma chemical vapor deposition) TEOS(tetraethoxysilane) oxide layer, having a thickness of 1000~5000 angstroms.

Description

Manufacturing method for semiconductor device

1A and 1B are manufacturing process diagrams of a semiconductor device according to the present invention.

2 is a layout diagram of a semiconductor device according to the present invention;

         <Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 12 gate insulating film

14 gate electrode 16 hard mask layer

18 spacer 20 first interlayer insulating film

22: landing plug 24: second interlayer insulating film

26: plug pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the charge storage electrode contact plug forming process performed after the formation of a bit line, a wineglass-shaped plug pad is formed on the contact plug to improve misalignment margin and to prevent contact failure. The present invention relates to a method for manufacturing a semiconductor device which can prevent the degradation of process yield and reliability of device operation.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A tri layer resister (hereinafter referred to as a TLR) in which a contrast enhancement layer (CEL) method or an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. A method or a silicide method for selectively injecting silicon on top of the photoresist film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the diameter of the contact hole is reduced. The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

Since the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current state of the art, there is a limit to high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

Although not shown, a process of forming a charge storage electrode contact of a semiconductor device according to the related art is as follows.

First, a device isolation oxide film is formed on a semiconductor substrate to define an active region, and lower structures such as a MOSFET, such as a gate electrode and a source / drain region, which overlap with a hard mask layer pattern, are formed on the entire surface of the structure. After forming a first interlayer insulating film having a landing plug, a bit line overlapping the hard mask made of a nitride film is formed on the first interlayer insulating film, and a nitride film spacer is formed on sidewalls of the bit line pattern.

Then, a second interlayer insulating film is formed on the entire surface of the structure, and the top surface is planarized by chemical mechanical polishing, and then a hard mask layer of polycrystalline silicon layer is formed on the second interlayer insulating film.

Thereafter, the hard mask layer is photo-etched with a photoresist pattern for forming a contact hole for a charge storage electrode to form a hard mask layer pattern, and the second interlayer insulating layer is removed using the hard mask layer pattern as a mask for charge storage electrode. A contact hole is formed.

Then, the hard mask layer is removed, a polysilicon layer which becomes a contact plug is applied to the entire surface of the structure to fill the contact hole, and the polysilicon layer on the contact hole is removed by chemical-mechanical polishing or the like. A contact plug having a polysilicon layer pattern is formed, and a capacitor including a charge storage electrode, a dielectric film, and a plate electrode is formed thereon.

The method of manufacturing a semiconductor device according to the prior art as described above uses a method of increasing the thickness of the gate electrode hard mask layer in order to increase the process margin during landing plug contact open co-operation during the charge storage electrode contact forming process. The aspect ratio is increased, such as a problem in contact open failure or gap fill margin is reduced, there is a problem, such as bridge failure occurs when the alignment margin of the contact is reduced or misalignment occurs or the contact threshold size is increased.

The present invention is to solve the above problems, an object of the present invention is to form a wineglass-shaped plug pad on the top of the landing plug for the charge storage electrode in the charge storage electrode contact forming process of the gate electrode hard mask layer The charge storage electrode contacts can be easily formed without increasing the thickness, thereby preventing an increase in aspect ratio, poor contact openness, or reduced gap fill margin, and an increase in contact alignment margin, resulting in bridge failure even when misalignment or contact threshold size is increased. This is to provide a method for manufacturing a semiconductor device that can be prevented to improve the process yield and the reliability of device operation.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a gate insulating film on the semiconductor substrate;

Forming a gate electrode overlapping the hard mask layer pattern on the gate insulating film;

Forming an insulating spacer on sidewalls of the hard mask layer pattern and the gate electrode;

Forming a first interlayer insulating film having a landing plug on the entire surface of the structure;

Forming a second interlayer insulating film on the entire surface of the structure;

Forming a contact hole by removing a second interlayer insulating film on a portion of the landing plug, which is intended as a charge storage electrode contact, and forming a contact hole in a wineglass shape;

And forming a plug pad filling the contact hole.

In another aspect of the present invention, the second interlayer dielectric layer is formed of BPSG or low pressure plasma chemical vapor deposition TEOS oxide, but is formed to a thickness of about 1000 to 5000 kPa, and the upper portion of the second interlayer dielectric layer is chemically mechanically polished or entirely etched. The second interlayer insulating film is left to have a thickness of 1000 to 2000 평탄 by etching through the same, and the wineglass-shaped contact hole is formed by etching two times by wet anisotropic etching and dry isotropic etching, and removing the photoresist pattern after forming the contact hole. And a process of cleaning using BOE, and the plug pad is formed by forming a polysilicon layer with a thickness of 500 to 3000 kPa and etching the same.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B are manufacturing process diagrams of a semiconductor device according to the present invention.

First, a device isolation oxide film (not shown) is formed on one side of the semiconductor substrate 10 and a gate insulating film 12 is formed on the entire surface of the structure, and then the gate insulating film 12 is formed. A gate electrode 14 overlapping the pattern of the hard mask layer 16 is formed on the substrate, and an insulating spacer 18 is formed on sidewalls of the pattern of the hard mask layer 16 and the gate electrode 14. Here, the gate electrode 14 is formed to a thickness of about 200 to 1000 GPa of polycrystalline silicon layer and about 500 to about 2000 GPa of W silicide, and the hard mask layer 16 is formed of a nitride film having a thickness of about 1000 to 2000 GPa, and the hard mask layer ( 16) Etching is performed using a CF ₄ / CHF ₃ / O ₂ / Ar mixed gas at a pressure of 30 to 70mTorr, 500 to 1000W power, and the W silicide layer and the polysilicon layer are C ₂ F ₆ / NF ₃ / Using a mixed gas such as Cl ₂ / O ₂ / N ₂ / He / HBr, the wafer is etched at a power of 500 to 1000 W at a pressure of 1 to 100 mTorr, and the spacer 18 is 100 to 300 kW to be an etch barrier layer made of a nitride film. Form to the thickness of about.

Then, the first interlayer insulating film 20 is formed on the entire surface of the structure, and the landing plug is removed by removing the first interlayer insulating film 20 on the portion of the semiconductor substrate 10, which is intended to be contacted, using a landing plug mask. After forming the contact hole, the landing plug 22 filling the contact hole is formed of polycrystalline silicon or the like, and a second interlayer insulating film 24 is formed on the entire surface of the structure. Here, the first interlayer insulating film 20 is formed of an oxide film such as BPSG to a thickness of about 5000 to 10000 kPa, wet heat treatment to smooth the gap fill, and etching and flattening by chemical mechanical polishing.

In addition, the landing plug mask may be formed using a photoresist pattern, or the first interlayer insulating layer 20 may be etched using a nitride film or a polysilicon layer as a hard mask layer, and C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH _The contact hole is opened by etching at 1000 to 2000 W power at a pressure of 10 to 100 mTorr using a mixed gas such as _{2F 2} / Ar / O ₂ / CO / N ₂ . When the photoresist pattern is removed after the contact is opened, the polymer may be removed by using a BOE mixed with H ₂ SO ₄ + H ₂ 0 ₂ to remove the polymer generated during etching and increase the bottom area of the contact hole. .

In addition, the conductive layer for the landing plug 22 may be coated with a polysilicon layer having a thickness of about 500 to 2000 kPa, and 100 to 100 mTorr pressure using a mixed gas such as C ₂ F ₆ / CF ₃ / Cl ₂ / HBr. Form by etching with 500W power. In addition, the second interlayer insulating film 24 is formed of an oxide film material such as BPSG or low pressure plasma chemical vapor deposition TEOS oxide film to a thickness of about 1000 to 5000 kPa. (See FIG. 1A).

Thereafter, the upper portion of the second interlayer insulating film 24 is etched and planarized by chemical mechanical polishing or front surface etching, and the second interlayer insulating film 24 is left to have a thickness of about 1000 to 2000 microseconds. A contact hole exposing the landing plug 22 for the charge storage electrode is formed by a photolithography process, and the contact hole is formed in a wineglass shape by etching twice with wet anisotropic etching and dry isotropic etching, and forming the contact hole. To form a plug pad 26 of the wineglass shape filling the. At this time, the second interlayer smoke screen 24 is left thin on the landing plug 22 for the bit line.

Here, the photoresist pattern is removed after the formation of the wineglass-shaped contact hole, and cleaning is performed using a BOE mixed with H ₂ SO ₄ + H ₂ 0 ₂ , thereby removing the polymer generated during etching and increasing the bottom area of the contact hole. You can. In addition, the plug pad 26 forms a polysilicon layer having a thickness of about 500 to 3000 kPa, and uses a mixed gas such as C ₂ F ₆ / CHF ₃ / Cl ₂ / HBr at a pressure of 1 to 20 mTorr and 100 to 500 W It is formed by etching with power. (See FIG. 1B).

Next, although not shown, a bit line in contact with the bit line landing plug 22 is formed on the structure, an insulating film is coated on the front surface, and a charge storage electrode contact plug in contact with the plug pad 26 is formed. Form a capacitor.

In this case, the contact plug is formed on the plug pad 26 to prevent the loss of the hard mask layer 16 of the gate electrode 14 due to the etching process.

FIG. 2 is a layout diagram of a semiconductor device according to the present invention, in which an active region (not shown) is defined by an isolation oxide layer 11 on a semiconductor substrate 10 and a gate is crossed across the line / space pattern. The electrode 14 extends in the longitudinal direction at regular intervals, and the bit line 30 is disposed in the horizontal direction orthogonal thereto, and the bit line 30 is connected to the substrate through the bit line contact hole 32. The plug pad 26 is connected between the gate electrodes 14 to form a wine glass, thereby increasing the contact margin, thereby increasing the margin of misalignment of the charge storage electrode contact hole 34.

In addition, although the bit line is formed above the plug pad, the plug pad may be formed above the bit line.

As described above, in the method of manufacturing the semiconductor device according to the present invention, since a wineglass-shaped plug pad is formed on the landing plug for the charge storage electrode before the charge storage electrode contact hole is formed on the semiconductor substrate on which the landing plug is formed. In addition, the margin of misalignment of the charge storage electrode contact hole is increased to prevent open defects and short circuit defects, thereby improving process yield and reliability of device operation.

Claims (6)

Forming a gate insulating film on the semiconductor substrate; Forming a gate electrode overlapping the hard mask layer pattern on the gate insulating film; Forming an insulating spacer on sidewalls of the hard mask layer pattern and the gate electrode; Forming a first interlayer insulating film having a landing plug on the entire surface of the structure; Forming a second interlayer insulating film on the entire surface of the structure; Forming a contact hole by removing a second interlayer insulating film on a portion of the landing plug, which is intended as a charge storage electrode contact, and forming a contact hole in a wineglass shape; And forming a plug pad filling the contact hole. The method of claim 1, wherein the second interlayer dielectric layer is formed of BPSG or low-pressure plasma chemical vapor deposition TEOS oxide, but has a thickness of about 1000 to 5000 kV. The method of claim 1, wherein the upper portion of the second interlayer dielectric layer is etched and planarized by chemical mechanical polishing or front surface etching to leave the second interlayer dielectric layer at 1000 to 2000 μm. The method of claim 1, wherein the wineglass-shaped contact hole is formed by etching twice by wet anisotropic etching and dry isotropic etching. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing the photoresist pattern after forming the contact hole and cleaning using BOE. The method of claim 1, wherein the plug pad is formed by forming a polysilicon layer with a thickness of 500 to 3000 μm and etching the same.

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