KR20000027639A - Method for manufacturing contact plug of semiconductor devices - Google Patents
Method for manufacturing contact plug of semiconductor devices Download PDFInfo
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- KR20000027639A KR20000027639A KR1019980045594A KR19980045594A KR20000027639A KR 20000027639 A KR20000027639 A KR 20000027639A KR 1019980045594 A KR1019980045594 A KR 1019980045594A KR 19980045594 A KR19980045594 A KR 19980045594A KR 20000027639 A KR20000027639 A KR 20000027639A
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- South Korea
- Prior art keywords
- contact plug
- forming
- contact
- insulating film
- semiconductor substrate
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title abstract description 31
- 238000004519 manufacturing process Methods 0.000 title description 18
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 238000003860 storage Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 abstract description 11
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 239000010410 layer Substances 0.000 description 30
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000005530 etching Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 7
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 콘택 플러그 제조방법에 관한 것으로, 특히 고집적 소자의 제조 공정시 저장전극 콘택과 비트라인 콘택 형성시 반도체기판에 접촉되는 저장전극 콘택 플러그 및 비트라인 콘택 플러그를 선택적 성장방법으로 형성함으로써 정션 누설전류가 적은 콘택을 형성하여 그에 따른 반도체소자의 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact plug of a semiconductor device. In particular, the storage electrode contact plug and the bit line contact plug which are in contact with the semiconductor substrate when the storage electrode contact and the bit line contact are formed in the manufacturing process of the highly integrated device are formed by a selective growth method. The present invention relates to a technology for forming a contact with low junction leakage current, thereby improving the reliability of the semiconductor device.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture:NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.
[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선, 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 공정 상의 방법으로는 노광마스크를 위상 반전 마스크를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL이라 함) 방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass: SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resist: 이하 TLR 라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, the micrometer has a limit of about μm, and an exposure apparatus using an ultraviolet ray having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source, or a process As a method of imaging, a method of using a phase inversion mask as an exposure mask and a method of forming a separate thin film on the wafer which can improve image contrast can be used. A tri layer resist method (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers or silicon on a photoresist layer selectively. It has been developed, such as silico-migration method for injection may lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고, 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화, 마스크간의 정합 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have factors such as misalignment tolerance during mask alignment, lens distortion during exposure process, threshold size change during mask fabrication and photolithography process, and matching between masks to maintain gaps. Consider these to form a mask.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 콘택 플러그 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a contact plug of a semiconductor device according to the related art will be described with reference to the accompanying drawings.
도 1a 내지 도 1e 는 종래기술의 제1실시예에 따른 반도체소자의 콘택 플러그 제조방법을 도시한 단면도이고, 도 2a 내지 도 2d 는 종래기술의 제2실시예에 따른 반도체소자의 콘택 플러그 제조방법을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a contact plug of a semiconductor device according to a first embodiment of the prior art, and FIGS. 2A to 2D illustrate a method of manufacturing a contact plug of a semiconductor device according to a second embodiment of the prior art. It is a cross-sectional view showing.
먼저, 반도체기판(11)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 절연막(12)을 형성하고, 나머지 반도체기판(11)에 게이트 절연막(13)을 형성한 다음, 게이트 전극(14)과 마스크 절연막(15)의 적층구조를 형성한 후, 상기 적층구조 양측의 반도체기판(11)에 엘.디.디.(lightly doped drain : LDD) 영역이 되는 저농도 불순물층(도시않됨)을 형성한 후, 상기 전체표면에 절연막을 증착한 다음, 전면식각을 실시하여 상기 적층구조의 측면에 절연막 스페이서(16)를 형성한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the device isolation region of the semiconductor substrate. Forming a device isolation insulating film 12 on a predetermined portion, forming a gate insulating film 13 on the remaining semiconductor substrate 11, and then forming a stacked structure of the gate electrode 14 and the mask insulating film 15. Then, a lightly doped impurity layer (not shown), which becomes an L.D. (LDD) region, is formed on the semiconductor substrate 11 on both sides of the stacked structure, and then an insulating film is deposited on the entire surface. Next, an entire surface is etched to form an insulating film spacer 16 on the side of the stacked structure.
그 후, 상기 절연막 스페이서(16) 양측의 반도체기판(11)에 고농도 불순물영역(도시않됨)을 형성한다.Thereafter, a high concentration impurity region (not shown) is formed in the semiconductor substrate 11 on both sides of the insulating film spacer 16.
다음, 전체표면 상부에 질화막을 전면적으로 형성하여 식각방지막(17)을 형성한 후, 상기 식각방지막(17) 상부에 스텝커버리지가 우수한 비.피.에스.지.(borophospho silicate glass, 이하 BPSG 라 함) 등의 산화막을 사용하여 층간절연막(18)을 형성한다.Next, the nitride film is formed on the entire surface of the entire surface to form an etch stop layer 17, and then the BPSG has excellent step coverage on the etch stop layer 17 (borophospho silicate glass, hereinafter referred to as BPSG). An interlayer insulating film 18 is formed using an oxide film.
그 다음, 상기 층간절연막(18) 상부에 상기 반도체기판(11)에서 비트라인 콘택과 저장전극 콘택으로 예정되는 부분을 노출시키는 감광막 패턴(19)을 형성한다.Next, a photoresist pattern 19 is formed on the interlayer insulating layer 18 to expose a portion of the semiconductor substrate 11 to be formed as a bit line contact and a storage electrode contact.
그 후, 상기 감광막 패턴(19)을 식각마스크로 사용하여 상기 층간절연막(18)을 식각한 다음, 상기 식각방지막(17)을 식각하여 비트라인 콘택 및 저장전극 콘택으로 예정되는 반도체기판(11)을 노출시키는 콘택홀을 형성한다.Thereafter, the interlayer insulating layer 18 is etched using the photoresist pattern 19 as an etch mask, and then the etch stop layer 17 is etched to form a bit line contact and a storage electrode contact. A contact hole is formed to expose the gap.
다음, 상기 감광막 패턴(19)을 제거하고, 전체표면 상부에 다결정실리콘층을 상기 콘택홀을 메우도록 형성한 후, 전면식각공정을 실시하여 콘택 플러그(20)를 형성한다.Next, the photoresist layer pattern 19 is removed, and a polysilicon layer is formed on the entire surface to fill the contact hole, and then the contact plug 20 is formed by performing an entire surface etching process.
한편, 종래기술의 제2실시예에 따른 반도체소자의 제조방법은, 상기 제1실시예의 도 1a 까지의 공정을 실시한 후, 전체표면 상부에 다결정실리콘층을 증착하고, 그 상부에 비트라인 콘택과 저장전극 콘택으로 예정되는 부분을 노출시키는 제1감광막 패턴(28)을 형성한 다음, 상기 제1감광막 패턴(28)을 식각마스크로 사용하여 상기 다결정실리콘층을 식각하여 제1콘택 플러그(27)를 형성한다. (도 2a, 도 2b참조)On the other hand, in the method of manufacturing a semiconductor device according to the second embodiment of the prior art, after performing the process up to FIG. 1A of the first embodiment, the polysilicon layer is deposited on the entire surface, and the bit line contact and After forming a first photoresist layer pattern 28 exposing a predetermined portion as a storage electrode contact, the polysilicon layer is etched using the first photoresist layer pattern 28 as an etch mask to form a first contact plug 27. To form. (See FIG. 2A, FIG. 2B)
그 후, 상기 제1감광막 패턴(28)을 제거한 다음, 전체표면 상부에 BPSG 등을 사용하여 층간절연막(29)을 형성하고, 그 상부에 상기 제1콘택 플러그(27)로 예정되는 부분을 노출시키는 제2감광막 패턴(30)을 형성한다.Thereafter, the first photoresist layer pattern 28 is removed, and then an interlayer insulating layer 29 is formed on the entire surface using BPSG or the like, and a portion of the first contact plug 27 is exposed thereon. The second photosensitive film pattern 30 is formed.
그 다음, 상기 제2감광막 패턴(30)을 식각마스크로 사용하여 상기 층간절연막(29)을 제거한다. (도 2c참조)Next, the interlayer insulating layer 29 is removed using the second photoresist layer pattern 30 as an etching mask. (See FIG. 2C)
그리고, 상기 제2감광막 패턴(30)을 제거한 후, 전체표면 상부에 다결정실리콘층을 형성하고, 전면식각공정을 실시하여 상기 제1콘택 플러그(27)와 접속되는 제2콘택 플러그(31)를 형성한다. (도 2d참조)After removing the second photoresist layer pattern 30, a polysilicon layer is formed on the entire surface, and the second contact plug 31 connected to the first contact plug 27 is formed by performing an entire surface etching process. Form. (See FIG. 2D)
상기와 같이 종래기술에 따른 반도체소자의 콘택 플러그 제조방법은, 워드라인과 워드라인 사이의 간격이 계속 좁아지는 고집적화에 따라 그 사이에 콘택을 형성하기 위한 공정마진이 감소되고, 콘택 형성후 콘택과 인접한 워드라인과의 접촉을 방지하기 위하여 콘택 안에 절연스페이서를 형성해야 하지만 콘택이 너무 좁아서 절연스페이서가 형성될 여유가 없으며, 상기 절연 스페이서 형성시 콘택의 정션이 심한 손상을 입는 등 공정수율 및 소자동작의 신뢰성을 떨어드리는 문제점이 있다.As described above, in the method of manufacturing a contact plug of a semiconductor device according to the related art, the process margin for forming a contact therebetween is reduced according to the high integration between the word line and the word line. Insulation spacers should be formed in the contacts to prevent contact with adjacent word lines, but the contacts are too narrow to afford insulation spacers. There is a problem that reduces the reliability of.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 비트라인 콘택 및 저장전극 콘택으로 예정되어 있는 부분의 반도체기판에 다결정실리콘을 선택적 성장시켜 비트라인 콘택 플러그 및 저장전극 콘택 플러그를 형성함으로써 콘택홀을 형성하기 위한 식각공정없이 콘택 플러그를 형성함으로써 반도체기판과 콘택간의 정션 누설전류를 감소시켜 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 콘택 플러그 제조방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by forming a bit line contact plug and a storage electrode contact plug by selectively growing a polysilicon on the semiconductor substrate of the portion intended as a bit line contact and a storage electrode contact contact hole It is an object of the present invention to provide a method for manufacturing a contact plug of a semiconductor device which reduces the junction leakage current between the semiconductor substrate and the contact by forming a contact plug without an etching process for forming a semiconductor device, thereby improving the characteristics and reliability of the semiconductor device.
도 1a 내지 도 1e 는 종래기술의 제1실시예에 따른 반도체소자의 콘택 플러그 제조방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method for manufacturing a contact plug of a semiconductor device according to a first embodiment of the prior art;
도 2a 내지 도 2d 는 종래기술의 제2실시예에 따른 반도체소자의 콘택 플러그 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method for manufacturing a contact plug of a semiconductor device according to a second embodiment of the prior art;
도 3a 내지 도 3d 는 본 발명에 따른 반도체소자의 콘택 플러그 제조방법을 도시한 단면도.3A to 3D are cross-sectional views illustrating a method for manufacturing a contact plug of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 21, 41 : 반도체기판 12, 22, 42 : 소자분리 절연막11, 21, 41: semiconductor substrate 12, 22, 42: device isolation insulating film
13, 23, 43 : 게이트 절연막 14, 24, 44 : 게이트 전극13, 23, 43: gate insulating film 14, 24, 44: gate electrode
15, 25, 45 : 마스크 절연막 16, 26, 46 : 절연막 스페이서15, 25, 45: mask insulating film 16, 26, 46: insulating film spacer
17 : 식각방지막 18, 29, 48 : 층간절연막17: etching prevention film 18, 29, 48: interlayer insulating film
19, 49 : 감광막 패턴 20 : 콘택 플러그19, 49: photosensitive film pattern 20: contact plug
27, 47 : 제1콘택 플러그 28 : 제1감광막 패턴27, 47: first contact plug 28: first photosensitive film pattern
30 : 제2감광막 패턴 31, 50 : 제2콘택 플러그30: second photosensitive film pattern 31, 50: second contact plug
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 콘택 플러그 제조방법은,Contact plug manufacturing method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 게이트 전극과 마스크 절연막 패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate electrode and a mask insulating film pattern on the semiconductor substrate;
상기 적층구조의 양쪽 반도체기판에 LDD영역을 형성하는 공정과,Forming LDD regions on both semiconductor substrates of the laminated structure;
상기 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the laminated structure;
상기 절연막 스페이서의 양쪽 반도체기판에 고농도의 불순물영역을 형성하는 공정과,Forming a high concentration impurity region on both semiconductor substrates of the insulating film spacer;
상기 반도체기판에서 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분에 다결정실리콘을 선택적으로 성장시켜 제1콘택 플러그를 형성하는 공정과,Forming a first contact plug by selectively growing polycrystalline silicon in a portion of the semiconductor substrate, the bit line contact and the storage electrode contact;
전체표면 상부에 상기 제1콘택 플러그를 노출시키는 절연막 패턴을 형성하는 공정과,Forming an insulating film pattern exposing the first contact plug on an entire surface thereof;
상기 제1콘택 플러그와 접속되는 제2콘택 플러그를 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a second contact plug connected to the first contact plug.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3a 내지 도 3d 는 본 발명에 따른 반도체소자의 콘택 플러그 제조방법을 도시한 단면도이다.3A to 3D are cross-sectional views illustrating a method for manufacturing a contact plug of a semiconductor device according to the present invention.
먼저, 반도체기판(41)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판(41)에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 절연막(42)을 형성하고, 전체표면 상부에 게이트 절연막(43)을 형성한 다음, 게이트 전극(44)과 마스크 절연막(45)의 적층구조를 형성한 후, 상기 적층구조 양쪽 반도체기판(41)에 LDD 영역이 되는 저농도 불순물층(도시않됨)을 형성한 후, 상기 전체표면에 절연막을 증착한 다음, 전면식각을 실시하여 상기 적층구조의 측면에 절연막 스페이서(46)를 형성한다. 상기 마스크 절연막(45)은 후속공정인 선택적인 에피공정시 상기 게이트 전극(44) 상부에 다결정실리콘이 성장하는 것을 방지하기 위해 형성한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 41 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the semiconductor substrate 41. A device isolation insulating film 42 is formed on a portion intended as the device isolation region, a gate insulating film 43 is formed over the entire surface, and a stacked structure of the gate electrode 44 and the mask insulating film 45 is formed. Then, after forming a low concentration impurity layer (not shown) that becomes an LDD region on both semiconductor substrates 41 of the stacked structure, an insulating film is deposited on the entire surface, and then subjected to full surface etching to the side of the stacked structure. The insulating film spacer 46 is formed. The mask insulating layer 45 is formed to prevent polycrystalline silicon from growing on the gate electrode 44 during a subsequent epitaxial process.
그 후, 상기 절연막 스페이서(46) 양쪽 반도체기판(41)에 고농도 불순물영역(도시않됨)을 형성한다. (도 3a참조)Thereafter, a high concentration impurity region (not shown) is formed in both semiconductor substrates 41 of the insulating film spacer 46. (See Figure 3a)
다음, 상기 게이트 전극(44) 사이로 노출되어 있는 반도체기판(41)에서 비트라인 콘택 및 저장전극 콘택으로 예정되어 있는 부분에 다결정실리콘층을 선택적으로 성장시켜 제1콘택 플러그(47)를 형성한다. (도 3b참조)Next, a first contact plug 47 is formed by selectively growing a polysilicon layer on a portion of the semiconductor substrate 41 exposed between the gate electrodes 44 as a bit line contact and a storage electrode contact. (See Figure 3b)
그 다음, 전체표면 상부에 BPSG(borophospho silicate glass)를 이용하여 층간절연막(48)을 형성하고, 상기 층간절연막(48) 상부에 상기 제1콘택 플러그(47)를 노출시키는 감광막 패턴(49)을 형성한다.Next, an interlayer insulating layer 48 is formed on the entire surface by using borophospho silicate glass (BPSG), and a photoresist pattern 49 exposing the first contact plug 47 is formed on the interlayer insulating layer 48. Form.
다음, 상기 감광막 패턴(49)을 식각마스크로 사용하여 상기 층간절연막(48)을 식각하여 상기 제1콘택 플러그(47)를 노출시킨다. (도 3c참조)Next, the interlayer insulating layer 48 is etched using the photoresist pattern 49 as an etch mask to expose the first contact plug 47. (See Figure 3c)
그 다음, 상기 감광막 패턴(49)을 제거하고, 전체표면 상부에 상기 제1콘택 플러그(47)와 접촉되는 다결정실리콘층을 형성한다.Next, the photoresist pattern 49 is removed and a polysilicon layer in contact with the first contact plug 47 is formed on the entire surface.
그 후, 전면식각공정이나 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정을 실시하여 제2콘택 플러그(50)를 형성한다. (도 3d참조)Thereafter, a second contact plug 50 is formed by performing a front surface etching process or a chemical mechanical polishing process. (See FIG. 3D)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 콘택 플러그 제조방법은, 반도체기판 상부에 게이트전극과 그 상부에 마스크 절연막 패턴이 적층되어 있고 절연 스페이서를 구비하는 구조로 형성하고, 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분의 반도체기판에 다결정실리콘을 선택적으로 성장시켜 제1콘택 플러그를 형성한 다음, 전체표면 상부에 상기 제1콘택 플러그를 노출시키는 절연막 패턴을 형성한 후, 상기 제1콘택 플러그와 접속되는 제2콘택 플러그를 형성함으로써 콘택을 형성하기 위한 식각공정이 생략되어 접합의 손상을 방지하여 접합 누설전류를 감소시키며, 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a contact plug of a semiconductor device according to the present invention, a gate electrode and a mask insulating film pattern are stacked on the semiconductor substrate, and a structure including an insulating spacer is formed, and bit line contact and storage are formed. The first contact plug is formed by selectively growing polycrystalline silicon on a semiconductor substrate of a portion intended as an electrode contact, and then forming an insulating layer pattern exposing the first contact plug on the entire surface, and then forming the first contact plug. By forming the second contact plug to be connected to the etch process, the etching process for forming the contact is omitted, thereby preventing damage to the junction, thereby reducing the junction leakage current, thereby improving the characteristics and reliability of the semiconductor device.
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| KR1019980045594A KR20000027639A (en) | 1998-10-28 | 1998-10-28 | Method for manufacturing contact plug of semiconductor devices |
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| KR1019980045594A KR20000027639A (en) | 1998-10-28 | 1998-10-28 | Method for manufacturing contact plug of semiconductor devices |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100369865B1 (en) * | 2000-12-29 | 2003-01-30 | 주식회사 하이닉스반도체 | Method for forming a plug |
| KR100460066B1 (en) * | 2002-07-19 | 2004-12-04 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
-
1998
- 1998-10-28 KR KR1019980045594A patent/KR20000027639A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100369865B1 (en) * | 2000-12-29 | 2003-01-30 | 주식회사 하이닉스반도체 | Method for forming a plug |
| KR100460066B1 (en) * | 2002-07-19 | 2004-12-04 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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