KR20000045365A - Method for forming transistor - Google Patents
Method for forming transistor Download PDFInfo
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- KR20000045365A KR20000045365A KR1019980061923A KR19980061923A KR20000045365A KR 20000045365 A KR20000045365 A KR 20000045365A KR 1019980061923 A KR1019980061923 A KR 1019980061923A KR 19980061923 A KR19980061923 A KR 19980061923A KR 20000045365 A KR20000045365 A KR 20000045365A
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- forming
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- gate electrode
- mask
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로서, 특히 게이트 전극을 형성하고 질화막과 산화막의 적층구조를 형성한 후, 상기 산화막을 전면식각하여 스페이서를 형성하여, 상기 질화막을 소오스/드레인영역을 형성하기 위한 이온주입공정에서는 반도체기판을 보호하기 위한 버퍼층으로 사용하고, 평탄화막 형성시에는 확산방지막으로 사용하고, 콘택식각공정에서는 반도체기판이 과도식각으로 인하여 손상되는 것을 방지하여 소자의 특성 및 신뢰성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device. In particular, after forming a gate electrode, forming a stacked structure of a nitride film and an oxide film, etching the entire surface of the oxide film to form a spacer to form a source / drain region of the nitride film. In the ion implantation process, it is used as a buffer layer to protect the semiconductor substrate. In the planarization film formation, it is used as a diffusion barrier. In the contact etching process, the semiconductor substrate is prevented from being damaged due to overetching. It is about how to improve.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광장치의 렌즈 구경(numerical aperture : NA, 개구수) 에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength? And the process variable k of the light source of the reduced exposure apparatus, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.
[ R = k * λ / NA , R = 해상도, λ = 광원의 파장, NA = 개구수 ][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365 ㎚ 인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5 ㎛ 정도가 한계이다. 그리고, 0.5 ㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet, DUV), 예를 들어 파장이 248 ㎚ 인 KrF 레이저나 193 ㎚ 인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL 이라 함)방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass : SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resister : 이하 TLR 이라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. About μm is the limit. In order to form a fine pattern of 0.5 µm or less, an exposure apparatus using a deep ultra violet (DUV), for example, a KrF laser having a wavelength of 248 nm or an ArF laser having 193 nm as a light source, is used. The method and the contrast enhancement layer (hereinafter referred to as CEL) method for forming a separate thin film on the wafer which can improve the image contrast or the S.O. Tri-layer resister (hereinafter referred to as TLR) method with an intermediate layer such as on glass (SOG) or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주요 배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고 엄격한 정렬이 요구되어 공정 여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size and spacing between the main wiring as the device is highly integrated, and the aspect ratio, which is a ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lensdistortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration) 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes provide misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, and matching between masks to maintain spacing. The mask is formed by considering factors such as registration.
이하, 종래의 기술에 따른 반도체소자의 트랜지스터 형성방법에 대해 설명하기로 한다.Hereinafter, a method of forming a transistor of a semiconductor device according to the related art will be described.
먼저, 반도체기판에 소자분리절연막을 형성하고, 노출된 반도체기판의 상부에 게이트 절연막과 다결정실리콘층을 적층한 다음, 패턴닝 공정으로 상기 다결정실리콘층과 게이트 절연막을 식각하여 게이트 전극을 형성한다.First, a device isolation insulating film is formed on a semiconductor substrate, a gate insulating film and a polysilicon layer are stacked on the exposed semiconductor substrate, and then the polysilicon layer and the gate insulating film are etched by a patterning process to form a gate electrode.
다음, 상기 게이트 전극의 양측의 반도체기판에 소오스/드레인을 형성한다. 여기서, 상기 소오스/드레인을 엘.디.디.(lightly doped drain, 이하 LDD 라함)구조로 형성할 수도 있으며, 이를 위해서는 게이트 전극 패터닝후 저농도 불순물을 주입하면 된다.Next, a source / drain is formed on the semiconductor substrates on both sides of the gate electrode. The source / drain may be formed of a lightly doped drain (LDD) structure. For this purpose, a low concentration of impurities may be injected after the gate electrode patterning.
그 다음, 상기 게이트 전극의 양측벽에 스페이서를 형성하고, 전표면을 평탄화시키는 평탄화막을 형성한다.Next, spacers are formed on both sidewalls of the gate electrode, and a planarization film for planarizing the entire surface is formed.
그리고, 반도체기판에서 콘택으로 예정된 부분 상의 평탄화막을 제거하여 콘택홀을 형성하고, 상기 반도체기판과 접속되는 콘택을 형성한다.The planarization film on the portion of the semiconductor substrate, which is supposed to be a contact, is removed to form a contact hole, thereby forming a contact connected to the semiconductor substrate.
상기와 같은 종래기술에 따른 반도체소자의 트랜지스터 형성방법은, 반도체소자가 점차 고집적화되어 감에 따라 게이트 전극 간에 콘택홀을 형성하기 위한 식각공정시 과도식각공정 또는 오배열(misalign)으로 스페이서 및 반도체기판이 식각되어 게이트 전극이 손상될 수 있고, 반도체기판이 손상되어 누설전류가 발생될 수 있다. 또한 평탄화막의 형성공정시 상기 평탄화막에서 불순물이 확산되기 쉬워 소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.In the method of forming a transistor of a semiconductor device according to the prior art as described above, a spacer and a semiconductor substrate are subjected to a transient etching process or misalignment during an etching process for forming a contact hole between gate electrodes as the semiconductor device is gradually integrated. The etching may damage the gate electrode, and damage the semiconductor substrate to generate a leakage current. In addition, impurities are easily diffused in the planarization film during the formation of the planarization film, thereby degrading the characteristics and reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 게이트 전극을 형성한 다음, 상기 게이트 전극의 측벽에 질화막/산화막 적층구조의 스페이서를 형성함으로써 콘택형성공정 및 소오스/드레인을 형성하기 위한 임플란트공정에서 반도체기판의 손상을 방지하고, 평탄화막으로부터 불순물이 확산되는 것을 방지하며, 금속배선 콘택홀의 식각공정시 과도식각으로 반도체기판이 손상되는 것을 방지하여 소자의 특성 및 신뢰성을 향상시키는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by forming a gate electrode, and then forming a spacer of the nitride film / oxide layer structure on the sidewall of the gate electrode forming process for forming a contact and source / drain To prevent damage to the semiconductor substrate, to prevent impurities from diffusing from the planarization layer, and to prevent damage to the semiconductor substrate due to excessive etching during the etching process of the metal wiring contact hole, thereby improving the characteristics and reliability of the device. The purpose is to provide a formation method.
도 1 내지 도 7 은 본 발명에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.1 to 7 are cross-sectional views showing a transistor forming method of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11 : 반도체기판 13 : 소자분리절연막11: semiconductor substrate 13: device isolation insulating film
15 : 게이트 절연막 17 : 게이트 전극15 gate insulating film 17 gate electrode
19 : 마스크 절연막 21 : 저농도 불순물영역19 mask insulating film 21 low concentration impurity region
23 : 질화막 25 : 산화막23 nitride film 25 oxide film
27 : 소오스/드레인영역 29 : 평탄화막27 source / drain region 29 planarization film
30 : 콘택홀 31 : 금속층30: contact hole 31: metal layer
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
반도체기판 상부에 게이트 전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate;
상기 게이트 전극 양쪽 반도체기판의 저농도 불순물을 이온주입하는 공정과,Ion implanting low concentration impurities of both the semiconductor substrates of the gate electrodes;
상기 구조 전표면에 제1절연막과 제2절연막을 형성하는 공정과,Forming a first insulating film and a second insulating film on the entire surface of the structure;
상기 제2절연막을 전면식각하여 상기 게이트 전극 측벽에 제2절연막 스페이서를 형성하는 공정과,Forming a second insulating film spacer on the sidewall of the gate electrode by etching the entire surface of the second insulating film;
상기 제2절연막 스페이서의 양쪽 반도체기판에 고농도 불순물을 이온주입하는 공정과,Ion implanting a high concentration of impurities into both semiconductor substrates of the second insulating film spacer;
상기 구조 전표면에 평탄화막을 형성하는 공정과,Forming a planarization film on the entire surface of the structure;
상기 소오스/드레인영역에서 금속배선 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 평탄화막을 식각하되, 과도식각공정으로 상기 제1절연막을 제거하여 금속배선 콘택홀을 형성하는 공정과,Etching the planarization layer by using a contact mask that exposes a predetermined portion of the source / drain region as a metal wiring contact using an etch mask, and removing the first insulating layer by a transient etching process to form a metal wiring contact hole;
상기 구조 상부에 상기 콘택홀이 매립되도록 금속층을 형성하는 공정과,Forming a metal layer to fill the contact hole on the structure;
상기 금속층을 금속배선 마스크를 이용하여 패터닝하는 공정을 포함하는 것을 특징으로 한다.And patterning the metal layer using a metallization mask.
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.
도 1 내지 도 7 은 본 발명에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다.1 to 7 are cross-sectional views showing a transistor forming method of a semiconductor device according to the present invention.
먼저, 반도체기판(11)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 상기 반도체기판(11)에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 절연막(13)을 형성하고, 상기 구조 전표면에 게이트 절연막(15)을 형성한 다음, 전면에 게이트 전극용 도전층 및 마스크 절연막의 적층구조를 형성한다. 이때, 상기 소자분리절연막(13)은 로코스(LOCal Oxidation of Silicon, LOCOS) 또는 얕은 트랜치소자분리(shallow tranch isolation, STI)방법으로 형성하고, 상기 게이트 전극용 도전층은 다결정실리콘층 또는 폴리사이드막을 사용한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region. A device isolation insulating film 13 is formed on a portion intended as the device isolation region, a gate insulating film 15 is formed on the entire surface of the structure, and then a stacked structure of a conductive layer and a mask insulating film for gate electrodes is formed on the entire surface. do. In this case, the device isolation insulating layer 13 is formed by LOCal (LOCal Oxidation of Silicon, LOCOS) or shallow trench isolation (STI) method, and the conductive layer for the gate electrode is a polysilicon layer or a polyside. Use a membrane.
다음, 게이트 전극용 마스크를 이용하여 상기 적층구조를 식각하여 게이트 전극(17) 및 마스크 절연막 패턴(19)을 형성한다.Next, the stack structure is etched using a gate electrode mask to form a gate electrode 17 and a mask insulating layer pattern 19.
그 다음, 상기 게이트 전극(17)과 마스크 절연막 패턴(19) 양쪽 반도체기판(11)에 저농도 불순물을 이온주입하여 저농도 불순물영역(21)을 형성한다. (도 1참조)Next, a low concentration impurity region 21 is formed by ion implanting low concentration impurities into both the semiconductor substrate 11 of the gate electrode 17 and the mask insulating film pattern 19. (See Fig. 1)
다음, 상기 구조 전표면에 질화막(23)을 50 ∼ 150Å 두께로 형성한다. 이때, 상기 질화막(23)은 후속 공정으로 형성되는 산화막과 식각선택비차이가 큰 박막을 이용하여 형성할 수 있다.Next, the nitride film 23 is formed in the said structure whole surface in 50-150 micrometers thickness. In this case, the nitride layer 23 may be formed using a thin film having a large difference in etching selectivity from an oxide layer formed in a subsequent process.
그 다음, 상기 질화막(23) 상부에 산화막(25)을 형성한다. (도 2참조)Next, an oxide film 25 is formed on the nitride film 23. (See Fig. 2)
그리고, 상기 산화막(25)을 전면식각하여 상기 게이트 전극(17 및 마스크 절연막 패턴(19)의 측벽에 산화막(25) 스페이서를 형성한다. 이때, 상기 질화막(23)을 식각방지막으로 사용하여 상기 식각공정시 상기 반도체기판(11)이 손상되는 것을 방지한다.The entire surface of the oxide layer 25 is etched to form spacers of the oxide layer 25 on the sidewalls of the gate electrode 17 and the mask insulating layer pattern 19. At this time, the nitride layer 23 is used as an etch stop layer. The semiconductor substrate 11 is prevented from being damaged during the process.
다음, 상기 산화막(25) 스페이서의 양쪽 반도체기판(11)에 고농도의 불순물을 이온주입하여 소오스/드레인영역(27)을 형성한다. 상기 이온주입공정시 상기 반도체기판(11) 상부에 남아있는 질화막(23)이 버퍼층으로 사용되어 상기 반도체기판(11)의 표면을 보호한다. (도 3참조)Next, a high concentration of impurities are ion implanted into both semiconductor substrates 11 of the spacer of the oxide film 25 to form the source / drain regions 27. In the ion implantation process, the nitride film 23 remaining on the semiconductor substrate 11 is used as a buffer layer to protect the surface of the semiconductor substrate 11. (See Fig. 3)
그 다음, 상기 구조 전표면에 평탄화막(29)을 형성한 후, 플로우시켜 평탄화한다. 상기 평탄화막(29)은 보론(B) 및 인(P)이 도핑되어 있는 BPSG(borophospho silicate glass, 이하 BPSG 라 함)로 형성한다. 상기 평탄화막(29)의 형성공정시 상기 질화막(23)이 확산방지막으로 사용되어 상기 평탄화막(29)에서 불순물이 상기 반도체기판(11)으로 확산되는 것을 방지한다. (도 4참조)Next, the planarization film 29 is formed on the entire surface of the structure, and then flows to planarize it. The planarization layer 29 is formed of borophospho silicate glass (BPSG) doped with boron (B) and phosphorus (P). During the formation of the planarization layer 29, the nitride layer 23 is used as a diffusion barrier layer to prevent impurities from diffusing into the semiconductor substrate 11 in the planarization layer 29. (See Fig. 4)
다음, 상기 소오스/드레인영역(27)에서 금속배선 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 평탄화막(29)을 식각하여 콘택홀(30)을 형성한다. 이때, 상기 식각공정시 상기 질화막(23)이 식각방지막으로 사용되어 상기 반도체기판(11)을 보호한다. 그리고, 과도식각공정으로 인하여 식각공정후 상기 질화막(23)이 제거되어 상기 반도체기판(11)이 노출된다. (도 5참조)Next, the planarization layer 29 is etched using a contact mask that exposes a portion of the source / drain region 27 to be a metal wiring contact to form a contact hole 30. In this case, the nitride film 23 is used as an etch stop layer in the etching process to protect the semiconductor substrate 11. After the etching process, the nitride layer 23 is removed to expose the semiconductor substrate 11 due to the transient etching process. (See Fig. 5)
그 다음, 전체표면 상부에 상기 콘택홀(30)이 매립되도록 금속층(31)을 형성한다. (도 6참조)Next, the metal layer 31 is formed to fill the contact hole 30 on the entire surface. (See FIG. 6)
그 후, 상기 금속층(31)을 금속배선 마스크를 식각마스크로 식각한다. (도 7참조)Thereafter, the metal layer 31 is etched with a metal wiring mask as an etching mask. (See Fig. 7)
본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 반도체기판에 게이트 전극을 형성하고, 전면에 질화막과 산화막을 형성한 다음, 상기 질화막을 식각방지막으로 상기 산화막을 전면식각하여 상기 게이트 전극이 측벽에 스페이서를 형성하고, 상기 스페이서의 양쪽 반도체기판에 고농도의 불순물을 이온주입하여 소오스/드레인영역을 형성하되, 상기 질화막을 이온주입공정에 대한 버퍼층을 사용하여 반도체기판이 손상되는 것을 방지하며, 상기 구조 전표면에 평탄화막을 형성한 후 상기 소오스/드레인영역에서 금속배선 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 이용하여 상기 평탄화막을 식각하되, 과도식각공정을 실시하여 상기 질화막을 제거하여 금속배선 콘택홀을 형성함으로써 상기 평탄화막 형성후 상기 평탄화막에서 반도체기판으로 불순물이 확산되는 것과, 상기 콘택공정시 과도식각공정으로 인하여 반도체기판이 손상되는 것을 방지하여 누설전류가 발생하는 것을 방지하고, 콘택의 공정 마진을 향상시켜 소자의 수율 및 신뢰성을 향상시키는 이점이 있다.In the method of forming a transistor of a semiconductor device according to the present invention, a gate electrode is formed on a semiconductor substrate, a nitride film and an oxide film are formed on the entire surface, and the nitride film is etched entirely with an etch stop layer so that the gate electrode is spacerd on a sidewall. Form a source / drain region by implanting a high concentration of impurities into both semiconductor substrates of the spacer, and preventing the semiconductor substrate from being damaged by using the nitride layer as a buffer layer for an ion implantation process. After the planarization layer is formed on the surface, the planarization layer is etched by using a contact mask that exposes a predetermined portion of the source / drain region as a metal interconnection contact, and the nitride layer is removed by performing an overetch process to remove the metallization contact hole. By forming the planarization film and then penetrating the planarization film. Advantages of improving the yield and reliability of the device by preventing impurities from being diffused into the substrate and preventing damage to the semiconductor substrate due to the over-etching process during the contact process to prevent leakage current, and improving the process margin of the contact. There is this.
Claims (7)
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| KR1019980061923A KR20000045365A (en) | 1998-12-30 | 1998-12-30 | Method for forming transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030050780A (en) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
| KR100713327B1 (en) * | 2002-12-30 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for making transistor in semiconductor |
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1998
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030050780A (en) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
| KR100713327B1 (en) * | 2002-12-30 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for making transistor in semiconductor |
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