KR20010059453A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR20010059453A KR20010059453A KR1019990066958A KR19990066958A KR20010059453A KR 20010059453 A KR20010059453 A KR 20010059453A KR 1019990066958 A KR1019990066958 A KR 1019990066958A KR 19990066958 A KR19990066958 A KR 19990066958A KR 20010059453 A KR20010059453 A KR 20010059453A
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- Prior art keywords
- pattern
- layer
- plug
- silicide layer
- contact
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 229920000642 polymer Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 238000003860 storage Methods 0.000 claims description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 52
- 239000010408 film Substances 0.000 description 18
- 239000012535 impurity Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 도프트다결정실리콘층으로 구성되는 콘택플러그의 사이에 실리사이드층패턴을 형성하여 상기 콘택플러그 내의 불순물이 접합영역으로 확산되는 것을 억제하여 누설전류특성 및 소자의 동작특성을 향상시키는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a silicide layer pattern is formed between a contact plug composed of a doped polysilicon layer to suppress diffusion of impurities in the contact plug into a junction region, thereby preventing leakage current characteristics and A method of manufacturing a semiconductor device for improving the operation characteristics of the device.
최근의 반도체장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체장치의 제조공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R) 은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture : NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.
[ R = k*λ/NA, R = 해상도, λ = 광원의 파장, NA = 개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.5, 0.3㎛ 정도가 한계이고, 0.3㎛이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet : DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하거나, 공정상의 방법으로는 노광마스크(photo mask)를 위상 반전 마스크(phase shift mask)를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer, 이하 CEL이라 함)방법이나 두 층의 감광막 사이에 SOG 등의 중간층을 개재시킨 삼층레지스트(tri layer resist, TLR) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.5 and 0.3 µm, respectively. Exposure is limited using a deep ultra violet (DUV) light, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source to form a fine pattern of 0.3 μm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가하기 때문에 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소되는 문제점이 있다.In addition, the contact holes connecting the upper and lower conductive wirings have a multi-layered structure due to the high integration of devices, and the gap between the size of the contact holes and the peripheral wirings is reduced and the aspect ratio, which is the ratio of the diameter and depth of the contact holes, is increased. In the highly integrated semiconductor device having the conductive wiring of, a precise and strict alignment between the masks in the manufacturing process is required to form a contact, thereby reducing the process margin.
이러한 이유로 256M DRAM의 제조에는 비트라인과 저장전극 콘택을 형성하는 경우 콘택플러그를 사용하게 된다. 상기 콘택플러그는 게이트전극을 형성한 다음 비트라인 콘택과 저장전극 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성하고, 전면에 도전층을 형성한 다음, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 제거하여 비트라인 콘택플러그와 저장전극 콘택플러그를 형성한다.For this reason, contact plugs are used to form 256M DRAM when forming bit line and storage electrode contacts. The contact plug forms an interlayer insulating film having a contact hole exposing a portion intended as a bit line contact and a storage electrode contact after forming a gate electrode, a conductive layer is formed on the front surface, and then chemical mechanical polishing The bit line contact plugs and the storage electrode contact plugs are formed by a polishing process.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 콘택플러그를 형성하기 위해 다결정실리콘층을 증착하는 공정 및 후속 열처리공정에 의해 콘택플러그 내에 함유되어 있는 불순물이 반도체기판의 접합영역에 확산되어 접합영역의 도핑농도를 증가시켜 접합 특성을 열화시킨다. 상기와 같이 접합영역의 도핑농도가 증가하면 면저항(Rs)이 감소하는 이점은 있지만, 외확산(out-diffusion)이 많이 되서 접합영역의 특성은 열화되고, 접합영역의 도핑농도가 감소하면 면저항이 증가하는 단점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, impurities contained in a contact plug are diffused into a junction region of a semiconductor substrate by a process of depositing a polysilicon layer to form a contact plug and a subsequent heat treatment process. Increasing the doping concentration of the region degrades the bonding properties. As described above, when the doping concentration of the junction region is increased, the sheet resistance (Rs) decreases, but the out-diffusion increases, so the properties of the junction region are deteriorated, and when the doping concentration of the junction region is decreased, the sheet resistance is decreased. There is an increasing disadvantage.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 콘택플러그의 형성공정시 도핑된 플러그폴리 사이에 실리사이드막을 개재시켜 플러그폴리의 증착공정 및 후속 열공정에 의해 접합영역으로 확산되는 불순물을 상기 실리사이드막에 분산시켜 상기 접합영역의 불순물농도가 높아지는 것을 방지하여 접합누설전류특성을 향상시키고, 트랜지스터의 동작특성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by the silicide film interposed between the doped plug poly during the formation of the contact plug, the silicide diffused to the junction region by the deposition process of the plug poly and subsequent thermal process SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the impurity concentration in the junction region is prevented from being dispersed in a film to improve the junction leakage current characteristic and the operation characteristic of the transistor.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명 ><Description of the code for the main part of the drawing>
11 : 반도체기판 13 : 소자분리막11: semiconductor substrate 13: device isolation film
15 : 게이트 절연막패턴 17 : 게이트전극15 gate insulating film pattern 17 gate electrode
19 : 제1실리사이드층 패턴 21 : 캐핑다결정실리콘층패턴19: first silicide layer pattern 21: capping polysilicon layer pattern
23 : 마스크절연막패턴 24 : LDD영역23 mask insulating film pattern 24 LDD region
25 : 절연막스페이서 27 : 제1플러그다결정실리콘층25 insulating film spacer 27 first plug polycrystalline silicon layer
28 : 제1콘택플러그 29 : 제2실리사이드층28: first contact plug 29: second silicide layer
30 : 제2콘택플러그 31 : 제2플러그다결정실리콘층30 second contact plug 31 second plug polycrystalline silicon layer
32 : 제2실리사이드층패턴 33 : 감광막패턴32: second silicide layer pattern 33: photoresist pattern
35 : 폴리머35 polymer
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 게이트절연막, 게이트전극, 제1실리사이드층패턴, 캐핑다결정실리콘층패턴과 마스크절연막패턴의 적층구조를 형성하고, 상기 적층구조의 양측 반도체기판에 LDD영역을 형성하는 공정과,Forming a stacked structure of a gate insulating film, a gate electrode, a first silicide layer pattern, a capping polysilicon layer pattern and a mask insulating film pattern on the semiconductor substrate, and forming LDD regions on both semiconductor substrates of the stacked structure;
상기 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the laminated structure;
전체표면 상부에 제1플러그다결정실리콘층을 형성한 다음, 전면식각공정을 실시하여 제1콘택플러그를 형성하는 공정과,Forming a first contact polysilicon layer on the entire surface, and then performing a front etching process to form a first contact plug;
전체표면 상부에 제2실리사이드층과 제2플러그다결정실리콘층을 순차적으로 형성하는 공정과,Sequentially forming a second silicide layer and a second plug polycrystalline silicon layer on the entire surface;
상기 제2플러그다결정실리콘층 상부에 비트라인콘택 및 저장전극 콘택으로 예정되는 부분을 보호하는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the second plug polycrystalline silicon layer, the photoresist pattern protecting a portion intended as a bit line contact and a storage electrode contact;
상기 감광막패턴의 측벽에 폴리머를 형성하는 공정과,Forming a polymer on sidewalls of the photoresist pattern;
상기 감광막패턴과 폴리머를 식각마스크로 상기 제2플러그다결정실리콘층과 제2실리사이드층을 식각하여 상기 제1콘택플러그와 접속되는 제2실리사이드층패턴과 제2콘택플러그를 형성하는 공정과,Etching the second plug polycrystalline silicon layer and the second silicide layer using the photoresist pattern and the polymer as an etch mask to form a second silicide layer pattern and a second contact plug connected to the first contact plug;
상기 감광막패턴과 폴리머를 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the photoresist pattern and the polymer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(11)에서 소자분리 영역으로 예정되어 있는 부분 상에 소자분리막(13)을 형성하고, 반도체기판(11)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한다.First, a device isolation film 13 is formed on a portion of the semiconductor substrate 11 that is intended as an isolation region, and ion implantation of a desired type of impurities into a desired portion of the semiconductor substrate 11 forms a channel portion of a well and a transistor. And an impurity in a desired shape in a lower portion of the device isolation region.
다음, 상기 반도체기판(11) 상부에 게이트절연막(도시안됨), 게이트전극용 도프트다결정실리콘층(도시안됨), 제1실리사이드층(도시안됨), 캐핑다결정실리콘층(도시안됨) 및 마스크절연막(도시안됨)의 적층구조를 형성한다. 상기 제1실리사이드층은 텅스텐실리사이드층으로 형성한다.Next, a gate insulating film (not shown), a doped polysilicon layer (not shown), a first silicide layer (not shown), a capping polysilicon layer (not shown), and a mask insulating film are formed on the semiconductor substrate 11. A laminated structure (not shown) is formed. The first silicide layer is formed of a tungsten silicide layer.
그 다음, 게이트전극으로 예정되는 부분을 보호하는 게이트전극마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막패턴(23), 캐핑다결정실콘층패턴(21),제1실리사이드층패턴(21), 게이트전극(15) 및 게이트절연막패턴(15)의 적층구조패턴을 형성한다.Next, the stack structure is etched using a gate electrode mask that protects a portion intended as a gate electrode by using an etch mask, thereby masking the insulating film pattern 23, the capping polysilicon layer pattern 21, the first silicide layer pattern 21, and the like. A stacked structure pattern of the gate electrode 15 and the gate insulating film pattern 15 is formed.
다음, 상기 적층구조패턴의 양측 반도체기판(11)에 저농도의 불순물을 이온주입하여 LDD영역(24)을 형성한다.Next, the LDD region 24 is formed by ion implanting impurities of low concentration into both semiconductor substrates 11 of the stacked structure pattern.
그 다음, 상기 적층구조패턴의 측벽에 절연막스페이서(25)를 형성한다.Next, an insulating film spacer 25 is formed on the sidewalls of the laminated structure pattern.
그 후, 전체표면 상부에 제1플러그다결정실리콘층(27)을 형성한다. 이때, 상기 제1플러그다결정실리콘층(27)은 도프트다결정실리콘층으로 형성한다. (도 1 참조)Thereafter, the first plug polycrystalline silicon layer 27 is formed over the entire surface. In this case, the first plug polycrystalline silicon layer 27 is formed of a doped polycrystalline silicon layer. (See Figure 1)
다음, 상기 제1플러그다결정실리콘층(27)을 전면식각하여 제1콘택플러그(28)를 형성하되, 상기 마스크절연막패턴(23)이 노출되도록 형성한다. (도 2 참조)Next, the first plug polycrystalline silicon layer 27 is etched to form a first contact plug 28, and the mask insulating layer pattern 23 is exposed. (See Figure 2)
그 다음, 전체표면 상부에 제2실리사이드층(29)과 제2플러그다결정실리콘층(31)을 순차적으로 형성한다. 상기 제2실리사이드층(29)은 텅스텐실리사이드층으로 형성하고, 상기 제2플러그다결정실리콘층(31)은 도프트다결정실리콘층으로 형성한다. (도 3 참조)Next, the second silicide layer 29 and the second plug polycrystalline silicon layer 31 are sequentially formed on the entire surface. The second silicide layer 29 is formed of a tungsten silicide layer, and the second plug polycrystalline silicon layer 31 is formed of a doped polycrystalline silicon layer. (See Figure 3)
다음, 상기 제2플러그다결정실리콘층(31) 상부에 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분을 보호하는 감광막패턴(33)을 형성한다. 이때, 상기 감광막패턴(33)을 형성하기 전에 상기 제2플러그다결정실리콘층(31) 상부에 반사방지막으로 산화질화막이 소정 두께 형성된다. (도 4 참조)Next, a photoresist pattern 33 is formed on the second plug polycrystalline silicon layer 31 to protect a portion of the bit plug contact and the storage electrode contact. In this case, before the photoresist pattern 33 is formed, an oxynitride film is formed to have a predetermined thickness on the second plug polycrystalline silicon layer 31 as an anti-reflection film. (See Figure 4)
그 후, 상기 감광막패턴(33)의 측벽에 폴리머(35)를 성장시켜 공정마진을 확보한다. (도 5 참조)Thereafter, the polymer 35 is grown on the sidewalls of the photoresist pattern 33 to secure a process margin. (See Figure 5)
그 다음, 상기 감광막패턴(33)과 폴리머(35)를 식각마스크로 상기 제2플러그다결정실리콘층(31)과 제2실리사이드층(29)을 식각하여 제1콘택플러그(28), 제2실리사이드층패턴(30) 및 제2콘택플러그(32)의 적층구조로 형성된 콘택플러그를 형성하되, 상기 식각공정은 상기 마스크절연막패턴(23)을 식각장벽으로 사용하여 실시한다. 상기와 같이 다결정실리콘층으로 구성되는 콘택플러그의 사이에 실리사이드층을 개재시킴으로써 상기 반도체기판(11)의 활성영역으로 확산되는 불순물의 양을 분산시킨다.Subsequently, the second plug polycrystalline silicon layer 31 and the second silicide layer 29 are etched using the photoresist pattern 33 and the polymer 35 as an etch mask to etch the first contact plug 28 and the second silicide. A contact plug formed of a stacked structure of the layer pattern 30 and the second contact plug 32 is formed, and the etching process is performed using the mask insulating layer pattern 23 as an etching barrier. As described above, the silicide layer is interposed between the contact plugs formed of the polysilicon layer to disperse the amount of impurities diffused into the active region of the semiconductor substrate 11.
다음, 상기 감광막패턴(33)과 폴리머(35)를 제거한다. (도 6 참조)Next, the photoresist pattern 33 and the polymer 35 are removed. (See Figure 6)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 고집적 반도체소자의 비트라인 콘택 및 저장전극콘택으로 예정되는 부분에 접속되는 콘택플러그를 형성하는 공정시 다결정실리콘층으로 구성되는 상기 콘택플러그의 사이에 실리사이드층을 개재시켜 상기 다결정실리콘층에 포함되어 있는 불순물이 접합영역으로 확산되는 것을 분산시켜 접합영역으로의 불순물확산을 억제시켜 접합누설전류 특성을 향상시키고, 콘택플러그의 면저항(Rs)을 감소시켜 반도체소자의 동작특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the contact plug configured of a polysilicon layer in a process of forming a contact plug connected to a portion intended as a bit line contact and a storage electrode contact of a highly integrated semiconductor device. Disperses the diffusion of impurities contained in the polycrystalline silicon layer into the junction region by interposing the silicide layer, thereby suppressing the diffusion of impurities into the junction region, thereby improving junction leakage current characteristics, and improving the sheet resistance (Rs) of the contact plug. There is an advantage to improve the operating characteristics and reliability of the semiconductor device by reducing the.
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| KR100574487B1 (en) * | 2002-07-05 | 2006-04-27 | 주식회사 하이닉스반도체 | Method for forming the MOS transistor in semiconductor device |
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| KR100574487B1 (en) * | 2002-07-05 | 2006-04-27 | 주식회사 하이닉스반도체 | Method for forming the MOS transistor in semiconductor device |
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