KR100333550B1 - Fabricating method for semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device, wherein the first etching process is performed by inducing a polymer in the process of forming the gate electrodes of the NMOS and PMOS transistors in the peripheral circuit region, and ion implantation of a high concentration of impurities is performed. After removing the polymer, a second etching process is performed to form a gate electrode, and then a gate electrode of the cell region is formed, and a low concentration impurity is ion-implanted to form a transistor to form a process margin of a portion scheduled for contact in a subsequent process. It is possible to ensure high integration of semiconductor devices, to stabilize the junction profile, and to control the characteristics of each transistor in the peripheral circuit area by controlling the CD (critical dimension) by improving the layer covering characteristics of the interlayer insulating film. Can be.

Description

Fabrication method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, gate electrodes of a PMOS transistor, an NMOS transistor, and a cell transistor are separately formed, and the gate electrodes of the PMOS transistor and the NMOS transistor are formed by two etching processes, respectively. It relates to a method for manufacturing a semiconductor device that can adjust the characteristics.

The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength? And the process variable k of the light source of the reduced exposure apparatus, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. About μm is the limit. In order to form a fine pattern of 0.5 µm or less, an exposure apparatus using a deep ultra violet (DUV), for example, a KrF laser having a wavelength of 248 nm or an ArF laser having 193 nm as a light source, is used. The method and the contrast enhancement layer (hereinafter referred to as CEL) method for forming a separate thin film on the wafer which can improve the image contrast or the S.O. Tri-layer resister (hereinafter referred to as TLR) method with an intermediate layer such as on glass (SOG) or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size and spacing between the main wiring as the device is highly integrated, and the aspect ratio, which is a ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes provide misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, and matching between masks to maintain spacing. The mask is formed by considering factors such as registration.

Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described.

First, a device isolation film is formed on a semiconductor substrate, a stacked structure of a gate oxide film, a conductive layer, and a mask insulating film is formed on the exposed semiconductor substrate, and then the stacked structure is etched by a patterning process to form a gate electrode.

Next, a low concentration impurity region is formed by ion implanting low concentration impurities into both semiconductor substrates of the gate electrode.

Next, a spacer film is formed on both sidewalls of the gate electrode, and a high concentration of impurities are ion implanted into both semiconductor substrates of the insulating film spacer to form a source / drain region.

Next, an interlayer insulating film is formed over the entire surface to planarize.

Then, a contact hole is formed by removing the interlayer insulating film on the portion of the semiconductor substrate, which is supposed to be a contact, to form a contact connected to the semiconductor substrate.

However, in the method of manufacturing a semiconductor device according to the related art as described above, since the insulating layer spacer formed on the sidewall of the gate electrode reduces the width between word lines, the process margin of the active region into which subsequent bit line contacts and storage electrode contacts enter. This decreases, thereby lowering the layer covering properties. In addition, since relatively high temperature processes such as deposition and oxidation processes are used, the dopant in the junction region is diffused, resulting in a change in the profile of the junction region. In addition, since the insulating region spacers having the same thickness are used for the junction regions of the PMOS transistors and the NMOS transistors having different characteristics, it is difficult to control the characteristics of the transistors, and the productivity is degraded due to a long process time deposition process and an oxidation process. There is this.

In order to solve the above problems of the prior art, the first etching process is performed by inducing a polymer during the formation of the gate electrode of the PMOS transistor and the NMOS transistor to form an anti-reflection film pattern, and then the gate electrode is formed to have a high concentration. Impurities are ion-implanted to form source / drain regions, the polymer is removed, a gate electrode is formed by a secondary etching process, a gate electrode of a cell transistor is formed, and a low concentration of impurities are generally implanted, respectively. It is an object of the present invention to provide a method for manufacturing a semiconductor device which improves the characteristics and reliability of the device by forming a transistor having a junction region suitable for the characteristics of the device.

1 to 14 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.

<Description of Signs of Major Parts of Drawings>

11 semiconductor substrate 13 gate insulating film

15 conductive layer for gate electrode 17 mask insulating film

19: antireflection film 21: first photosensitive film pattern

23 polymer 25 second photosensitive film pattern

27 oxide film 29 nitride film spacer

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

Forming a gate insulating film, a conductive layer, a mask insulating film, and an anti-reflection film over the cell region and the peripheral circuit region of the semiconductor substrate;

Forming a first photoresist pattern on the anti-reflection film in the peripheral circuit region to expose a portion intended to be a junction region of the first conductive MOS transistor region;

Etching the anti-reflection film using the first photoresist pattern as an etching mask, and forming a polymer on sidewalls of the first photoresist pattern and the anti-reflection film;

Etching the mask insulating layer and the conductive layer using the first photoresist pattern and the polymer as an etch mask, followed by ion implantation of a first conductive high concentration impurity and removing the polymer;

Etching the mask insulating layer and the conductive layer using the first photoresist pattern as an etching mask and using the gate insulating layer as an etching barrier;

Removing the first photoresist pattern;

Forming a second photoresist pattern on the entire surface, the second photoresist pattern exposing a portion intended to be a junction region of the second conductive MOS transistor region in the peripheral circuit region;

Etching the anti-reflection film using the second photoresist pattern as an etching mask, and forming a polymer on sidewalls of the first photoresist pattern and the anti-reflection film;

Etching the mask insulating layer and the conductive layer using the second photoresist pattern and the polymer as an etch mask, followed by ion implantation of a second conductive high concentration impurity and removing the polymer;

Etching the mask insulating layer and the conductive layer using the second photoresist pattern as an etch mask and using the gate insulating layer as an etch barrier;

Removing the second photoresist pattern;

Forming a third photoresist pattern on the entire surface of the cell region to expose a portion of the cell region to be a junction region, and etching the anti-reflection film and the mask insulating film by using the third photoresist pattern as an etching mask;

Removing the third photoresist pattern, and then etching the conductive layer using the anti-reflection film as an etching mask and simultaneously removing the anti-reflection film;

Oxidizing the structure and ion implanting the low concentration impurity entirely;

And forming an insulating film spacer on an etching surface of the conductive layer and the mask insulating film.

Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.

1 to 14 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region. An element isolation film (not shown) is formed on the portion intended as the element isolation region.

Next, a gate insulating film 13 is formed on the entire surface of the structure, and a stacked structure of a gate electrode conductive layer 15 and a mask insulating film 17 is formed on the gate insulating film 13, and then an antireflection film 19 ). (See Fig. 1)

Next, a first photoresist pattern 21 is formed on the anti-reflection film 19 to expose a portion of the NMOS transistor to be a junction region. (See Fig. 2)

Next, the anti-reflection film 19 is etched using the first photoresist pattern 21 as an etching mask, while the polymer 23 is formed on sidewalls of the first photoresist pattern 21 and the anti-reflection film 19. Carry out an etching process. In this case, the mask insulating layer 17 may be etched to facilitate the subsequent process. (See Fig. 3)

Next, the laminate structure is etched using the first photoresist pattern 21 and the polymer 23 as an etching mask. The polymer 23 is removed as much as possible during the etching process. (See Fig. 4)

Next, n + impurities are ion implanted into the first photoresist pattern 21 and the polymer 23 to form a high concentration source / drain region. (See Fig. 5)

Next, a washing process is performed to remove the polymer 23. The polymer 23 may be removed before the ion implantation process. (See Figure 6)

Next, the stack structure is etched using the first photoresist pattern 21 as an etch mask to form a gate electrode. In this case, the etching process is performed using the gate insulating layer 13 as an etching barrier. (See Fig. 7)

Next, the first photoresist pattern 21 is removed. (See FIG. 8)

Thereafter, a gate electrode and a high concentration source / drain region are formed in the PMOS transistor region in the same manner as described above. (See FIG. 9)

Next, a second photoresist pattern 25 is formed on the entire surface of the cell region to expose a portion of the cell region to be a junction region of the MOS transistor. (See FIG. 10)

Next, the anti-reflection film 19 and the mask insulating film 17 are etched using the second photoresist pattern 25 as an etch mask, and the second photoresist pattern 25 is removed. (See FIG. 11)

Next, after the second photoresist pattern 25 is removed, the anti-reflection film 19 on the exposed PMOS, NMOS and cell regions is removed.

Next, the gate insulating layer 15 on the cell region is etched using the mask insulating layer 17 pattern as an etch mask. The etching process is performed by using the gate insulating film 13 as an etching barrier.

Thereafter, the sacrificial oxidation process is performed to compensate for the damages in the previous process, and the oxidation process is carried out as a whole to form the oxide film 27 on the entire surface.

Next, by using the oxide film 27 as an ion implantation barrier, impurities of low concentration are implanted into the PMOS, NMOS, and cell regions as a whole. (See FIG. 13)

Thereafter, a nitride film is formed over the entire surface, and the nitride film is etched entirely to form a nitride film spacer 29 on sidewalls of the gate electrode and the mask insulating film. In this case, the nitride film may have a thickness of 10 to 40 nm to facilitate the contact process in a subsequent step. (See FIG. 14)

On the other hand, the anti-reflection film 19 may be removed by performing a transient etching process during the entire surface etching process of the nitride film.

In the method of manufacturing a semiconductor device according to the present invention, in the process of forming the gate electrodes of the NMOS and PMOS transistors in the peripheral circuit region, the polymer is first subjected to the etching process, and then ion implanted with a high concentration of impurities to remove the polymer. Next, after forming the gate electrode by performing the secondary etching process, the gate electrode of the cell region is formed, and the transistor is formed by ion implanting the low concentration impurity in the entire area to secure the process margin of the portion scheduled for contact in the subsequent process. As a result, the layer covering property of the interlayer insulating film is improved to enable high integration of semiconductor devices, to stabilize the junction profile, and to control the characteristics of each transistor in the peripheral circuit area by controlling the CD of the polymer and at the same time, the process time. It can be shortened and the gate electrode is formed by two etching processes. Reduction in the area and a CD bias of the gate electrode between the cell region below 0.01㎛ to such an advantage can be accurately adjusted to the characteristics of the transistors.

Claims (5)

Forming a gate insulating film, a conductive layer, a mask insulating film, and an anti-reflection film over the cell region and the peripheral circuit region of the semiconductor substrate; Forming a first photoresist pattern on the anti-reflection film in the peripheral circuit region to expose a portion intended to be a junction region of the first conductive MOS transistor region; Etching the anti-reflection film using the first photoresist pattern as an etching mask, and forming a polymer on sidewalls of the first photoresist pattern and the anti-reflection film; Etching the mask insulating layer and the conductive layer using the first photoresist pattern and the polymer as an etch mask, followed by ion implantation of a first conductive high concentration impurity and removing the polymer; Etching the mask insulating layer and the conductive layer using the first photoresist pattern as an etching mask and using the gate insulating layer as an etching barrier; Removing the first photoresist pattern; Forming a second photoresist pattern on the entire surface, the second photoresist pattern exposing a portion intended to be a junction region of the second conductive MOS transistor region in the peripheral circuit region; Etching the anti-reflection film using the second photoresist pattern as an etching mask, and forming a polymer on sidewalls of the first photoresist pattern and the anti-reflection film; Etching the mask insulating layer and the conductive layer using the second photoresist pattern and the polymer as an etch mask, followed by ion implantation of a second conductive high concentration impurity and removing the polymer; Etching the mask insulating layer and the conductive layer using the second photoresist pattern as an etch mask and using the gate insulating layer as an etch barrier; Removing the second photoresist pattern; Forming a third photoresist pattern on the entire surface of the cell region to expose a portion of the cell region to be a junction region, and etching the anti-reflection film and the mask insulating film by using the third photoresist pattern as an etching mask; Removing the third photoresist pattern, and then etching the conductive layer using the anti-reflection film as an etching mask and simultaneously removing the anti-reflection film; Oxidizing the structure and ion implanting the low concentration impurity entirely; And forming an insulating film spacer on an etching surface of the conductive layer and the mask insulating film. The method of claim 1, The method of manufacturing a semiconductor device, characterized in that for reducing the CD bias of the gate electrode to 0.01㎛. The method of claim 1, The polymer is a manufacturing method of a semiconductor device, characterized in that to remove the high concentration impurities before implantation. The method of claim 1, The nitride film spacer is a method of manufacturing a semiconductor device, characterized in that the nitride film is deposited by a thickness of 10 to 40nm and then etched by a front etching process. The method according to claim 1 or 4, The anti-reflection film is a method of manufacturing a semiconductor device, characterized in that to remove the over-etching process during the entire surface etching process for forming the nitride film spacer.