KR20020002642A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device Download PDF

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KR20020002642A
KR20020002642A KR1020000036868A KR20000036868A KR20020002642A KR 20020002642 A KR20020002642 A KR 20020002642A KR 1020000036868 A KR1020000036868 A KR 1020000036868A KR 20000036868 A KR20000036868 A KR 20000036868A KR 20020002642 A KR20020002642 A KR 20020002642A
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South Korea
Prior art keywords
mask
pattern
insulating film
gate electrode
bit line
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KR1020000036868A
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Korean (ko)
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이병철
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000036868A priority Critical patent/KR20020002642A/en
Publication of KR20020002642A publication Critical patent/KR20020002642A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a leakage current, by wet-etching a predetermined thickness of a mask insulation layer pattern stacked on a gate electrode after an ion implantation process and by forming a bitline contact hole. CONSTITUTION: A stacked structure of a gate insulation layer, a conductive layer for the gate electrode and a mask insulation layer is formed on the semiconductor substrate(20). The stacked structure is etched to form a stacked structure pattern of a mask insulation layer pattern(24), the gate electrode(23) and a gate insulation layer pattern(22) by using a gate electrode mask as an etch mask. A low-density junction region(21) is formed in the substrate at both sides of the stacked structure pattern, and an insulation layer spacer(25) is formed on the sidewall of the stacked structure pattern. The first interlayer dielectric(26) is formed, and is planarized to expose the mask insulation layer pattern. A predetermined thickness of the mask insulation layer pattern is removed to form a groove(28) by using as an etch mask the first bitline contact mask exposing a portion for a bitline contact on the gate electrode. The second interlayer dielectric is formed. The second interlayer dielectric and the mask insulation layer pattern are etched to form the bitline contact hole by using as an etch mask the second bitline contact mask exposing a portion for the bitline contact on the gate electrode and a portion for the bitline contact in the junction region.

Description

반도체소자의 제조방법{Manufacturing method for semiconductor device}Manufacturing method for semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 비트라인 콘택홀의형성공정 시 게이트전극 상부의 마스크절연막을 미리 소정 두께 제거한 다음, 비트라인 콘택홀을 형성함으로써 비트라인 콘택홀을 형성하기 위한 식각공정 시 반도체기판이 손실되는 것을 방지하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, an etching process for forming a bit line contact hole by forming a bit line contact hole after removing a predetermined thickness of a mask insulating film on an upper portion of a gate electrode in a process of forming a bit line contact hole is performed. The present invention relates to a method for manufacturing a semiconductor device that prevents the semiconductor substrate from being lost.

최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture:NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.

[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선, 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 공정 상의 방법으로는 노광마스크를 위상 반전 마스크를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL이라 함) 방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass: SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resist: 이하 TLR 라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, the micrometer has a limit of about μm, and an exposure apparatus using an ultraviolet ray having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source, or a process As a method of imaging, a method of using a phase inversion mask as an exposure mask and a method of forming a separate thin film on the wafer which can improve image contrast can be used. A tri layer resist method (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers or silicon on a photoresist layer selectively. It has been developed, such as silico-migration method for injection may lower the resolution limit.

또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고, 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화, 마스크간의 정합 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have factors such as misalignment tolerance during mask alignment, lens distortion during exposure process, threshold size change during mask fabrication and photolithography process, and matching between masks to maintain gaps. Consider these to form a mask.

이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

먼저, 반도체기판(10) 상부에 게이트 절연막패턴(12), 게이트 전극(13) 및 마스크 절연막패턴(14)의 적층구조를 형성하고, 상기 적층구조 양측의 반도체기판(10)에 엘.디.디.(lightly doped drain, 이하 LDD 라 함) 영역이 되는 저농도 접합영역(11)을 형성한 후, 상기 적층구조의 측벽에 절연막 스페이서(15)를 형성한다.First, a lamination structure of the gate insulating film pattern 12, the gate electrode 13, and the mask insulating film pattern 14 is formed on the semiconductor substrate 10, and the L.D. After forming the low-concentration junction region 11 serving as a lightly doped drain (LDD) region, an insulating film spacer 15 is formed on the sidewall of the laminated structure.

다음, 전체표면 상부에 제1층간절연막(16)을 형성하고, 화학적 기계적 연마공정으로 평탄화시킨다. 상기 제1층간절연막(16)은 산화막으로 형성한다. (도 1a 참조)Next, a first interlayer insulating film 16 is formed over the entire surface and planarized by a chemical mechanical polishing process. The first interlayer insulating film 16 is formed of an oxide film. (See Figure 1A)

그 다음, 전체표면 상부에 제2층간절연막(17)을 형성한다. 상기 제2층간절연막(17)은 산화막으로 형성한다. (도 1b 참조)Next, a second interlayer insulating film 17 is formed over the entire surface. The second interlayer insulating film 17 is formed of an oxide film. (See FIG. 1B)

다음, 상기 제2층간절연막(17) 상부에 상기 게이트전극(13) 및 반도체기판(10)의 접합영역(11)에서 비트라인 콘택으로 예정되는 부분을 노출시키는 감광막패턴(18)을 형성한다.Next, a photosensitive film pattern 18 is formed on the second interlayer insulating film 17 to expose a portion of the junction region 11 of the gate electrode 13 and the semiconductor substrate 10 to be a bit line contact.

그 다음, 상기 감광막패턴(18)을 식각마스크로 상기 제2층간절연막(17), 제1층간절연막(16) 및 마스크절연막패턴(14)을 식각하여 비트라인 콘택홀(19a, 19b)을 형성한다.Next, the second interlayer insulating layer 17, the first interlayer insulating layer 16, and the mask insulating layer pattern 14 are etched using the photoresist pattern 18 as an etch mask to form bit line contact holes 19a and 19b. do.

상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 소자가 고집적화되어감에 따라 비트라인 콘택과 저장전극 콘택을 직접 형성하지 않고, 각각의 콘택 부분에 콘택플러그를 형성한 다음, 비트라인 콘택과 저장전극콘택을 형성하는 공정이 사용되고 있으나, 최근에는 콘택 플러그 식각공정 시 자기정렬콘택식각(self aligned contact etch)을 용이하게 하기 위해 게이트전극 상부에 마스크절연막패턴을 형성하고, 콘택플러그를 접합영역과 게이트 전극 상부에 형성하였으나, 상기 마스크절연막패턴은 층간절연막보다 식각선택비가 작기 때문에 식각속도가 느린데 비하여 상기 층간절연막의 식각속도가 빨라서 비트라인 콘택홀 형성 후 반도체기판이 손실되어 누설전류가 증가하고 그에 따른 반도체소자의 동작 특성을 저하시키는 문제점이 있다.As described above, the semiconductor device manufacturing method according to the related art does not directly form a bit line contact and a storage electrode contact as the device is highly integrated, and forms a contact plug on each contact portion, and then, Although a process of forming a storage electrode contact is used, in recent years, a mask insulating film pattern is formed on the gate electrode to facilitate self-aligned contact etching during the contact plug etching process, and the contact plug is connected to the junction region. Although formed on the gate electrode, the mask insulating layer pattern has a smaller etching selectivity than the interlayer insulating layer, and thus the etching rate is slower, whereas the etching rate of the interlayer insulating layer is faster, resulting in a loss of the semiconductor substrate after the formation of the bit line contact hole, thereby increasing leakage current. There is a problem of lowering the operation characteristics of the semiconductor device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 비트라인 콘택으로 예정되는 게이트전극 상의 마스크절연막을 소정 두께 식각한 다음, 층간절연막을 형성하고, 비트라인 콘택홀을 형성함으로써 비트라인 콘택홀 형성 후 반도체기판이 손실되는 것을 방지하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.According to the present invention, in order to solve the above problems of the prior art, the mask insulating film on the gate electrode intended as the bit line contact is etched by a predetermined thickness, and then the interlayer insulating film is formed and the bit line contact hole is formed by forming the bit line contact hole. It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents the semiconductor substrate from being lost.

도 1 내지 도 1c 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 1c are cross-sectional views showing a method for manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10, 20 : 반도체기판 11, 21 : 접합영역10, 20: semiconductor substrate 11, 21: junction region

12, 22 : 게이트절연막패턴 13, 23 : 게이트전극12, 22: gate insulating film pattern 13, 23: gate electrode

14, 24 : 마스크절연막패턴 15, 25 : 절연막 스페이서14, 24: mask insulating film pattern 15, 25: insulating film spacer

16, 26 : 제1층간절연막 17, 29 : 제2층간절연막16, 26: first interlayer insulating film 17, 29: second interlayer insulating film

18 : 감광막패턴 19a, 19b, 31, 32 : 비트라인 콘택홀18: photoresist pattern 19a, 19b, 31, 32: bit line contact hole

27 :제1감광막패턴 28 : 홈27: first photosensitive film pattern 28: groove

30 : 제2감광막패턴30: second photosensitive film pattern

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

반도체기판 상부에 게이트 절연막, 게이트전극용 도전층 및 마스크절연막의 적층구조를 형성하고, 게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막패턴, 게이트전극 및 게이트절연막패턴의 적층구조패턴을 형성하는 공정과,A stack structure of a gate insulating film, a conductive layer for a gate electrode, and a mask insulating film is formed on the semiconductor substrate, and the stack structure is etched by using a gate electrode mask as an etch mask to form a stack structure pattern of a mask insulating film pattern, a gate electrode, and a gate insulating film pattern. Forming process,

상기 적층구조패턴의 양쪽 반도체기판에 저농도 접합영역을 형성하고, 상기 적층구조패턴의 측벽에 절연막 스페이서를 형성하는 공정과,Forming a low concentration junction region on both semiconductor substrates of the laminated structure pattern, and forming insulating film spacers on sidewalls of the laminated structure pattern;

전체표면 상부에 제1층간절연막을 형성하고, 상기 마스크절연막패턴이 노출되도록 평탄화시키는 공정과,Forming a first interlayer insulating film over the entire surface, and planarizing the mask insulating film pattern to expose the mask insulating film pattern;

상기 게이트전극 상에서 비트라인 콘택으로 예정되는 부분을 노출시키는 제1비트라인 콘택마스크를 식각마스크로 상기 마스크절연막패턴을 소정 두께 제거하여 홈을 형성하는 공정과,Forming a groove by removing a predetermined thickness of the mask insulating layer pattern with an etch mask using a first bit line contact mask that exposes a portion intended to be a bit line contact on the gate electrode;

전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;

상기 게이트전극 상에서 비트라인 콘택으로 예정되는 부분과 상기 반도체기판의 접합영역에서 비트라인 콘택으로 예정되는 부분을 노출시키는 제2비트라인 콘택마스크를 식각마스크로 상기 제2층간절연막, 제2층간절연막 및 마스크절연막패턴을 식각하여 비트라인 콘택홀을 형성하는 공정을 포함하는 것을 특징으로 한다.The second interlayer dielectric layer, the second interlayer dielectric layer, and the second bit line contact mask exposing a portion intended for the bit line contact on the gate electrode and a portion intended for the bit line contact in the junction region of the semiconductor substrate are etch masks. And etching the mask insulating film pattern to form a bit line contact hole.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

먼저, 반도체기판(20)에서 소자분리 영역으로 예정되어 있는 부분 상에 소자분리 절연막(도시 안됨)을 형성하고, 반도체기판(20)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한 후, 나머지 반도체기판(20)에 게이트 절연막, 게이트전극용 도전층 및 마스크절연막의 적층구조를 순차적으로 형성한다. 이때, 상기 마스크절연막은 질화막으로 형성한다.First, a device isolation insulating film (not shown) is formed on a portion of the semiconductor substrate 20 that is intended as the device isolation region, and ion implantation of a desired type of impurity into a desired portion of the semiconductor substrate 20 is performed to form a well and a transistor. After the impurities are present in desired portions in the channel portion and the lower portion of the device isolation region, the stacked structure of the gate insulating film, the gate electrode conductive layer and the mask insulating film is sequentially formed on the remaining semiconductor substrate 20. In this case, the mask insulating film is formed of a nitride film.

다음, 게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막패턴(24), 게이트전극(23) 및 게이트절연막패턴(22)의 적층구조패턴을 형성한다.Next, the stack structure is etched using the gate electrode mask as an etch mask to form a stack structure pattern of the mask insulating film pattern 24, the gate electrode 23, and the gate insulating film pattern 22.

그 다음, 상기 적층구조패턴의 양측 반도체기판(20)에 저농도 불순물을 이온주입하여 LDD 영역이 되는 접합영역(21)을 형성한 후, 상기 적층구조패턴의 측벽에 절연막 스페이서(25)를 형성한다. 이때, 상기 절연막스페이서(25)는 질화막으로 형성한다.Subsequently, ion-implanted low-concentration impurities into both semiconductor substrates 20 of the laminated structure pattern are formed to form a junction region 21 that becomes an LDD region, and then insulating film spacers 25 are formed on sidewalls of the laminated structure pattern. . At this time, the insulating film spacer 25 is formed of a nitride film.

다음, 전체표면 상부에 제1층간절연막(26)을 증착하고, 화학적 기계적 연마공정으로 평탄화시켜 상기 마스크절연막패턴(24)을 노출시킨다. (도 2a 참조)Next, a first interlayer insulating film 26 is deposited on the entire surface and planarized by a chemical mechanical polishing process to expose the mask insulating film pattern 24. (See Figure 2A)

그 다음, 상기 게이트전극(23) 상부에서 비트라인 콘택으로 예정되는 부분을 노출시키는 제1비트라인 콘택마스크인 제1감광막패턴(27)을 형성한다. (도 2b 참조)Next, a first photoresist pattern 27, which is a first bit line contact mask that exposes a portion of the gate electrode 23 to be a bit line contact, is formed. (See Figure 2b)

다음, 상기 제1감광막패턴(27)을 식각마스크로 상기 마스크절연막패턴(24)을 소정 두께 식각하되, 상기 식각공정은 이온주입공정을 실시하고 습식식각공정을 실시하여 홈(28)을 형성한다. 상기 마스크절연막패턴(24)에 이온주입공정을 실시하여 막질을 손상시킨 후 습식식각공정을 실시함으로써 손상된 마스크절연막패턴(24)만을 제거할 수 있어 두께 조절이 용이하다.Next, the mask insulating layer pattern 24 is etched to a predetermined thickness using the first photoresist layer pattern 27 as an etch mask, and the etching process includes an ion implantation process and a wet etching process to form the grooves 28. . By performing an ion implantation process on the mask insulating film pattern 24 to damage the film quality and performing a wet etching process, only the damaged mask insulating film pattern 24 can be removed, thereby making it easy to adjust the thickness.

그 다음, 상기 제1감광막패턴(27)을 제거한다. (도 2c 참조)Next, the first photoresist pattern 27 is removed. (See Figure 2c)

다음, 전체표면 상부에 제2층간절연막(29)을 형성한다. 이때, 상기 제2층간절연막(29)은 상기 홈(28)을 완전히 매립시켜 홈(28) 상부에 단차가 형성된다. (도 2d 참조)Next, a second interlayer insulating film 29 is formed over the entire surface. At this time, the second interlayer insulating film 29 is completely filled with the groove 28 so that a step is formed on the groove 28. (See FIG. 2D)

그 다음, 상기 제2층간절연막(29) 상부에 상기 게이트전극(23) 상에서 비트라인 콘택으로 예정되는 부분과 반도체기판(20)의 접합영역(21) 상에서 비트라인 콘택으로 예정되는 부분을 노출시키는 제2비트라인 콘택마스크인 제2감광막패턴(30)을 형성한다.Next, a portion intended to be a bit line contact on the gate electrode 23 and a portion intended to be a bit line contact on the junction region 21 of the semiconductor substrate 20 are exposed on the second interlayer insulating layer 29. A second photoresist pattern 30, which is a second bit line contact mask, is formed.

그 후, 상기 제2감광막패턴(30)을 식각마스크로 상기 제2층간절연막(29), 제1층간절연막(26) 및 마스크절연막패턴(24)을 식각하여 비트라인 콘택홀(31, 32)을 형성한다. (도 2e 참조)Thereafter, the second interlayer insulating layer 29, the first interlayer insulating layer 26, and the mask insulating layer pattern 24 are etched using the second photoresist layer pattern 30 as an etch mask, thereby forming bit line contact holes 31 and 32. To form. (See Figure 2E)

그 후, 상기 제2감광막패턴(30)을 제거한다.Thereafter, the second photoresist layer pattern 30 is removed.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판의 접합영역에 형성되는 비트라인 콘택홀과 게이트전극 상부에 형성되는 비트라인 콘택홀을 형성하는 경우, 게이트전극 상에 적층되어 있는 마스크절연막패턴을 이온주입공정 후 습식식각하는 방법으로 소정 두께 제거한 다음, 비트라인 콘택홀을 형성함으로써 비트라인 콘택홀 형성 후 반도체기판의 접합영역이 손실되어 누설전류가 발생하는 것을 방지하고, 그에 소자의 공정 수율 및 동작특성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, when the bit line contact hole is formed in the junction region of the semiconductor substrate and the bit line contact hole is formed on the gate electrode, the semiconductor device is stacked on the gate electrode. After removing the predetermined thickness of the mask insulating film pattern by a method of wet etching after the ion implantation process, by forming a bit line contact hole, the junction region of the semiconductor substrate is lost after the bit line contact hole is formed to prevent leakage current There is an advantage of improving the process yield and operation characteristics of the device.

Claims (2)

반도체기판 상부에 게이트 절연막, 게이트전극용 도전층 및 마스크절연막의 적층구조를 형성하고, 게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막패턴, 게이트전극 및 게이트절연막패턴의 적층구조패턴을 형성하는 공정과,A stack structure of a gate insulating film, a conductive layer for a gate electrode, and a mask insulating film is formed on the semiconductor substrate, and the stack structure is etched by using a gate electrode mask as an etch mask to form a stack structure pattern of a mask insulating film pattern, a gate electrode, and a gate insulating film pattern. Forming process, 상기 적층구조패턴의 양쪽 반도체기판에 저농도 접합영역을 형성하고, 상기 적층구조패턴의 측벽에 절연막 스페이서를 형성하는 공정과,Forming a low concentration junction region on both semiconductor substrates of the laminated structure pattern, and forming insulating film spacers on sidewalls of the laminated structure pattern; 전체표면 상부에 제1층간절연막을 형성하고, 상기 마스크절연막패턴이 노출되도록 평탄화시키는 공정과,Forming a first interlayer insulating film over the entire surface, and planarizing the mask insulating film pattern to expose the mask insulating film pattern; 상기 게이트전극 상에서 비트라인 콘택으로 예정되는 부분을 노출시키는 제1비트라인 콘택마스크를 식각마스크로 상기 마스크절연막패턴을 소정 두께 제거하여 홈을 형성하는 공정과,Forming a groove by removing a predetermined thickness of the mask insulating layer pattern with an etch mask using a first bit line contact mask that exposes a portion intended to be a bit line contact on the gate electrode; 전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface; 상기 게이트전극 상에서 비트라인 콘택으로 예정되는 부분과 상기 반도체기판의 접합영역에서 비트라인 콘택으로 예정되는 부분을 노출시키는 제2비트라인 콘택마스크를 식각마스크로 상기 제2층간절연막, 제2층간절연막 및 마스크절연막패턴을 식각하여 비트라인 콘택홀을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 제조방법.The second interlayer dielectric layer, the second interlayer dielectric layer, and the second bit line contact mask exposing a portion intended for the bit line contact on the gate electrode and a portion intended for the bit line contact in the junction region of the semiconductor substrate are etch masks. And forming a bit line contact hole by etching the mask insulating layer pattern. 제 1 항에 있어서,The method of claim 1, 상기 홈은 상기 제1비트라인 콘택마스크를 식각마스크로 상기 마스크절연막패턴에 이온주입공정을 실시하여 막질을 손상시킨 다음, 습식식각공정을 실시하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The groove is formed by performing an ion implantation process on the mask insulating layer pattern using the first bit line contact mask as an etch mask to damage the film quality and then performing a wet etching process.
KR1020000036868A 2000-06-30 2000-06-30 Manufacturing method for semiconductor device KR20020002642A (en)

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